Re: gEDA-user: Polygons in PCB
I think their tools don't know the difference between vias and pins, and if you have any vias bigger than the smallest pin, it thinks you have tented pins. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
On Mon, Mar 08, 2010 at 09:47:55AM -0800, Anthony Shanks wrote: > Sorry that was a mis-statement. > > Is there anyway to place vias that have a soldermask clearance MORE than 0? What I typically do is to se all parameters of a via to be what I want, and then type "a" on top of the via to perform copies. This way I have very few types of vias. However, I have never used the autorouter (not of much use for microwave signals). Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
I just submitted a board to them a few weeks ago. When I uploaded my gerbers I got hundreds of warnings for having no soldermask clearance. I added their minimum clearance and all of the warnings were gone. Maybe technically since they were warnings its not required, but I didn't want to take a chance. Plus even if they didn't give me warnings, I don't want all my vias covered with soldermask. On Mon, Mar 8, 2010 at 10:03 AM, DJ Delorie wrote: > >> Why is that? > > Because nobody's changed it to do otherwise? > >> The board house I use (4pcb) requires soldermask clearance for vias. > > I use 4pcb and they do not require soldermask clearance for vias. > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
> Why is that? Because nobody's changed it to do otherwise? > The board house I use (4pcb) requires soldermask clearance for vias. I use 4pcb and they do not require soldermask clearance for vias. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
Why is that? The board house I use (4pcb) requires soldermask clearance for vias. I'm sure they are not the only ones. On Mon, Mar 8, 2010 at 9:49 AM, DJ Delorie wrote: > >> Is there anyway to place vias that have a soldermask clearance MORE >> than 0? > > The code for inserting new vias has a zero hard-coded in the function > call (action.c, look for CreateNewVia). > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
> Is there anyway to place vias that have a soldermask clearance MORE > than 0? The code for inserting new vias has a zero hard-coded in the function call (action.c, look for CreateNewVia). ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
Sorry that was a mis-statement. Is there anyway to place vias that have a soldermask clearance MORE than 0? By default, when I place a via, it has zero soldermask clearance. On Mon, Mar 8, 2010 at 9:40 AM, Gabriel Paubert wrote: > On Mon, Mar 08, 2010 at 09:18:56AM -0800, Anthony Shanks wrote: >> Is there a way to make a square polygon with round edges in pcb? >> > > Not to my knowledge, I have done it by cutting the corners at 45 degrees > and adding a non polycon-clearing zero length track at the corner (in one > case I also used an track drawn with the arc tool, but I don't remember > why, perhaps because there was a component pad/pin in the area). > >> One more unrelated question. Is there a way to place vias with a >> default soldermask clearance less than 0? > > Yes, I almost exclusively use tented vias. Enable the soldermask layer > and press Shift-K repeatedly until the via is fully covered. Or edit > the pcb source file, manually or with a script. > > Gabriel > > > ___ > geda-user mailing list > geda-user@moria.seul.org > http://www.seul.org/cgi-bin/mailman/listinfo/geda-user > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
On Mon, Mar 08, 2010 at 09:18:56AM -0800, Anthony Shanks wrote: > Is there a way to make a square polygon with round edges in pcb? > Not to my knowledge, I have done it by cutting the corners at 45 degrees and adding a non polycon-clearing zero length track at the corner (in one case I also used an track drawn with the arc tool, but I don't remember why, perhaps because there was a component pad/pin in the area). > One more unrelated question. Is there a way to place vias with a > default soldermask clearance less than 0? Yes, I almost exclusively use tented vias. Enable the soldermask layer and press Shift-K repeatedly until the via is fully covered. Or edit the pcb source file, manually or with a script. Gabriel ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Polygons in PCB
> Is there a way to make a square polygon with round edges in pcb? Manually? Sure. Use a zero-length line to form the round bits on an otherwise 8-sided polygon. > One more unrelated question. Is there a way to place vias with a > default soldermask clearance less than 0? Soldermask opening size is independent of copper size; "less than zero" means "smaller than no opening". ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
