Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
Peter TB Brett wrote: >> Or should I fire up gEDA on something smaller and less visible first? >> Anyone want to hold my hand while I do it? > > Smaller and less visible, first, I would say, +1 I went from protel to geda. My experience was: Both suites have their specific strengths and weaknesses. Personal work style adjusts as you get used to the tools. Coming from a different suite, the weaknesses are immediately obvious. The strengths need more time to be appreciated. ---<)kaimartin(> -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Monday 17 January 2011 18:30:35 Steve Wiseman wrote: > Or should I fire up gEDA on something smaller and less visible first? > Anyone want to hold my hand while I do it? Smaller and less visible, first, I would say, if only so that you can get a feel for whether gEDA/pcb lacks features *required* for the B4 design before committing to it. I do think it would be really useful to let Peter C sit in with you for a few hours just watching you work with Altium, too. Not only would that be valuable from the perspective of improving gEDA, but also from the point of view of determining whether gEDA can do what you need. Cheers, Peter -- Peter Brett Remote Sensing Research Group Surrey Space Centre signature.asc Description: This is a digitally signed message part. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
Hi, all. I am that person... Balloon4's design and layout is (at least partly) my baby. I'd like to do it in open tools, and for that, gEDA seems to be the only game in town. (Balloon4 is roughly credit card sized, and has a TI OMAP(3or4) SOC, Xilinx FPGA, power supplies, USB, Ethernet, camera, display interfaces - imagine a Beagle Board XM, with rather more stuff, in about half the space. There a few design challenges, other than the density - fast wide buses (DDR2/3 and others), balanced and impedance controlled USB and Ethernet lines, >Gbps MIPI buses, many power domains and planes. We need to be able to manufacture it reliably, in volume, and have it pass EMC standards. We don't have funds to do many aborted runs due to DRC oopses. We don't have time to burn. The project sponsor needs working boards.) Things in gEDA's favour: It exists, it works (in that people are generating boards), it's live and under active development and use. It's free. The autorouter is alleged to work. If I can usefully get other people to collaborate on the design, they don't need expensive tools. It would be great to have Balloon designed in open tools. (I'm a happy user of plenty of other open tools, and electronic design would be fine too. I'd be happy to chip in my Altium support money...) Things in Altium's favour: Momentum. I use it day in, day out. I can get stuff done in it, quickly and correctly, including boards of this complexity. I can import TI's Beagle or Panda reference designs and work from there. No need to generate schematic parts. PCB footprint generation is speedy, and has integrated 3D models. I also have large libraries of tried & tested components. (I do have a full Specctra autorouting license, but Altium's interactive router is my preferred layout scheme, on any but the most autorouter-friendly boards). >From a perspective of 'just getting it done and shipped', it's (to me) clearly going to be faster in Altium. I know the tools, I know the tools can do the job, and I can import the reference design. I've seen some reasonably complex boards done in gEDA - but have no idea how long they've taken. It's possible to do PCBs in MS-Paint or by cutting tape, given sufficient time, the tools just make things faster and less error-prone. So: Given the board spec, and the constraints, would _you_ say it's sane to use gEDA for this? I'd expect it to take 5-7 weeks end to end, in Altium, from spec to gerbers (with the usual level of spec revisions, datasheet reading, component unavailability, coffee drinking - or 3-4 weeks of uninterrupted work). Or should I fire up gEDA on something smaller and less visible first? Anyone want to hold my hand while I do it? Steve ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Sun, 2011-01-16 at 11:32 -0600, John Griessen wrote: > On 01/15/2011 06:32 AM, Bob Paddock wrote: > > git HEAD rendering speed alone > >> would make it prohibitive. > > I've been able to layout dense boards. The autorouter for digital wires after > the main power is laid out doesn't need rendering I mentioned the PCB auto-router in my earlier email, but when talking about rendering speed, I was just talking about how long it takes for PCB to draw a screen-update whilst manually editing the board. You and Bob seem to have thought I was concerned about rendering speed _during_ auto-routing. You still need to look at the auto-router results, even if you don't care about the intermediate steps ;) >From Bob's comments, it seems that perhaps Altium isn't as polished as I've imagined it is. There will still be momentum behind it though, due to: Tool familiarity amongst the designers The designers already bought Altium at some point Existing symbols / schematics which can be reused Production tested and optimised footprints > Belief more than logic seems to be what moves people to choose proprietary > over open tools. That is probably true. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Mon, 2011-01-17 at 08:11 +0100, Stephan Boettcher wrote: > > I'm lost.. who is Bob? > > You do not use a thread view in your mail reader, do you? Not normally, no.. and switching it on did clear things up. It looks like I completely missed Bob's email in the thread. I know who Bob Paddock is, but I thought John was talking about one of the Balloon developers. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Sat, 2011-01-15 at 01:42 +0100, Kai-Martin Knaak wrote: > Peter Clifton wrote: > > >> It is intended that these will be published in Altium format as that > >> is the CAD package of choice for the design process. > > Why not geda in the first place? I've mentioned some reasons in other emails - I'll let people know if I find out anything concrete. > >> However we will also explore the possibility of publishing the files > >> for one of the Open ECAD packages such as gEDA. > > How would the conversion be performed? Unclear at this point. > >> The BOHL will be modified to encompass this change and the onus will > >> be on organisations that decide to use the Balloon 4 design to make > >> the instantiations they create Open and available for purchase. > > Those who use the schematics are required to make the resulting device > available for purchase? How would this be enforced? That wording did strike me as odd. If I get talking to them, I'll ask about it. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
Peter Clifton writes: > On Sun, 2011-01-16 at 11:44 -0600, John Griessen wrote: >> On 01/16/2011 11:32 AM, John Griessen wrote: >> > So I don't see how that was a stopper, even without Bill's specific Altium >> > experience. >> >> I meant Bob's > > I'm lost.. who is Bob? You do not use a thread view in your mail reader, do you? -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Jan 17, 2011, at 1:09 AM, al davis wrote: > If simulation means Spice to you, you are 20 years behind. > If Verilog means only digital to you, you are 20 years behind. And yet, the infrastructure and community support for Verilog as more than a digital tool are far poorer than for SPICE. Thus, its advantages remain largely theoretical rather than practical. > Are we proud of being 20 years behind? There's no inherent virtue in "newer". Users of the Pythagorean Theorem are 2500 years behind, but of course there's nothing wrong with that. The virtue comes from using what works. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
> I'm lost.. who is Bob? You're uncle? (sorry, couldn't resist) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Sun, 2011-01-16 at 11:44 -0600, John Griessen wrote: > On 01/16/2011 11:32 AM, John Griessen wrote: > > So I don't see how that was a stopper, even without Bill's specific Altium > > experience. > > I meant Bob's I'm lost.. who is Bob? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
al davis wrote: >> Graphics information would be lost during the process. > Yes .. you missed something. Verilog has a structural part too, > which is well documented, has a published standard, and > completely adequate for this. Hmm, "structural" in the context of verilog always seemed to mean "description by gates" rather than "description by behavior". That is, you are still stuck with expressions like (a NAND NOT b) AND (b OR c) But no geometry information on where to put the gates in a schematic representation. Maybe we just misunderstand each other. ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On 01/16/2011 02:43 PM, Patrick Doyle wrote: I'm somewhat confused by the twist things took here -- how does this tie into gnucap? Are you requesting a plugin that would produce a gschem schematic, given a gnucap internal representation? Yes, I think that's one of the translator plugins Al wants. When you also have one for gEDA gschem, then you have a 2-way translator for Altium <--> gschem. JG ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Fri, Jan 14, 2011 at 8:59 PM, al davis wrote: >> >> However we will also explore the possibility of publishing >> >> the files for one of the Open ECAD packages such as gEDA. >> >> How would the conversion be performed? > > That's obvious. They are waiting for us to provide a conversion > utility. > > Let me ask for help again. .. Gnucap has a conversion facility > based on Verilog syntax. If someone writes a plugin for geda > format (which I have already asked for), and someone else writes > one for Altium format, we have that translator. I tuned into this thread late (i.e. just now). I used Altium once for a small board design, and played with it off and on after that. It has a scripting language. In theory, one could write a script to enumerate all of the objects on a schematic and produce a gschem compatible output file. In theory, one could write a script to enumerate all of the objects on a layout and produce a PCB compatible output file. In theory, there is no difference between theory and practice. In practice, there is. I'm somewhat confused by the twist things took here -- how does this tie into gnucap? Are you requesting a plugin that would produce a gschem schematic, given a gnucap internal representation? That seems like a reasonable request... I'd like to take a shot at it, as it dovetails into my own interest. (Having said that, I should also say that I'd like to have the time and focus to be able to take a shot at this... we'll see how well that works out.) Are you also suggesting a plugin that would parse an Altium schematic and map it into the internal gnucap representation? I think that's more problematic, for the file format compatibility reasons others mentioned later in this thread. However, an Altium script to translate an Altium schematic into a verilog netlist (and perhaps back again) does seem like a pretty useful utility. Perhaps Altium already has one of these. Or am I missing something here? --wpd ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On 01/16/2011 11:32 AM, John Griessen wrote: So I don't see how that was a stopper, even without Bill's specific Altium experience. I meant Bob's ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On 01/15/2011 06:32 AM, Bob Paddock wrote: git HEAD rendering speed alone would make it prohibitive. I've been able to layout dense boards. The autorouter for digital wires after the main power is laid out doesn't need rendering So I don't see how that was a stopper, even without Bill's specific Altium experience. Back when it was called protel, a friend using it said, "it's great when it works.." Belief more than logic seems to be what moves people to choose proprietary over open tools. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Sunday 16 January 2011, John Griessen wrote: > On 01/15/2011 10:36 PM, al davis wrote: > > Unless I massively missed something, verilog is completely > > procedural. > > Really verilog is all in parallel, not procedural code, > unless you want to put some in with special features that > are trickier to use than everyday verilog. > > The basic statement of verilog is assign, which defines wires > and connectivity of busses of wires and renamings and logical > combinations of wire values... Much like a graphical > schematic. > > Modules also map names in verilog, allowing reuse of subcells > with different names for wires inside them. You are thinking of the original Verilog, as it was in its first draft from Cadence over 20 years ago. Today, Verilog means a family of languages with common syntax that do just about everything in electronics. There is System Verilog, Verilog-A, Verilog-AMS, The insiders refer to the old digital verilog alone as "Verilog-D". If simulation means Spice to you, you are 20 years behind. If Verilog means only digital to you, you are 20 years behind. Are we proud of being 20 years behind? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On 01/15/2011 10:36 PM, al davis wrote: Unless I massively missed something, verilog is completely procedural. Really verilog is all in parallel, not procedural code, unless you want to put some in with special features that are trickier to use than everyday verilog. The basic statement of verilog is assign, which defines wires and connectivity of busses of wires and renamings and logical combinations of wire values... Much like a graphical schematic. Modules also map names in verilog, allowing reuse of subcells with different names for wires inside them. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Saturday 15 January 2011, Kai-Martin Knaak wrote: > I don't see how this could possibly work. Both, gschem and > altium contain a graphical representation of the circuit. > Unless I massively missed something, verilog is completely > procedural. Graphics information would be lost during the > process. Yes .. you missed something. Verilog has a structural part too, which is well documented, has a published standard, and completely adequate for this. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Saturday 15 January 2011, Kai-Martin Knaak wrote: > I looked at lang_verilog_in.cc > Unfortunately, my c++ is not fluent enough to read the code > right away. This is aggravated by the lack of comments on > what the various code blocks do. Since I also don't know > verilog by heart, the whole file looks more like a puzzle. > Sorry, but this fruit is hanging too high for me. (You can > call me programming coward) > Is there a comprehensive specification, what gnucap expects > to get from the import plugin? If so, it might make a > gschem import component a lot easier. I started to write up things like that: http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual:tech:plugins but then other things came up so I didn't have time to do more. If somebody actually wants to help, wants to write a language plugin, I will work with you and complete the documentation. The interaction is a necessary part of completing the work. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
> a) They have Altium > b) They have bits in Altium already (footprints etc..) -> momentum. > c) They need an auto-router which can handle really complex stuff. Hun? Three of us at work have spent weeks trying to get Altium's autorouter to do much at all, and do it correctly when it does, and finally gave up. As far I can tell the native Altium router is just there to irritate you enough to force your boss into spending the money for their high end optional router. The autorouter in PCB 'just works'. > d) Blind / buried vias may be needed. Which is why I still endure Altium. I know there is a build of PCB 'out there' that does have the patch applied for this. > No-one could in good conscience suggest PCB is going to be able to > compete up with that sort of design. I must be unconscious, as I use both regularly. PCB has its faults, mostly in the user interface, where Altium the faults are everyplace. For example there are multiple places to set up the printer. Some of the places work, some of the places interact with the other places, some places do nothing, and in the end you may or may not get what you wanted on the printer. My favorite is move a schematic from one place to an other, or even open the same schematic with the same version of Altium after reinstalling it due to a hard disk failure, and all of the schematic symbols now have 'dots' in them that you can't get rid of without redoing the schematic for every symbol. > git HEAD rendering speed alone > would make it prohibitive. You don't turn on the Altium's autorouter's 'show trials' unless your goal is to goof off. > Not necessarily.. but whatever happens, it may well be beneficial to the > community as a whole. I've never had much luck with Altium's own Import/Export working in trying to go between that and PADS. Seems like they really don't want it to work. You also have to know what version of Altium is being talked about because the proprietary file formats have changed over the years, in ways that are not backwards compatible with older versions. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Fri, 2011-01-14 at 20:59 -0500, al davis wrote: > Anyone here who uses LTspice need only to look in the mirror to > figure that out. Apparently, there are some features that > Altium has that they consider to be important. What are they? Will get back to you when I know more, but having chatted to these guys in the past: a) They have Altium b) They have bits in Altium already (footprints etc..) -> momentum. c) They need an auto-router which can handle really complex stuff. d) Blind / buried vias may be needed. No-one could in good conscience suggest PCB is going to be able to compete up with that sort of design. git HEAD rendering speed alone would make it prohibitive. > > How would the conversion be performed? > > That's obvious. They are waiting for us to provide a conversion > utility. Not necessarily.. but whatever happens, it may well be beneficial to the community as a whole. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
al davis wrote: > On Friday 14 January 2011, Kai-Martin Knaak wrote: >> Peter Clifton wrote: > > No. David Bisset wrote, on another list. Peter just passed it > on to us. > >> >> It is intended that these will be published in Altium >> >> format as that is the CAD package of choice for the >> >> design process. >> >> Why not geda in the first place? > > Anyone here who uses LTspice need only to look in the mirror to > figure that out. They apparently decided, to issue the schematics in geda format. This is unlike the simulation case, where it is not intended to redo the simulation in gnucap or ngspice. (BTW, I switched to qucs lately) > Apparently, there are some features that > Altium has that they consider to be important. What are they? That's why I asked. >> >> However we will also explore the possibility of publishing >> >> the files for one of the Open ECAD packages such as gEDA. >> >> How would the conversion be performed? > > That's obvious. They are waiting for us to provide a conversion > utility. Unless something has dramatically changed since I last checked, altium file format is completely inaccessible from outside. From the inside you'd have to sign strict NDAs. > > Let me ask for help again. .. Gnucap has a conversion facility I looked at lang_verilog_in.cc Unfortunately, my c++ is not fluent enough to read the code right away. This is aggravated by the lack of comments on what the various code blocks do. Since I also don't know verilog by heart, the whole file looks more like a puzzle. Sorry, but this fruit is hanging too high for me. (You can call me programming coward) Is there a comprehensive specification, what gnucap expects to get from the import plugin? If so, it might make a gschem import component a lot easier. > based on Verilog syntax. If someone writes a plugin for geda > format (which I have already asked for), and someone else writes > one for Altium format, we have that translator. I don't see how this could possibly work. Both, gschem and altium contain a graphical representation of the circuit. Unless I massively missed something, verilog is completely procedural. Graphics information would be lost during the process. ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
On Friday 14 January 2011, Kai-Martin Knaak wrote: > Peter Clifton wrote: No. David Bisset wrote, on another list. Peter just passed it on to us. > >> It is intended that these will be published in Altium > >> format as that is the CAD package of choice for the > >> design process. > > Why not geda in the first place? Anyone here who uses LTspice need only to look in the mirror to figure that out. Apparently, there are some features that Altium has that they consider to be important. What are they? > >> However we will also explore the possibility of publishing > >> the files for one of the Open ECAD packages such as gEDA. > > How would the conversion be performed? That's obvious. They are waiting for us to provide a conversion utility. Let me ask for help again. .. Gnucap has a conversion facility based on Verilog syntax. If someone writes a plugin for geda format (which I have already asked for), and someone else writes one for Altium format, we have that translator. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
Peter Clifton wrote: >> It is intended that these will be published in Altium format as that >> is the CAD package of choice for the design process. Why not geda in the first place? >> However we will also explore the possibility of publishing the files >> for one of the Open ECAD packages such as gEDA. How would the conversion be performed? >> The BOHL will be modified to encompass this change and the onus will >> be on organisations that decide to use the Balloon 4 design to make >> the instantiations they create Open and available for purchase. Those who use the schematics are required to make the resulting device available for purchase? How would this be enforced? ---<)kaimartin(>--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: FYI [Fwd: [Balloon] Balloon 4]
Forwarded Message > From: David Bisset > Reply-to: da...@itechnic.co.uk > To: ball...@balloonboard.org > Subject: [Balloon] Balloon 4 > Date: Fri, 14 Jan 2011 18:30:41 - > > There has been a flurry of activity over the last few months trying to > see what sort of design might constitute Balloon 4. > > > > There is now an agreement with Toby Churchill Ltd that will fund the > development of an Open Hardware board based around their requirements > for an embedded processor to replace Balloon 3. > > > > We are still trying to decide on a processor but current thinking is > that it should be based on OMAP 3. > > This will allow us to tap into a vast amount of open source hardware > and software expertise. > > > > The emphasis will remain on designing an embeddable processor board > with good accessible IO and onboard programmable logic. > > > > Because the design intent is that the board will be embedded into > products it is important that any IO can be broken out to standard > connectors off board. > > > > The design team would welcome suggestions of what to include, and what > not to include, given that we wish to differentiate from other boards > in the market, and that the board will be used in products that will > have to gain CE mark approvals. > > *It is not our intent to design yet another netbook.* > > > > One major change from the way that the Balloon 3 project worked has > also been agreed. > > > > For Balloon 4 we will open the design at the schematic level, > publishing the schematic designs and full PCB design files. > > It is intended that these will be published in Altium format as that > is the CAD package of choice for the design process. > > However we will also explore the possibility of publishing the files > for one of the Open ECAD packages such as gEDA. > > This will allow third parties to develop their own instantiations of > the Balloon 4 design. > > > > This move recognises the fact that the barrier to production is the > finance required to get a PCB like this into production and the > expertise needed to design and debug it, rather than the IP in the > design. > > > > It is intended that the schematic design will be created as modular > blocks and that these will be published individually. > > Each block will then be tagged with a confidence level indicating the > level of prototyping, manufacturing and testing that has been applied > to it. In this way others can contribute modules at a schematic level > without breaking the core design. > > > > For this reason the term “Balloon 4” will now refer to the collection > of schematic design modules rather than a specific PCB instantiation. > > The BOHL will be modified to encompass this change and the onus will > be on organisations that decide to use the Balloon 4 design to make > the instantiations they create Open and available for purchase. > > > > Any comments and thoughts are welcome, both on the design and the more > open design approach. > > > > David Bisset > > > > > > __ Information from ESET Smart Security, version of virus > signature database 5788 (20110114) __ > > The message was checked by ESET Smart Security. > > http://www.eset.com > ___ > Balloon mailing list > ball...@balloonboard.org > http://balloonboard.org/mailman/listinfo/balloon -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
