Re: gEDA-user: Next problem, PCB looses rats
On Tue, 08 Jun 2010 00:32:09 +0100, Peter Clifton wrote: >> Do we use alt for anything else? Would alt-click interfere with window >> managers? > > Metacity / compiz have that as a short-cut for dragging windows around. With metacity this is configurable: MainMenu -> System -> Windows -> MovementKey This setting can be either "Alt", or "Super (Windows logo)" I don't know about compiz but expect it to be configurable , too. If the proposed modified drag is caught with some settings of some window managers then the affected users are in the same situation like now. Everybody else would gain a shortcut to a frequently needed action. ---<)kaimartin(>--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmk&op=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
Hm - doing that and throwing that knowledge away once the mouse hovers over
something else - I can't believe it's implemented like this.
And there must be at least 2 lists to be able to detect a shorting
of copper traces e.g. when moving a part. The rats optimizer needs the
information for all nets (btw. I think it has some flaws anyway - it doesn't
find the shortes connection in some cases, not even considering only the
endpoints of trace-segments)
Keeping one list of trace segments, polygons and pads per net would be
a natural solution. In that case the solution of copper islands is trivial:
keep them in a "not connected" list and allow to connect to such a segment.
If the segment changes net, treat it as new drawn to see what it touches...
The implementation must be present already to resolve the situation
after turning off/on the DRC. Just the handling of the contact needs to be
different: the "not connected" net would need to "virtually" belong to
the current net {if (netToTest == currentNet || netToTest == 0) ...}.
If the trace really gets connected, the portion with real contact has to
be split out.
If the traces belonging to nothing are not in a single list but disjoint
areas are in separate lists each, it's even simpler:
{if (netToTest == currentNet || netToTest < 0) ...} assuming there is an
internal net-number and net-listed nets have positiv, dangling nets have
negative numbers.
Thinking of practical routing, the question is, whether silently connecting
random copper fields to a random trace is really as desirable as it
looks when running into the off/on hassle while knowing what one does.
So making this potential feature configurable or requireing a shortcut-key
to be able to move onto dangling nets is probably due.
HTH, Armin
kai-martin knaak wrote:
Armin Faltl wrote:
If the copper traces have no idea of a net (or vice versa), how does the
positive test work, i.e. why is it possible to connect anything at all
despite there is a DRC?
A wild guess in the dark: The algorithm internally builds a list ob objects
connected to the currently drawn track. Everything else is to be avoided by
a margin.
---<)kaimartin(>---
___
geda-user mailing list
geda-user@moria.seul.org
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
Armin Faltl wrote: > If the copper traces have no idea of a net (or vice versa), how does the > positive test work, i.e. why is it possible to connect anything at all > despite there is a DRC? A wild guess in the dark: The algorithm internally builds a list ob objects connected to the currently drawn track. Everything else is to be avoided by a margin. ---<)kaimartin(>--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
On Tue, 08 Jun 2010 01:13:08 +0200, kai-martin knaak wrote: > DJ Delorie wrote: > >>> ack. The necessity to deactivate auto-DRC is a crutch. Does the internal >>> representation prevent this to be fixed? >> >> Yup. It's based on touch/no-touch tests, not "which net" tests, since >> we don't associate nets with copper. > > Then how about making the crutch easier to handle: > "Press [alt] while drawing a track to temporarily disable auto-DRC" There is already a kind of kludge to do this: * enable "Auto DRC" * select the "Line"-tool (important, the "Line"-tool has to be activated first, it normally clears the "found"-flag) * press on the copper which you want to reach * draw the line from some other copper to the "found" copper I hope this helps, perhaps there should be an entry in the FAQ? Or is it a bug? -- mit freundlichem Gruss Christian Riggenbach ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
If the copper traces have no idea of a net (or vice versa), how does the positive test work, i.e. why is it possible to connect anything at all despite there is a DRC? DJ Delorie wrote: ack. The necessity to deactivate auto-DRC is a crutch. Does the internal representation prevent this to be fixed? Yup. It's based on touch/no-touch tests, not "which net" tests, since we don't associate nets with copper. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
On Mon, 2010-06-07 at 19:14 -0400, DJ Delorie wrote: > Do we use alt for anything else? Would alt-click interfere with > window managers? Metacity / compiz have that as a short-cut for dragging windows around. Compiz eats almost all the Meta + ... operations, along with Alt+Scroll, and various other combinations. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
Do we use alt for anything else? Would alt-click interfere with window managers? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
DJ Delorie wrote: >> ack. The necessity to deactivate auto-DRC is a crutch. Does the internal >> representation prevent this to be fixed? > > Yup. It's based on touch/no-touch tests, not "which net" tests, since > we don't associate nets with copper. Then how about making the crutch easier to handle: "Press [alt] while drawing a track to temporarily disable auto-DRC" ---<)kaimartin(>--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
> ack. The necessity to deactivate auto-DRC is a crutch. Does the internal > representation prevent this to be fixed? Yup. It's based on touch/no-touch tests, not "which net" tests, since we don't associate nets with copper. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
Armin Faltl wrote: > There is one known shortcoming with PCB (iirc): if you create a "copper > island" somewhere, that is a copper area not connected to anything with > a know net, this gets a hidden ID and is not treated as undefined. ack. The necessity to deactivate auto-DRC is a crutch. Does the internal representation prevent this to be fixed? ---<)kaimartin(>--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=get&search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
I found where I have moved a component slightly a caused a short between ground an power. I got all that fixed. But every time I start to run the power buss, I reach a point where pins are highlighted green, but the rat lines disappear, and the DRC makes it impossible to run a trace to the pin. I have to keep saving the layout, exiting the program, and starting over. Even reloading the net list and displaying the rat lines does not help. This is slowing things down quit a bit. But I don't think I can build a 4 layer board at home, and with only two layers, there is no ground an power planes, so I want the power and ground lines thick and well laid out, so I don't want to rey autorouting just yet. What I am doing wrong this time There is one known shortcoming with PCB (iirc): if you create a "copper island" somewhere, that is a copper area not connected to anything with a know net, this gets a hidden ID and is not treated as undefined. So if you layout a strip of copper you intend to become part of e.g. ground later, once you want to connect it to a known ground you have to turn off auto-DRC for this one connection. As long as that area is not shorted to anything else the next rats-optimization should show no trouble. Don't forget to turn on auto-DRC again after the deliberate "forced shorting". HTH, Armin ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
On Mon, 2010-05-31 at 15:14 -0700, Mike Bushroe wrote: > OK, I have the layout. I found that some symbols don't have explicit OR >implicit power connections. Others use VDD and VSS instead of Vcc and >GND. I found where I have moved a component slightly a caused a short >between ground an power. I got all that fixed. But every time I start >to run the power buss, I reach a point where pins are highlighted >green, but the rat lines disappear, and the DRC makes it impossible to ^___ not sure why, perhaps you hit "e" for erase rats? >run a trace to the pin. I have to keep saving the layout, exiting the >program, and starting over. Even reloading the net list and displaying >the rat lines does not help. This is slowing things down quit a bit. ^___ If you hit "o" for optimize rats, to re-show the rats, does that help? If not... try switching off Settings->"Auto enforce DRC clearance". That will stop the DRC checker getting in the way of routing tracks. If the board isn't confidential, perhaps send it (or a snippet) along with instructions to reproduce the problem, and someone will take a look to see what the problem might be. Best wishes, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Next problem, PCB looses rats
On May 31, 2010, at 4:14 PM, Mike Bushroe wrote: > OK, I have the layout. I found that some symbols don't have explicit OR > implicit power connections. Yep. The authors no doubt intended that they be used with separate power symbols. > Others use VDD and VSS instead of Vcc and > GND. Yep. Different authors, different conventions, different purposes, different flows, ... You have to check your symbols before you use them. That's also true of the big $$ commercial packages. Symbols are pretty universally trouble in EDA. > I found where I have moved a component slightly a caused a short > between ground an power. I got all that fixed. But every time I start > to run the power buss, I reach a point where pins are highlighted > green, but the rat lines disappear, and the DRC makes it impossible to > run a trace to the pin. I have to keep saving the layout, exiting the > program, and starting over. Even reloading the net list and displaying > the rat lines does not help. This is slowing things down quit a bit. > But I don't think I can build a 4 layer board at home, and with only > two layers, there is no ground an power planes, so I want the power and > ground lines thick and well laid out, so I don't want to rey > autorouting just yet. What I am doing wrong this time? You'll have to find a pcb expert, I don't use it. Different purposes, different flows, ... John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: Next problem, PCB looses rats
OK, I have the layout. I found that some symbols don't have explicit OR implicit power connections. Others use VDD and VSS instead of Vcc and GND. I found where I have moved a component slightly a caused a short between ground an power. I got all that fixed. But every time I start to run the power buss, I reach a point where pins are highlighted green, but the rat lines disappear, and the DRC makes it impossible to run a trace to the pin. I have to keep saving the layout, exiting the program, and starting over. Even reloading the net list and displaying the rat lines does not help. This is slowing things down quit a bit. But I don't think I can build a 4 layer board at home, and with only two layers, there is no ground an power planes, so I want the power and ground lines thick and well laid out, so I don't want to rey autorouting just yet. What I am doing wrong this time? Mike ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
