input validation (was: gEDA-user: pcb refdes name restrictions?)
Hi, Moving this thread to geda-dev... El vie, 03-11-2006 a las 12:47 +, Peter Clifton escribió: [snip] > Peter B and I were looking at the possibility of introducing some > plugable input validation / auto-complete modules into the gschem > attribute editing system. The down side of course, is these must be > configured (by default if you will) to understand what attributes are > necessary, and what is legal. I was thinking about this for a while before you post this mail... My two wishes are: 1) gschem should know what attributes can have a given object (and hide the rest in the attribute editor window). Example: if editing the attributes of a net, don't show the refdes, slot,... attributes as options in the drop down menu. 2) user configurable input validation (both for the content of the attribute, as well as attribute bounds (don't allow to set slot=5 for a part with only 2 slots), and object checking (don't allow to set the refdes attribute for a net, for example). At that time, I thought to: 1) add a scheme function which takes an object list (a list with the objects selected), and returned the common attributes of all the objects. This would be used to fill the attribute name list in the attribute editor. Of course we need a way to define the object type an attribute can be attached to, but that's a simple problem. 2) add a new scheme function to check the attribute. When the user adds a new attribute, call this function, which would return a string showing the problem description. Thus, an error window can be raised, and the message and checks are user configurable. A general regular expression can be defined for each attribute as well as any other check function. > One idea was "footprint" (assuming your config states that validation > and auto-complete for this attribute should be for "PCB", not some other > layout package). > > The user setting the footprint attribute would auto-complete with a > drop-down list of the available footprints - obviously requires a > knowledge of how / where PCB finds its footprint lists, or a library > interface to this functionality in PCB. The validation method described above relies on scheme, and maybe it's not as flexible and powerful as you may want. I don't see how to do the PCB stuff that way. Do you have some thoughts about how to do it? Regards, Carlos ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Peter Clifton wrote: > The user setting the footprint attribute would auto-complete with a drop-down list of the available footprints This would be useful. The insertion of proper footprint names in gattrib is currently the slowest part (for me anyway) of going from gschem to PCB. Another thought was even to (optionally) bring up the PCB footprint window with a GUI preview. (Suitably library'fied if possible to avoid code duplication) This would be useful. Phil Taylor ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Fri, 2006-11-03 at 09:57 +, Peter Baxendale wrote: > > >The parser starts at the end, moving towards the start of the string and > > >strips off lower case characters until it encounters any non-lowercase > > >character, then it stops. Thus Rp4 will be a valid element name. This > > >has been documented in the manual for at least 5 years now since I first > > >wrote that code. From the pcb manual: > > > > It might be useful to put this information in gEDA/gaf's attribute > > guide under refdes as well. Filed bug to remind us: > > Yes, thanks, that's a good idea. It's at the schematic entry stage when > you're choosing refdes values, so it would be handy to mention it there, > even though strictly it's a pcb issue, not gEDA/gaf. Sorry I missed the > pcb manual bit - I could have saved myself and others some time and also > some noise on this list if I'd seen it. Whilst this statement may be controversial, I'm inclined to believe that anything you have to dig deep into a manual to discover isn't obvious enough in the program :). There are of course exceptions, as no-one expects a complicated EDA package to be learnt solely through feeling your way around the gui.. it simply isn't productive to do so. OTOH, this is how beginners learn, and was exactly how I started. I like to see what people trip over in real life. Even if there is an "answer" in a manual somewhere, perhaps there is a better way. Amusing aside: a few times I found myself poking at the source to see if I could implement a feature / behaviour in PCB / gschem, only to find it was there already and I just didn't know how to activate it! Now, the source-code is my manual! I had a great computer science teacher at A-Level... when you took a program to her for testing, rather than inputting the proper numbers (which as a developer, you do), she would randomly press all the keyboard keys until something broke. A great lesson in input validation! Peter B and I were looking at the possibility of introducing some plugable input validation / auto-complete modules into the gschem attribute editing system. The down side of course, is these must be configured (by default if you will) to understand what attributes are necessary, and what is legal. One idea was "footprint" (assuming your config states that validation and auto-complete for this attribute should be for "PCB", not some other layout package). The user setting the footprint attribute would auto-complete with a drop-down list of the available footprints - obviously requires a knowledge of how / where PCB finds its footprint lists, or a library interface to this functionality in PCB. Another thought was even to (optionally) bring up the PCB footprint window with a GUI preview. (Suitably library'fied if possible to avoid code duplication) I already have too much work backed up to get on with this right now, but if people feed back that this might be useful, it will go higher on the todo pile. (Right after finishing the DBus support in PCB and making xgsch2pcb place nice with it). Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> >The parser starts at the end, moving towards the start of the string and > >strips off lower case characters until it encounters any non-lowercase > >character, then it stops. Thus Rp4 will be a valid element name. This > >has been documented in the manual for at least 5 years now since I first > >wrote that code. From the pcb manual: > > It might be useful to put this information in gEDA/gaf's attribute > guide under refdes as well. Filed bug to remind us: Yes, thanks, that's a good idea. It's at the schematic entry stage when you're choosing refdes values, so it would be handy to mention it there, even though strictly it's a pcb issue, not gEDA/gaf. Sorry I missed the pcb manual bit - I could have saved myself and others some time and also some noise on this list if I'd seen it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
[snip] >The parser starts at the end, moving towards the start of the string and >strips off lower case characters until it encounters any non-lowercase >character, then it stops. Thus Rp4 will be a valid element name. This >has been documented in the manual for at least 5 years now since I first >wrote that code. From the pcb manual: It might be useful to put this information in gEDA/gaf's attribute guide under refdes as well. Filed bug to remind us: http://sourceforge.net/tracker/index.php?func=detail&aid=1589700&group_id=161080&atid=818426 -Ales ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On 10/31/06, Peter Clifton <[EMAIL PROTECTED]> wrote: We run a robot design project, subdivided into mechanical, electrical and software components. The electronics is done basically on strip board, but that is a sub-section on our PCB(s) with micro-controller interfaces ready to populate. I am one of the demonstrators for the electronics part of the lab, and the desire is (from the project's leader) that the students use gschem or similar to draw their schematics. We aren't yet at the stage where these students build custom PCBs, however various ideas for rapid prototyping (miniature milling setups) have been discussed as a future possibility. Peter, When Dr. Long was at the Freedog meeting in August he gave out copies of an MDP DVD (Version 0.5.8 Beta). Is that DVD (or a more recent version) available for download? (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Dan McMahill wrote: It had never occurred to me to use anything but an upper case alpha character followed by a numeric value for a refdes, but students have a habit of trying the unexpected. It threw me for quite a while trying to understand what pcb was complaining about, since it referred to a "CONN" part which wasn't in either the schematic or the pcb netlist or the pcb file. Now I know about the lower case feature I'll know what to look for next time. Correct me if I'm wrong, but only lower case at the end of a refdes is ignored by pcb (but not by gsch2pcb), so something like Rp4 is ok. I'd have to look. The test would be to load a netlist and then look in the .pcb file. Or look at the netlist parser. The parser starts at the end, moving towards the start of the string and strips off lower case characters until it encounters any non-lowercase character, then it stops. Thus Rp4 will be a valid element name. This has been documented in the manual for at least 5 years now since I first wrote that code. From the pcb manual: If a NAME ends with a lower-case letter, all lower-case letters are stripped from the end of the NAME to determine the matching layout-name name. For example: Data U1-3 U2abc-4 FLOP1a-7 Uabc3-A9 specifies that the net called "Data" should have pin 3 of U1 connected to pin 4 of U2, to pin 7 of FLOP1 and to pin A9 of Uabc3. Note that element name and pin number strings are case-sensitive. It is up to you to name the elements so that their layout-name names agrees with the netlist. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Tue, 2006-10-31 at 13:00 +, Peter Baxendale wrote: > > I am curious to know if your notes are available online, or are released > > under such a license that we can make them available to students here? > > > > I've put them on my web page > ( http://www.durham.ac.uk/peter.baxendale ). They are pdfs but I can > send you openoffice files if they are any use to you. They are just > brief notes to support a simple assignment (4x2 hour sessions) so you > may find them a bit basic. I'd be interested in hearing your own > experiences using geda with students. Aha... I am a student myself actually (just starting a PhD), so have no direct experience with teaching gEDA. My own experience was that the learning curve is initially steep, but having got to grips with it, I find it far nicer than other EDA packages I've used. To keep things simpler, we try and provide symbols and footprints for all parts which students might be expected to use. We run a robot design project, subdivided into mechanical, electrical and software components. The electronics is done basically on strip board, but that is a sub-section on our PCB(s) with micro-controller interfaces ready to populate. I am one of the demonstrators for the electronics part of the lab, and the desire is (from the project's leader) that the students use gschem or similar to draw their schematics. We aren't yet at the stage where these students build custom PCBs, however various ideas for rapid prototyping (miniature milling setups) have been discussed as a future possibility. I'll show the notes to Dr. Long, who is in charge of the robot design project. The draw, simulate, layout exercise looks a lot like the sort of thing he was suggesting for more general ECAD teaching. Regards -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Dan McMahill wrote: Stuart Brorson wrote: Note that you can't do this with things like CONNpower and CONNsignal. How do you renumber alpha refdeses? Admittedly, CONNpower and the like are easier to deal with than J1, J2, etc, but if you've got a board with thousands of components on it, then you can't give each a unique alpha refdes, and the above renumbering scheme is extremely convenient. Since we can't do backanno in gschem/PCB, this point is moot, however. We're pretty close to being able to do that. You can renumber automatically in PCB and it produces a file that with probably only a few minutes of perl hacking could be used to back annotate to gschem. Actually, I'll see if I have any energy left after halloween activities tonight to code up something. Since there is already a perl program for backannotating from pads all that has to change is the parser and that should be easy. ok, actually spent 10 minutes and cranked it out. gaf/utils/scripts/pcb_backannotate is in CVS. Any feedback would be appreciated. To use, *make a scratch copy of your design first*. Please don't mess up your active copy and blame me! If you use cvs or subversion or whatever, its a good time to check in your work first so you can undo all of these changes globally. open up your layout, run the pcb action :Renumber() and give a log file name. PCB will renumber your footprints and record its actions in the log file. Now run pcb_backannotate [--verbose] renumber_log_file pg1.sch [pg2.sch ...] and hopefully all of your changes will be back annotated. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> I am curious to know if your notes are available online, or are released > under such a license that we can make them available to students here? > I've put them on my web page ( http://www.durham.ac.uk/peter.baxendale ). They are pdfs but I can send you openoffice files if they are any use to you. They are just brief notes to support a simple assignment (4x2 hour sessions) so you may find them a bit basic. I'd be interested in hearing your own experiences using geda with students. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Peter Baxendale wrote: Thanks for the comment on refdes values. I'll add a few things to next year's notes for the students. I'll try to remember to modify gsch2pcb. The framework exists in gnetlist to include rules about the name space of the output format and deal with it. For example, pads seems to convert everything to upper case so the pads backend currently converts everything to upper case as part of netlisting. Note that there is some extra magic that makes sure you don't create shorts by moving to a more restrictive name space. It had never occurred to me to use anything but an upper case alpha character followed by a numeric value for a refdes, but students have a habit of trying the unexpected. It threw me for quite a while trying to understand what pcb was complaining about, since it referred to a "CONN" part which wasn't in either the schematic or the pcb netlist or the pcb file. Now I know about the lower case feature I'll know what to look for next time. Correct me if I'm wrong, but only lower case at the end of a refdes is ignored by pcb (but not by gsch2pcb), so something like Rp4 is ok. I'd have to look. The test would be to load a netlist and then look in the .pcb file. Or look at the netlist parser. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Stuart Brorson wrote: Note that you can't do this with things like CONNpower and CONNsignal. How do you renumber alpha refdeses? Admittedly, CONNpower and the like are easier to deal with than J1, J2, etc, but if you've got a board with thousands of components on it, then you can't give each a unique alpha refdes, and the above renumbering scheme is extremely convenient. Since we can't do backanno in gschem/PCB, this point is moot, however. We're pretty close to being able to do that. You can renumber automatically in PCB and it produces a file that with probably only a few minutes of perl hacking could be used to back annotate to gschem. Actually, I'll see if I have any energy left after halloween activities tonight to code up something. Since there is already a perl program for backannotating from pads all that has to change is the parser and that should be easy. -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Tue, 2006-10-31 at 10:04 +, Peter Baxendale wrote: > Thanks for the comment on refdes values. I'll add a few things to next > year's notes for the students. We're hoping to introduce more students to gEDA here at Cambridge, and as a related project, myself and Peter Brett spent our summers programming improvements for gschem (and PCB, but nothing user visible). I am curious to know if your notes are available online, or are released under such a license that we can make them available to students here? > It had never occurred to me to use anything but an upper case alpha > character followed by a numeric value for a refdes, but students have a > habit of trying the unexpected. It threw me for quite a while trying to > understand what pcb was complaining about, since it referred to a "CONN" > part which wasn't in either the schematic or the pcb netlist or the pcb > file. Now I know about the lower case feature I'll know what to look for > next time. > > Correct me if I'm wrong, but only lower case at the end of a refdes is > ignored by pcb (but not by gsch2pcb), so something like Rp4 is ok. That should be fine. Incidentally, we wrote / are writing a GTK frontend to gsch2pcb, since we identified this as one area where the workflow in gEDA isn't all that friendly to new users. It isn't stable enough for production use yet, but once we've got some back-end features improved in PCB (a patch to allow communication via DBus), we should be in a position to make a more formal release of the code. Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
Thanks for the comment on refdes values. I'll add a few things to next year's notes for the students. It had never occurred to me to use anything but an upper case alpha character followed by a numeric value for a refdes, but students have a habit of trying the unexpected. It threw me for quite a while trying to understand what pcb was complaining about, since it referred to a "CONN" part which wasn't in either the schematic or the pcb netlist or the pcb file. Now I know about the lower case feature I'll know what to look for next time. Correct me if I'm wrong, but only lower case at the end of a refdes is ignored by pcb (but not by gsch2pcb), so something like Rp4 is ok. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Mon, 30 Oct 2006, John Luciani wrote: On 10/30/06, Peter Baxendale <[EMAIL PROTECTED]> wrote: Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. A reason not to have long refdes values is clutter. Names that are seven and eight characters get difficult to place (legibly) on dense schematics and PCBs. A seven character refdes will probably take up more board area than most of you SMD components. I'll add a second reason. In a very common design flow, you first create a schematic with refdeses R1, R2, R3, C1, C2, C3, etc. Then you lay out the board. Then when the layout is done, the layout engineer *renumbers* the refdeses from e.g. upper left to lower right. The new refdeses are then backannotated into the final schematic. The idea is that refdeses with similar number all lie close to each other so that when it comes time to service the board (or during DVT) you can more easily find the components. Note that you can't do this with things like CONNpower and CONNsignal. How do you renumber alpha refdeses? Admittedly, CONNpower and the like are easier to deal with than J1, J2, etc, but if you've got a board with thousands of components on it, then you can't give each a unique alpha refdes, and the above renumbering scheme is extremely convenient. Since we can't do backanno in gschem/PCB, this point is moot, however. Stuart ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> Any lower case suffix is ignored. This is so you can, for example, place > 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and > they will netlist into a single footprint / component, U1. > Ah, thanks - that explains exactly what I was seeing - CONNpower became CONN. > I'm not sure of any other restrictions. Spaces are probably unwise " ", > but I've not tested that. The students tried that - as you'd expect, spaces are a bad idea. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
> A reason not to have long refdes values is clutter. Names that are seven and > eight characters get difficult to place (legibly) on dense schematics and > PCBs. A seven character refdes will probably take up more board area than most > of you SMD components. Yes, I agree entirely. What I meant was that I was surprised that pcb doesn't work with this kind of refdes. For instance, Ja doesn't work either. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On 10/30/06, Peter Baxendale <[EMAIL PROTECTED]> wrote: Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. A reason not to have long refdes values is clutter. Names that are seven and eight characters get difficult to place (legibly) on dense schematics and PCBs. A seven character refdes will probably take up more board area than most of you SMD components. I usually use Jn for connectors. If I want to label a connector "power" or "signal" I will add labels to the schematic and PCB. It is usually easier to place two smaller strings (neatly) than one large one. (* jcl *) -- http://www.luciani.org ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb refdes name restrictions?
On Mon, 2006-10-30 at 13:59 +, Peter Baxendale wrote: > Another dumb question. I teach a class of undergraduates about ECAD and > this year abandoned commercial tools in favour of geda. Students being > students, they tend to try things I wouldn't think of doing. Today, a > couple of them decided to be creative and on their schematic used names > like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it > unconventional and probably inadvisable, I couldn't offhand see why they > shouldn't do that. > > Gsch2pcb happily produced a netlist and pcb file which both looked fine, > as far as I could tell. But when loaded into pcb, optimising the netlist > causes error messages such as "Can't find CONN pin 4 called for in > netlist". > > So does pcb require that all reference designators be in the form of a > string followed by a numerical value? If so, are there any other refdes > restrictions I should know about? Given time, they're bound to find > them... > > Thanks, > PB Any lower case suffix is ignored. This is so you can, for example, place 4 discrete NAND gates on the schematic called U1a, U1b, U1c and U1d, and they will netlist into a single footprint / component, U1. (The NAND symbols are "slotted", you set the 4 gates to a different slot number - with the "slot" attribute, and they will each netlist to the correct pins in the final package.) So... don't use lowercase suffixes, also: Don't use the hyphen character "-", in the refdes, as it upsets the M4 macro language used to process generating the footprints. (I think "_" is ok. I'm not sure of any other restrictions. Spaces are probably unwise " ", but I've not tested that. Regards -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb refdes name restrictions?
Another dumb question. I teach a class of undergraduates about ECAD and this year abandoned commercial tools in favour of geda. Students being students, they tend to try things I wouldn't think of doing. Today, a couple of them decided to be creative and on their schematic used names like "CONNpower" and "CONNsignal" for refdes values. Whilst I thought it unconventional and probably inadvisable, I couldn't offhand see why they shouldn't do that. Gsch2pcb happily produced a netlist and pcb file which both looked fine, as far as I could tell. But when loaded into pcb, optimising the netlist causes error messages such as "Can't find CONN pin 4 called for in netlist". So does pcb require that all reference designators be in the form of a string followed by a numerical value? If so, are there any other refdes restrictions I should know about? Given time, they're bound to find them... Thanks, PB ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
