[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13521 )
Change subject: arch-arm: Add initial support for SVE gather/scatter
loads/stores
..
arch-arm: Add initial support for SVE gather/scatter loads/stores
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13521
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
A src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
7 files changed, 1,403 insertions(+), 100 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/sve_macromem.hh
b/src/arch/arm/insts/sve_macromem.hh
new file mode 100644
index 000..a31af9b
--- /dev/null
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#ifndef __ARCH_ARM_SVE_MACROMEM_HH__
+#define __ARCH_ARM_SVE_MACROMEM_HH__
+
+#include "arch/arm/generated/decoder.hh"
+#include "arch/arm/insts/pred_inst.hh"
+
+namespace ArmISA {
+
+template class MicroopType>
+class SveIndexedMemVI : public PredMacroOp
+{
+ protected:
+IntRegIndex dest;
+IntRegIndex gp;
+IntRegIndex base;
+uint64_t imm;
+
+ public:
+SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
+IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+uint64_t _imm)
+: PredMacroOp(mnem, machInst, __opClass),
+ dest(_dest), gp(_gp), base(_base), imm(_imm)
+{
+bool isLoad = (__opClass == MemReadOp);
+
+int num_elems = ((machInst.sveLen + 1) * 16) / sizeof(RegElemType);
+
+numMicroops = num_elems;
+if (isLoad) {
+numMicroops++;
+}
+
+microOps = new StaticInstPtr[numMicroops];
+
+StaticInstPtr *uop = microOps;
+
+if (isLoad) {
+// The first microop of a gather load copies the source vector
+// register used for address calculation to an auxiliary
register,
+// with all subsequent microops reading from the latter. This
is
+// needed to properly handle cases where the source vector
+// register is the same as the destination register
+*uop = new ArmISAInst::SveGatherLoadCpySrcVecMicroop(
+mnem, machInst, _base, this);
+uop++;
+}
+
+for (int i = 0; i < num_elem
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 to look at the new patch set (#8). Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm: Add initial support for SVE gather/scatter loads/stores Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli --- A src/arch/arm/insts/sve_macromem.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa M src/arch/arm/isa/templates/sve_mem.isa M src/arch/arm/registers.hh 7 files changed, 1,403 insertions(+), 100 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Gerrit-Change-Number: 13521 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Andreas Sandberg Gerrit-CC: Jason Lowe-Power Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 to look at the new patch set (#7). Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm: Add initial support for SVE gather/scatter loads/stores Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/decoder.hh M src/arch/arm/insts/misc64.cc A src/arch/arm/insts/sve_macromem.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa M src/arch/arm/isa/templates/sve_mem.isa M src/arch/arm/registers.hh 9 files changed, 1,405 insertions(+), 101 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Gerrit-Change-Number: 13521 Gerrit-PatchSet: 7 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-CC: Andreas Sandberg Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Giacomo Travaglini has uploaded a new patch set (#5) to the change originally created by Giacomo Gabrielli. ( https://gem5-review.googlesource.com/c/public/gem5/+/13521 ) Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm: Add initial support for SVE gather/scatter loads/stores In addition to the code for implementing decoding and execution of these instructions, a couple of additional features have been implemented: 1. a mechanism to skip the memory access part of a load/store operation - used by gather loads for implementing zeroing predication; 2. the Arm decoder was augmented in a previous changeset to keep track of the active SVE vector length - this feature is now used by gather/scatter operations to determine the right number of microops to be generated. Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/decoder.hh A src/arch/arm/insts/sve_macromem.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa M src/arch/arm/isa/templates/sve_mem.isa M src/arch/arm/registers.hh M src/arch/isa_parser.py M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/exec_context.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/simple/exec_context.hh M src/cpu/simple_thread.hh M src/cpu/thread_context.hh 18 files changed, 1,491 insertions(+), 107 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Gerrit-Change-Number: 13521 Gerrit-PatchSet: 5 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Giacomo Travaglini has uploaded a new patch set (#4) to the change originally created by Giacomo Gabrielli. ( https://gem5-review.googlesource.com/c/public/gem5/+/13521 ) Change subject: arch-arm: Add initial support for SVE gather/scatter loads/stores .. arch-arm: Add initial support for SVE gather/scatter loads/stores In addition to the code for implementing decoding and execution of these instructions, a couple of additional features have been implemented: 1. a mechanism to skip the memory access part of a load/store operation - used by gather loads for implementing zeroing predication; 2. the Arm decoder was augmented in a previous changeset to keep track of the active SVE vector length - this feature is now used by gather/scatter operations to determine the right number of microops to be generated. Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Signed-off-by: Giacomo Gabrielli --- M src/arch/arm/decoder.hh A src/arch/arm/insts/sve_macromem.hh M src/arch/arm/isa/formats/sve_2nd_level.isa M src/arch/arm/isa/includes.isa M src/arch/arm/isa/insts/sve_mem.isa M src/arch/arm/isa/operands.isa M src/arch/arm/isa/templates/sve_mem.isa M src/arch/arm/registers.hh M src/arch/isa_parser.py M src/cpu/base_dyn_inst.hh M src/cpu/base_dyn_inst_impl.hh M src/cpu/checker/cpu.hh M src/cpu/exec_context.hh M src/cpu/minor/exec_context.hh M src/cpu/o3/lsq_unit_impl.hh M src/cpu/simple/exec_context.hh M src/cpu/simple_thread.hh M src/cpu/thread_context.hh 18 files changed, 1,491 insertions(+), 107 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13521 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2 Gerrit-Change-Number: 13521 Gerrit-PatchSet: 4 Gerrit-Owner: Giacomo Gabrielli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add initial support for SVE gather/scatter loads/stores
Giacomo Gabrielli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13521
Change subject: arch-arm: Add initial support for SVE gather/scatter
loads/stores
..
arch-arm: Add initial support for SVE gather/scatter loads/stores
In addition to the code for implementing decoding and execution of
these instructions, a couple of additional features have been
implemented:
1. a mechanism to skip the memory access part of a load/store
operation - used by gather loads for implementing zeroing
predication;
2. the Arm decoder was augmented in a previous changeset to keep track
of the active SVE vector length - this feature is now used by
gather/scatter operations to determine the right number of microops to
be generated.
Change-Id: I891623015b47a39f61ed616f8896f32a7134c8e2
Signed-off-by: Giacomo Gabrielli
---
M src/arch/arm/decoder.hh
A src/arch/arm/insts/sve_macromem.hh
M src/arch/arm/isa/formats/sve_2nd_level.isa
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa/insts/sve_mem.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/isa/templates/sve_mem.isa
M src/arch/arm/registers.hh
M src/arch/isa_parser.py
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
18 files changed, 1,491 insertions(+), 107 deletions(-)
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index f44a981..45b1e2b 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
diff --git a/src/arch/arm/insts/sve_macromem.hh
b/src/arch/arm/insts/sve_macromem.hh
new file mode 100644
index 000..7cad9a6
--- /dev/null
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Giacomo Gabrielli
+ */
+
+#ifndef __ARCH_ARM_SVE_MACROMEM_HH__
+#define __ARCH_ARM_SVE_MACROMEM_HH__
+
+#include "arch/arm/generated/decoder.hh"
+#include "arch/arm/insts/pred_inst.hh"
+
+namespace ArmISA {
+
+template class MicroopType>
+class SveIndexedMemVI : public PredMacroOp
+{
+ protected:
+IntRegIndex dest;
+IntRegIndex gp;
+IntRegIndex base;
+uint64_t imm;
+
+ public:
+SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass
__opClass,
+IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+uint64_t _imm)
+: PredMacroOp(mnem, machInst, __opClass),
+ dest(_dest), gp(_gp), base(_base), imm(_imm)
+{
+bool
