[RFC PATCH v4 9/9] arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/configs/zx_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/zx_defconfig b/arch/arm/configs/zx_defconfig index b200bb0..ab683fb 100644 --- a/arch/arm/configs/zx_defconfig +++ b/arch/arm/configs/zx_defconfig @@ -83,7 +83,6 @@ CONFIG_MMC=y CONFIG_MMC_UNSAFE_RESUME=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_EXT2_FS=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 0/9]
Add external dma support for Synopsys MSHC Synopsys DesignWare mobile storage host controller supports three types of transfer mode: pio, internal dma and external dma. However, dw_mmc can only supports pio and internal dma now. Thus some platforms using dw-mshc integrated with generic dma can't work in dma mode. So we submit this patch to achieve it. And the config option, CONFIG_MMC_DW_IDMAC, was added by Will Newton (commit:f95f3850) for the first version of dw_mmc and never be touched since then. At that time dt-bindings hadn't been introduced into dw_mmc yet means we should select CONFIG_MMC_DW_IDMAC to enable internal dma mode at compile time. Nowadays, device-tree helps us to support a variety of boards with one kernel. That's why we need to remove it and decide the transfer mode by reading dw_mmc's HCON reg at runtime. This RFC patch needs lots of ACKs. I know it's hard, but it does need someone to make the running. Patch does the following things: - remove CONFIG_MMC_DW_IDMAC config option - add bindings for edmac used by synopsys-dw-mshc at runtime - add edmac support for synopsys-dw-mshc Patch is based on next of git://git.linaro.org/people/ulf.hansson/mmc Changes in v4: - remove "host->trans_mode" and use "host->use_dma" to indicate transfer mode. - remove all bt-bindings' changes since we don't need new properities. - check transfer mode at runtime by reading HCON reg - spilt defconfig changes for each sub-architecture - fix the title of cover letter - reuse some code for reducing code size Changes in v3: - choose transfer mode at runtime - remove all CONFIG_MMC_DW_IDMAC config option - add supports-idmac property for some platforms Changes in v2: - Fix typo of dev_info msg - remove unused dmach from declaration of dw_mci_dma_slave Shawn Lin (9): mmc: dw_mmc: Add external dma interface support Documentation: synopsys-dw-mshc: add bindings for idmac and edmac mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC arm: zx_defconfig: remove CONFIG_MMC_DW_IDMAC .../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 25 ++ arch/arc/configs/axs101_defconfig | 1 - arch/arc/configs/axs103_defconfig | 1 - arch/arc/configs/axs103_smp_defconfig | 1 - arch/arm/configs/exynos_defconfig | 1 - arch/arm/configs/hisi_defconfig| 1 - arch/arm/configs/lpc18xx_defconfig | 1 - arch/arm/configs/multi_v7_defconfig| 1 - arch/arm/configs/zx_defconfig | 1 - arch/mips/configs/pistachio_defconfig | 1 - drivers/mmc/host/Kconfig | 11 +- drivers/mmc/host/dw_mmc-pltfm.c| 2 + drivers/mmc/host/dw_mmc.c | 258 + include/linux/mmc/dw_mmc.h | 27 ++- 14 files changed, 257 insertions(+), 75 deletions(-) -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 1/9] mmc: dw_mmc: Add external dma interface support
DesignWare MMC Controller can supports two types of DMA
mode: external dma and internal dma. We get a RK312x platform
integrated dw_mmc and ARM pl330 dma controller. This patch add
edmac ops to support these platforms. I've tested it on RK312x
platform with edmac mode and RK3288 platform with idmac mode.
Signed-off-by: Shawn Lin
---
Changes in v4:
- remove "host->trans_mode" and use "host->use_dma" to indicate
transfer mode.
- remove all bt-bindings' changes since we don't need new properities.
- check transfer mode at runtime by reading HCON reg
- spilt defconfig changes for each sub-architecture
- fix the title of cover letter
- reuse some code for reducing code size
Changes in v3:
- choose transfer mode at runtime
- remove all CONFIG_MMC_DW_IDMAC config option
- add supports-idmac property for some platforms
Changes in v2:
- Fix typo of dev_info msg
- remove unused dmach from declaration of dw_mci_dma_slave
drivers/mmc/host/Kconfig| 11 +-
drivers/mmc/host/dw_mmc-pltfm.c | 2 +
drivers/mmc/host/dw_mmc.c | 258
include/linux/mmc/dw_mmc.h | 27 -
4 files changed, 232 insertions(+), 66 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 6a0f9c7..a86c0eb 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -607,15 +607,7 @@ config MMC_DW
help
This selects support for the Synopsys DesignWare Mobile Storage IP
block, this provides host support for SD and MMC interfaces, in both
- PIO and external DMA modes.
-
-config MMC_DW_IDMAC
- bool "Internal DMAC interface"
- depends on MMC_DW
- help
- This selects support for the internal DMAC block within the Synopsys
- Designware Mobile Storage IP block. This disables the external DMA
- interface.
+ PIO, internal DMA mode and external DMA modes.
config MMC_DW_PLTFM
tristate "Synopsys Designware MCI Support as platform device"
@@ -644,7 +636,6 @@ config MMC_DW_K3
tristate "K3 specific extensions for Synopsys DW Memory Card Interface"
depends on MMC_DW
select MMC_DW_PLTFM
- select MMC_DW_IDMAC
help
This selects support for Hisilicon K3 SoC specific extensions to the
Synopsys DesignWare Memory Card Interface driver. Select this option
diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index ec6dbcd..7e1d13b 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -59,6 +59,8 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
host->pdata = pdev->dev.platform_data;
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ /* Get registers' physical base address */
+ host->phy_regs = (void *)(regs->start);
host->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(host->regs))
return PTR_ERR(host->regs);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 40e9d8e..5d6cdff 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -56,7 +56,7 @@
#define DW_MCI_FREQ_MAX2 /* unit: HZ */
#define DW_MCI_FREQ_MIN40 /* unit: HZ */
-#ifdef CONFIG_MMC_DW_IDMAC
+
#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
@@ -99,7 +99,6 @@ struct idmac_desc {
__le32 des3; /* buffer 2 physical address */
};
-#endif /* CONFIG_MMC_DW_IDMAC */
static bool dw_mci_reset(struct dw_mci *host);
static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
@@ -403,7 +402,6 @@ static int dw_mci_get_dma_dir(struct mmc_data *data)
return DMA_FROM_DEVICE;
}
-#ifdef CONFIG_MMC_DW_IDMAC
static void dw_mci_dma_cleanup(struct dw_mci *host)
{
struct mmc_data *data = host->data;
@@ -441,12 +439,21 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
mci_writel(host, BMOD, temp);
}
-static void dw_mci_idmac_complete_dma(struct dw_mci *host)
+static void dw_mci_dmac_complete_dma(void *arg)
{
+ struct dw_mci *host = arg;
struct mmc_data *data = host->data;
dev_vdbg(host->dev, "DMA complete\n");
+ if (host->use_dma == TRANS_MODE_EDMAC)
+ if (data && (data->flags & MMC_DATA_READ))
+ /* Invalidate cache after read */
+ dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
+ data->sg,
+ data->sg_len,
+ DMA_FROM_DEVICE);
+
host->dma_ops->cleanup(host);
/*
@@ -527,7 +534,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host,
struct mmc_data *data,
Re: [PATCH 00/11] omap_hsmmc: voltage switching and tuning
* Kishon Vijay Abraham I [150805 08:03]: > Hi, > > On Wednesday 05 August 2015 04:13 PM, Tony Lindgren wrote: > > * Kishon Vijay Abraham I [150730 00:49]: > >> Patch series implements voltage switching and tuning for omap_hsmmc > >> driver. > >> > >> Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM, > >> Beaglebone black, OMAP5 uEVM and OMAP4 PANDA. > > > > Your tests are missing omap3? > > I don't have one at my disposal :-( I'll try to find one and add omap3 tests. Great :) Beagle xm is a good one to test the USB PHY stuff on and also MMC. Having USB cable connected or EHCI loaded blocks the PM though, so NFSroot is not very usable for testing on it. If you want to test PM over NFSroot, boards with the smsc911x known to work with PM are at least omap3-evm-37xx.dts and logicpd-torpedo-37xx-devkit.dts. Since you tinker with the USB PHYs, torpedo has MUSB working the same way as the beagle boards, EVM I think can be modified that way but by default has diffent PHY. Also overo tobi boards work with PM but only for retntion idle and not off idle, and map3-sbc-t3517.dts probably can be made to work with PM but I have mine as a gateway and have not been able to test with it. Probably also zoom3 boards with later processor boards can be made to work, the LDP has early omap34xx variants and can't be made to work reliably. I don't have omap3-lilly, but I'd assume that can also be made to work with PM if not already working. > > I suggest you add some omap3 tests in general as otherwise you are > > only testing a subset of the driver features and completely missing > > things like rutnime PM and save and restore for the deeper idle > > states. > > yeah, I'll do those tests and re-post the series. Thanks! Tony -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 8/9] arm: multi_v7_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/configs/multi_v7_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5fd8df6..a3734b5 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -520,7 +520,6 @@ CONFIG_MMC_ATMELMCI=y CONFIG_MMC_MVSDIO=y CONFIG_MMC_SDHI=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_ROCKCHIP=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 6/9] arm: hisi_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/configs/hisi_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig index 5997dbc..b2e340b 100644 --- a/arch/arm/configs/hisi_defconfig +++ b/arch/arm/configs/hisi_defconfig @@ -69,7 +69,6 @@ CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y CONFIG_RTC_CLASS=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_PLTFM=y CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 7/9] arm: lpc18xx_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/configs/lpc18xx_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig index 1c47f86..b7e8cda 100644 --- a/arch/arm/configs/lpc18xx_defconfig +++ b/arch/arm/configs/lpc18xx_defconfig @@ -119,7 +119,6 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_MMC=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_PCA9532=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 4/9] arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arc/configs/axs101_defconfig | 1 - arch/arc/configs/axs103_defconfig | 1 - arch/arc/configs/axs103_smp_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arc/configs/axs101_defconfig b/arch/arc/configs/axs101_defconfig index 562dac6..c92c0ef 100644 --- a/arch/arc/configs/axs101_defconfig +++ b/arch/arc/configs/axs101_defconfig @@ -89,7 +89,6 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y diff --git a/arch/arc/configs/axs103_defconfig b/arch/arc/configs/axs103_defconfig index 83a6d8d..cfac24e 100644 --- a/arch/arc/configs/axs103_defconfig +++ b/arch/arc/configs/axs103_defconfig @@ -95,7 +95,6 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y diff --git a/arch/arc/configs/axs103_smp_defconfig b/arch/arc/configs/axs103_smp_defconfig index f1e1c84..9922a11 100644 --- a/arch/arc/configs/axs103_smp_defconfig +++ b/arch/arc/configs/axs103_smp_defconfig @@ -96,7 +96,6 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT3_FS=y CONFIG_EXT4_FS=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 5/9] arm: exynos_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/arm/configs/exynos_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 9504e77..7e4af6e 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -161,7 +161,6 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S3C=y CONFIG_MMC_SDHCI_S3C_DMA=y CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_EXYNOS=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MAX77686=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 3/9] mips: pistachio_defconfig: remove CONFIG_MMC_DW_IDMAC
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin --- Changes in v4: None Changes in v3: None Changes in v2: None arch/mips/configs/pistachio_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig index 1646cce..013c62c 100644 --- a/arch/mips/configs/pistachio_defconfig +++ b/arch/mips/configs/pistachio_defconfig @@ -257,7 +257,6 @@ CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_TEST=m CONFIG_MMC_DW=y -CONFIG_MMC_DW_IDMAC=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_RTC_CLASS=y -- 2.3.7 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC PATCH v4 2/9] Documentation: synopsys-dw-mshc: add bindings for idmac and edmac
synopsys-dw-mshc supports three types of transfer mode. We add
bindings and description for how to use them at runtime.
Signed-off-by: Shawn Lin
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 25 ++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
index 346c609..8636f5a 100644
--- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt
@@ -75,6 +75,12 @@ Optional properties:
* vmmc-supply: The phandle to the regulator to use for vmmc. If this is
specified we'll defer probe until we can find this regulator.
+* dmas: List of DMA specifiers with the controller specific format as described
+ in the generic DMA client binding. Refer to dma.txt for details.
+
+* dma-names: request names for generic DMA client binding. Must be "rx-tx".
+ Refer to dma.txt for details.
+
Aliases:
- All the MSHC controller nodes should be represented in the aliases node using
@@ -95,6 +101,23 @@ board specific portions as listed below.
#size-cells = <0>;
};
+[board specific internal DMA resources]
+
+ dwmmc0@1220 {
+ clock-frequency = <4>;
+ clock-freq-min-max = <40 2>;
+ num-slots = <1>;
+ broken-cd;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ vmmc-supply = <&buck8>;
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+[board specific generic DMA request binding]
+
dwmmc0@1220 {
clock-frequency = <4>;
clock-freq-min-max = <40 2>;
@@ -106,4 +129,6 @@ board specific portions as listed below.
bus-width = <8>;
cap-mmc-highspeed;
cap-sd-highspeed;
+ dmas = <&pdma 12>;
+ dma-names = "rx-tx";
};
--
2.3.7
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[PATCH] mmc: Kconfig: Add dependency on GPIOLIB for MMC_SDHCI
Add GPIOLIB dependency for MMC_SDHCI. Problem was observed after adding the patch "mmc: sdhci-of-arasan: Call OF parsing for MMC" (sha1: 16b23787fc709fe60c5d2bd05927b1a3da33d4e9) which calls mmc_of_parse() -> mmc_gpiod_request_cd() (slot-gpio.c) which calls devm_gpiod_get_index() which returns -ENOSYS. Error log: sdhci-arasan ff16.sdhci: parsing dt failed (4294967258) sdhci-arasan: probe of ff16.sdhci failed with error -38 Signed-off-by: Michal Simek --- After RFC here https://lkml.org/lkml/2015/7/24/371 adding dependency on MMC_SDHCI. --- drivers/mmc/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index fd9a58e216a5..5519803c124b 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -38,6 +38,7 @@ config MMC_PXA config MMC_SDHCI tristate "Secure Digital Host Controller Interface support" depends on HAS_DMA + depends on GPIOLIB help This selects the generic Secure Digital Host Controller Interface. It is used by manufacturers such as Texas Instruments(R), Ricoh(R) -- 2.3.5 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] mmc: dw_mmc: Fix coding style issues
Hi, Shawn.
Applied this patch at my dw-mmc tree.
I will request pull on this weekend.
Thanks a lot!
Best Regards,
Jaehoon Chung
On 08/03/2015 04:07 PM, Shawn Lin wrote:
> This patch fixes the following issues reported by checkpatch.pl:
> - use -EINVAL instead of -ENOSYS, to fix warning message:
>"ENOSYS means 'invalid syscall nr' and nothing else"
> - split lines whose length is greater than 80 characters
> - avoid quoted string split across lines
> - use min_t instead of min, to fix warning message:
>"min() should probably be min_t(int, cnt, host->part_buf_count)"
> - fix missing a blank line after declarations
>
> Signed-off-by: Shawn Lin
>
> ---
>
> Changes in v2:
> - Keep consistency of comments
> - Rebase on https://patchwork.kernel.org/patch/6672581
>
> drivers/mmc/host/dw_mmc.c | 90
> +--
> 1 file changed, 56 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index e41fb74..3f070d9 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -238,8 +238,8 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc,
> struct mmc_command *cmd)
> struct dw_mci *host = slot->host;
> const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
> u32 cmdr;
> - cmd->error = -EINPROGRESS;
>
> + cmd->error = -EINPROGRESS;
> cmdr = cmd->opcode;
>
> if (cmd->opcode == MMC_STOP_TRANSMISSION ||
> @@ -374,7 +374,7 @@ static void dw_mci_start_command(struct dw_mci *host,
>cmd->arg, cmd_flags);
>
> mci_writel(host, CMDARG, cmd->arg);
> - wmb();
> + wmb(); /* drain writebuffer */
> dw_mci_wait_while_busy(host, cmd_flags);
>
> mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
> @@ -383,6 +383,7 @@ static void dw_mci_start_command(struct dw_mci *host,
> static inline void send_stop_abort(struct dw_mci *host, struct mmc_data
> *data)
> {
> struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
> +
> dw_mci_start_command(host, stop, host->stop_cmdr);
> }
>
> @@ -467,6 +468,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host,
> struct mmc_data *data,
> {
> unsigned int desc_len;
> int i;
> +
> if (host->dma_64bit_address == 1) {
> struct idmac_desc_64addr *desc_first, *desc_last, *desc;
>
> @@ -474,6 +476,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host,
> struct mmc_data *data,
>
> for (i = 0; i < sg_len; i++) {
> unsigned int length = sg_dma_len(&data->sg[i]);
> +
> u64 mem_addr = sg_dma_address(&data->sg[i]);
>
> for ( ; length ; desc++) {
> @@ -518,6 +521,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host,
> struct mmc_data *data,
>
> for (i = 0; i < sg_len; i++) {
> unsigned int length = sg_dma_len(&data->sg[i]);
> +
> u32 mem_addr = sg_dma_address(&data->sg[i]);
>
> for ( ; length ; desc++) {
> @@ -557,7 +561,7 @@ static void dw_mci_translate_sglist(struct dw_mci *host,
> struct mmc_data *data,
> desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
> }
>
> - wmb();
> + wmb(); /* drain writebuffer */
> }
>
> static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
> @@ -575,6 +579,7 @@ static void dw_mci_idmac_start_dma(struct dw_mci *host,
> unsigned int sg_len)
> temp |= SDMMC_CTRL_USE_IDMAC;
> mci_writel(host, CTRL, temp);
>
> + /* drain writebuffer */
> wmb();
>
> /* Enable the IDMAC */
> @@ -622,7 +627,9 @@ static int dw_mci_idmac_init(struct dw_mci *host)
> host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
>
> /* Forward link the descriptor list */
> - for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++,
> p++) {
> + for (i = 0, p = host->sg_cpu;
> + i < host->ring_size - 1;
> + i++, p++) {
> p->des3 = cpu_to_le32(host->sg_dma +
> (sizeof(struct idmac_desc) * (i + 1)));
> p->des1 = 0;
> @@ -751,7 +758,7 @@ static void dw_mci_adjust_fifoth(struct dw_mci *host,
> struct mmc_data *data)
> u32 fifo_width = 1 << host->data_shift;
> u32 blksz_depth = blksz / fifo_width, fifoth_val;
> u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
> - int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
> + int idx = ARRAY_SIZE(mszs) - 1;
>
> tx_wmark = (host->fifo_depth) / 2;
> tx_wmark_invers = host->fifo_depth - tx_wmark;
> @@ -876,6 +883,7 @@ static int dw_mci_submit_data_dma(struct dw_mci *host,
> struct mmc_data *data)
> static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
> {
> unsigned long irqflags;
Re: [PATCH] mmc: dw_mmc: fix pio mode when internal dmac is enabled
Hi, Heiko.
Applied this patch at my dw-mmc tree.
I will request pull on this weekend.
Thanks a lot!
Best Regards,
Jaehoon Chung
On 08/04/2015 12:04 AM, Heiko Stübner wrote:
> The dw_mci_init_dma() may decide to not use dma, but pio instead, caused
> by things like wrong dma settings in the system.
>
> Till now the code dw_mci_init_slot() always assumed that dma is available
> when CONFIG_MMC_DW_IDMAC was defined, ignoring the host->use_dma var
> set during dma init.
>
> So when now the dma init failed for whatever reason, the transfer sizes
> would still be set for dma transfers, especially including the maximum
> block-count calculated from host->ring_size and resulting in a
>
> [4.991109] [ cut here ]
> [4.99] kernel BUG at drivers/mmc/core/core.c:256!
> [4.991113] Internal error: Oops - BUG: 0 [#1] SMP ARM
>
> because host->ring_size is 0 in this case and the slot init code uses
> the wrong code to calculate the values.
>
> Fix this by selecting the correct calculations using the host->use_dma
> variable instead of the CONFIG_MMC_DW_IDMAC config option.
>
> Signed-off-by: Heiko Stuebner
> ---
> drivers/mmc/host/dw_mmc.c | 27 ++-
> 1 file changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
> index 40e9d8e..9ec3521 100644
> --- a/drivers/mmc/host/dw_mmc.c
> +++ b/drivers/mmc/host/dw_mmc.c
> @@ -2391,19 +2391,20 @@ static int dw_mci_init_slot(struct dw_mci *host,
> unsigned int id)
> mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
> } else {
> /* Useful defaults if platform data is unset. */
> -#ifdef CONFIG_MMC_DW_IDMAC
> - mmc->max_segs = host->ring_size;
> - mmc->max_blk_size = 65536;
> - mmc->max_seg_size = 0x1000;
> - mmc->max_req_size = mmc->max_seg_size * host->ring_size;
> - mmc->max_blk_count = mmc->max_req_size / 512;
> -#else
> - mmc->max_segs = 64;
> - mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
> - mmc->max_blk_count = 512;
> - mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
> - mmc->max_seg_size = mmc->max_req_size;
> -#endif /* CONFIG_MMC_DW_IDMAC */
> + if (host->use_dma) {
> + mmc->max_segs = host->ring_size;
> + mmc->max_blk_size = 65536;
> + mmc->max_seg_size = 0x1000;
> + mmc->max_req_size = mmc->max_seg_size * host->ring_size;
> + mmc->max_blk_count = mmc->max_req_size / 512;
> + } else {
> + mmc->max_segs = 64;
> + mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
> + mmc->max_blk_count = 512;
> + mmc->max_req_size = mmc->max_blk_size *
> + mmc->max_blk_count;
> + mmc->max_seg_size = mmc->max_req_size;
> + }
> }
>
> if (dw_mci_get_cd(mmc))
>
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[PATCH] mmc: host: use of_property_bool()
Use more compact of_property_read_bool() calls instead of the of_find_property()
calls.
Signed-off-by: Sergei Shtylyov
---
The patch is against Ulf Hansson's 'mmc.git' repo's 'next' branch.
drivers/mmc/core/host.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
Index: mmc/drivers/mmc/core/host.c
===
--- mmc.orig/drivers/mmc/core/host.c
+++ mmc/drivers/mmc/core/host.c
@@ -398,7 +398,7 @@ int mmc_of_parse(struct mmc_host *host)
{
struct device_node *np;
u32 bus_width;
- int len, ret;
+ int ret;
bool cd_cap_invert, cd_gpio_invert = false;
bool ro_cap_invert, ro_gpio_invert = false;
@@ -445,12 +445,12 @@ int mmc_of_parse(struct mmc_host *host)
*/
/* Parse Card Detection */
- if (of_find_property(np, "non-removable", &len)) {
+ if (of_property_read_bool(np, "non-removable")) {
host->caps |= MMC_CAP_NONREMOVABLE;
} else {
cd_cap_invert = of_property_read_bool(np, "cd-inverted");
- if (of_find_property(np, "broken-cd", &len))
+ if (of_property_read_bool(np, "broken-cd"))
host->caps |= MMC_CAP_NEEDS_POLL;
ret = mmc_gpiod_request_cd(host, "cd", 0, true,
@@ -491,41 +491,41 @@ int mmc_of_parse(struct mmc_host *host)
if (ro_cap_invert ^ ro_gpio_invert)
host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
- if (of_find_property(np, "cap-sd-highspeed", &len))
+ if (of_property_read_bool(np, "cap-sd-highspeed"))
host->caps |= MMC_CAP_SD_HIGHSPEED;
- if (of_find_property(np, "cap-mmc-highspeed", &len))
+ if (of_property_read_bool(np, "cap-mmc-highspeed"))
host->caps |= MMC_CAP_MMC_HIGHSPEED;
- if (of_find_property(np, "sd-uhs-sdr12", &len))
+ if (of_property_read_bool(np, "sd-uhs-sdr12"))
host->caps |= MMC_CAP_UHS_SDR12;
- if (of_find_property(np, "sd-uhs-sdr25", &len))
+ if (of_property_read_bool(np, "sd-uhs-sdr25"))
host->caps |= MMC_CAP_UHS_SDR25;
- if (of_find_property(np, "sd-uhs-sdr50", &len))
+ if (of_property_read_bool(np, "sd-uhs-sdr50"))
host->caps |= MMC_CAP_UHS_SDR50;
- if (of_find_property(np, "sd-uhs-sdr104", &len))
+ if (of_property_read_bool(np, "sd-uhs-sdr104"))
host->caps |= MMC_CAP_UHS_SDR104;
- if (of_find_property(np, "sd-uhs-ddr50", &len))
+ if (of_property_read_bool(np, "sd-uhs-ddr50"))
host->caps |= MMC_CAP_UHS_DDR50;
- if (of_find_property(np, "cap-power-off-card", &len))
+ if (of_property_read_bool(np, "cap-power-off-card"))
host->caps |= MMC_CAP_POWER_OFF_CARD;
- if (of_find_property(np, "cap-sdio-irq", &len))
+ if (of_property_read_bool(np, "cap-sdio-irq"))
host->caps |= MMC_CAP_SDIO_IRQ;
- if (of_find_property(np, "full-pwr-cycle", &len))
+ if (of_property_read_bool(np, "full-pwr-cycle"))
host->caps2 |= MMC_CAP2_FULL_PWR_CYCLE;
- if (of_find_property(np, "keep-power-in-suspend", &len))
+ if (of_property_read_bool(np, "keep-power-in-suspend"))
host->pm_caps |= MMC_PM_KEEP_POWER;
- if (of_find_property(np, "enable-sdio-wakeup", &len))
+ if (of_property_read_bool(np, "enable-sdio-wakeup"))
host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
- if (of_find_property(np, "mmc-ddr-1_8v", &len))
+ if (of_property_read_bool(np, "mmc-ddr-1_8v"))
host->caps |= MMC_CAP_1_8V_DDR;
- if (of_find_property(np, "mmc-ddr-1_2v", &len))
+ if (of_property_read_bool(np, "mmc-ddr-1_2v"))
host->caps |= MMC_CAP_1_2V_DDR;
- if (of_find_property(np, "mmc-hs200-1_8v", &len))
+ if (of_property_read_bool(np, "mmc-hs200-1_8v"))
host->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
- if (of_find_property(np, "mmc-hs200-1_2v", &len))
+ if (of_property_read_bool(np, "mmc-hs200-1_2v"))
host->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
- if (of_find_property(np, "mmc-hs400-1_8v", &len))
+ if (of_property_read_bool(np, "mmc-hs400-1_8v"))
host->caps2 |= MMC_CAP2_HS400_1_8V | MMC_CAP2_HS200_1_8V_SDR;
- if (of_find_property(np, "mmc-hs400-1_2v", &len))
+ if (of_property_read_bool(np, "mmc-hs400-1_2v"))
host->caps2 |= MMC_CAP2_HS400_1_2V | MMC_CAP2_HS200_1_2V_SDR;
host->dsr_req = !of_property_read_u32(np, "dsr", &host->dsr);
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Re: [RFC] sdhci: fix DMA leaks [was: [SHDCI] Heavy (thousands) DMA leaks]
On Wed 2015-08-05 17:11:48, Jiri Slaby wrote: > On 08/05/2015, 01:52 PM, Jiri Slaby wrote: > >> Yes, I see: > >> sdhci-pci :02:00.0: swiotlb buffer is full (sz: 65536 bytes) > >> after some time. The driver falls back to non-DMA transfers after that. > >> It also generates a warning about that: > >> WARNING: CPU: 0 PID: 0 at drivers/mmc/host/sdhci.c:857 > >> sdhci_prepare_data+0x8ec/0x900 [sdhci]() > > > > I am attaching a debug patch and a debug log. You can see where > > 0xfffb and 0xfffe is leaked. It is when 'invalid > > cookie' error happens. > > And you could see the cookie handling is totally bogus. > > With this rewrite, I no longer see the problems. Could you confirm it > still does the good job with respect to performance -- the numbers you > mentioned in your commit. > > Ulf, what do you think about the attached patch? (Do not look at the > commented info prints.) Umm. Normally we inline patches for easier comments. Attaching it with type of _mailbox_ is not really good. Pavel [-- Attachment #2: fix.patch --] [-- Type: application/mbox, Encoding: base64, Size: 8.2K --] -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC] sdhci: fix DMA leaks [was: [SHDCI] Heavy (thousands) DMA leaks]
On 08/05/2015, 01:52 PM, Jiri Slaby wrote: >> Yes, I see: >> sdhci-pci :02:00.0: swiotlb buffer is full (sz: 65536 bytes) >> after some time. The driver falls back to non-DMA transfers after that. >> It also generates a warning about that: >> WARNING: CPU: 0 PID: 0 at drivers/mmc/host/sdhci.c:857 >> sdhci_prepare_data+0x8ec/0x900 [sdhci]() > > I am attaching a debug patch and a debug log. You can see where > 0xfffb and 0xfffe is leaked. It is when 'invalid > cookie' error happens. And you could see the cookie handling is totally bogus. With this rewrite, I no longer see the problems. Could you confirm it still does the good job with respect to performance -- the numbers you mentioned in your commit. Ulf, what do you think about the attached patch? (Do not look at the commented info prints.) thanks, -- js suse labs fix.patch Description: application/mbox
Re: [PATCH 0/7] ARM: dts: MMC fixes for DRA7 based boards
Hi, On Wednesday 05 August 2015 04:24 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [150730 01:16]: >> Miscellaneous fixes in dts files for MMC device tree nodes. >> >> Did basic read/write test in J6, J6 Eco and Beagle-x15 >> >> Balaji T K (1): >> ARM: dts: dra7-evm: add evm_3v3_sd regulator >> >> Kishon Vijay Abraham I (5): >> ARM: dts: dra72-evm: add evm_3v3_sd regulator >> ARM: dts: dra72-evm: Set max clock frequency of MMC1 and MMC2 >> ARM: dts: am57xx-beagle-x15: mmc1: remove redundant pbias-supply >> property >> ARM: dts: dra7-evm: Fix spurious card insert/removal interrupt >> ARM: dts: dra72-evm: Fix spurious card insert/removal interrupt >> >> Nishanth Menon (1): >> ARM: dts: dra7-evm: Add MMCSD card removal GPIO >> >> arch/arm/boot/dts/am57xx-beagle-x15.dts |1 - >> arch/arm/boot/dts/dra7-evm.dts | 18 +- >> arch/arm/boot/dts/dra72-evm.dts | 16 ++-- >> 3 files changed, 31 insertions(+), 4 deletions(-) > > Thanks applying all these into omap-for-v4.3/dt. Thanks. Please take [1] one too. [1] -> https://lkml.org/lkml/2015/8/5/443 Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/11] omap_hsmmc: voltage switching and tuning
Hi, On Wednesday 05 August 2015 04:13 PM, Tony Lindgren wrote: > * Kishon Vijay Abraham I [150730 00:49]: >> Patch series implements voltage switching and tuning for omap_hsmmc >> driver. >> >> Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM, >> Beaglebone black, OMAP5 uEVM and OMAP4 PANDA. > > Your tests are missing omap3? I don't have one at my disposal :-( I'll try to find one and add omap3 tests. > > I suggest you add some omap3 tests in general as otherwise you are > only testing a subset of the driver features and completely missing > things like rutnime PM and save and restore for the deeper idle > states. yeah, I'll do those tests and re-post the series. Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [SHDCI] Heavy (thousands) DMA leaks
On 08/03/2015, 11:39 AM, Jiri Slaby wrote: > Hi, > > On 08/03/2015, 11:30 AM, Chen Bough wrote: >> I carefully review my patch, all the DMA memory mapped in sdhci_pre_req() is >> unmapped in sdhci_post_req. > > I suspect 'host_cookie' or 'next' handling is bad somewhere. But I don't > know... > >> Can you provide the method of your testing DMA leaks? > > boot kernel with CONFIG_DMA_API_DEBUG > insert the card > mount it > rsync from the card ~200 MB > umount it > unload the sdhci driver > the leak warning is reported > > I am not sure whether suspend-resume is needed after the first step. No, it's not. This is sufficient: boot kernel with CONFIG_DMA_API_DEBUG insert the card remove the card unload the sdhci driver the leak warning is reported >> You said over 4000 leaked mappings during one card transfer, if true, >> We can't map any dma memory after some sd transfer, do you meet this? > > Yes, I see: > sdhci-pci :02:00.0: swiotlb buffer is full (sz: 65536 bytes) > after some time. The driver falls back to non-DMA transfers after that. > It also generates a warning about that: > WARNING: CPU: 0 PID: 0 at drivers/mmc/host/sdhci.c:857 > sdhci_prepare_data+0x8ec/0x900 [sdhci]() I am attaching a debug patch and a debug log. You can see where 0xfffb and 0xfffe is leaked. It is when 'invalid cookie' error happens. regards, -- js suse labs [ 474.663337] sdhci_pre_dma_transfer: mapped 88030bfe7bc0 0xf3f0 (wanted=1, got=1), next= (null), hcook=0, ncook=1 [ 474.663844] sdhci_finish_data: unmapping 88030bfe7bc0 phys=0xf3f0 size=1 [ 474.664109] sdhci_pre_dma_transfer: mapped 88030bfe7bc0 0xe310 (wanted=1, got=1), next= (null), hcook=0, ncook=1 [ 474.665025] sdhci_finish_data: unmapping 88030bfe7bc0 phys=0xe310 size=1 [ 474.665136] sdhci_pre_dma_transfer: mapped 88030bfe7bd0 0xd310 (wanted=1, got=1), next= (null), hcook=0, ncook=1 [ 474.666746] sdhci_finish_data: unmapping 88030bfe7bd0 phys=0xd310 size=1 [ 474.666912] sdhci_pre_dma_transfer: mapped 88030bfe7be0 0xc310 (wanted=1, got=1), next= (null), hcook=0, ncook=1 [ 474.669979] sdhci_finish_data: unmapping 88030bfe7be0 phys=0xc310 size=1 [ 474.670405] mmc0: new high speed SDHC card at address e624 [ 474.671107] mmcblk0: mmc0:e624 SU16G 14.8 GiB [ 474.672309] sdhci_pre_dma_transfer: mapped 880306c52e10 0xb000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=1 [ 474.682178] sdhci_post_req: unmapping 880306c52e10 phys=0xb000 size=1 [ 474.682234] mmcblk0: p1 [ 474.684064] sdhci_pre_dma_transfer: mapped 880306c52e10 0xf000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=2 [ 474.684825] sdhci_post_req: unmapping 880306c52e10 phys=0xf000 size=1 [ 474.684954] sdhci_pre_dma_transfer: mapped 880306c52e10 0xe000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=3 [ 474.685494] sdhci_post_req: unmapping 880306c52e10 phys=0xe000 size=1 [ 474.685660] sdhci_pre_dma_transfer: mapped 880306c52e10 0xd000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=4 [ 474.686316] sdhci_post_req: unmapping 880306c52e10 phys=0xd000 size=1 [ 474.686449] sdhci_pre_dma_transfer: mapped 880306c52e10 0xc000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=5 [ 474.686878] sdhci_post_req: unmapping 880306c52e10 phys=0xc000 size=1 [ 474.687046] sdhci_pre_dma_transfer: mapped 880306c52e10 0xa000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=6 [ 474.687590] sdhci_post_req: unmapping 880306c52e10 phys=0xa000 size=1 [ 474.687720] sdhci_pre_dma_transfer: mapped 880306c52e10 0x9000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=7 [ 474.688203] sdhci_post_req: unmapping 880306c52e10 phys=0x9000 size=1 [ 474.688342] sdhci_pre_dma_transfer: mapped 880306c52e10 0x8000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=8 [ 474.688865] sdhci_post_req: unmapping 880306c52e10 phys=0x8000 size=1 [ 474.688988] sdhci_pre_dma_transfer: mapped 880306c52e10 0x7000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=9 [ 474.689618] sdhci_post_req: unmapping 880306c52e10 phys=0x7000 size=1 [ 474.689748] sdhci_pre_dma_transfer: mapped 880306c52e10 0x6000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=10 [ 474.690393] sdhci_post_req: unmapping 880306c52e10 phys=0x6000 size=1 [ 474.690549] sdhci_pre_dma_transfer: mapped 880306c52e10 0x5000 (wanted=1, got=1), next=88030bf21aa4, hcook=0, ncook=11 [ 474.691165] sdhci_post_req: unmapping 880306c52e10
Re: [PATCH 0/7] ARM: dts: MMC fixes for DRA7 based boards
* Kishon Vijay Abraham I [150730 01:16]: > Miscellaneous fixes in dts files for MMC device tree nodes. > > Did basic read/write test in J6, J6 Eco and Beagle-x15 > > Balaji T K (1): > ARM: dts: dra7-evm: add evm_3v3_sd regulator > > Kishon Vijay Abraham I (5): > ARM: dts: dra72-evm: add evm_3v3_sd regulator > ARM: dts: dra72-evm: Set max clock frequency of MMC1 and MMC2 > ARM: dts: am57xx-beagle-x15: mmc1: remove redundant pbias-supply > property > ARM: dts: dra7-evm: Fix spurious card insert/removal interrupt > ARM: dts: dra72-evm: Fix spurious card insert/removal interrupt > > Nishanth Menon (1): > ARM: dts: dra7-evm: Add MMCSD card removal GPIO > > arch/arm/boot/dts/am57xx-beagle-x15.dts |1 - > arch/arm/boot/dts/dra7-evm.dts | 18 +- > arch/arm/boot/dts/dra72-evm.dts | 16 ++-- > 3 files changed, 31 insertions(+), 4 deletions(-) Thanks applying all these into omap-for-v4.3/dt. Tony -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 2/6] mmc: sdhci-esdhc-imx: add tuning-step seting support
tuning-step is the delay cell steps in tuning procedure. The default value
of tuning-step is 1. Some boards or cards need another value to pass the
tuning procedure. For example, imx7d-sdb board need the tuning-step value
as 2, otherwise it can't pass the tuning procedure.
So this patch add the tuning-step setting in driver, so that user can set
the tuning-step value in dts.
Signed-off-by: Haibo Chen
---
drivers/mmc/host/sdhci-esdhc-imx.c | 9 +
include/linux/platform_data/mmc-esdhc-imx.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 48f009c..803d24f 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -75,6 +75,7 @@
#define ESDHC_STD_TUNING_EN(1 << 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP 0x1
+#define ESDHC_TUNING_STEP_SHIFT16
/* pinctrl state */
#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
@@ -474,6 +475,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
} else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
+ u32 tuning_ctrl;
if (val & SDHCI_CTRL_TUNED_CLK) {
v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
} else {
@@ -484,6 +486,11 @@ static void esdhc_writew_le(struct sdhci_host *host, u16
val, int reg)
if (val & SDHCI_CTRL_EXEC_TUNING) {
v |= ESDHC_MIX_CTRL_EXE_TUNE;
m |= ESDHC_MIX_CTRL_FBCLK_SEL;
+ tuning_ctrl = readl(host->ioaddr +
ESDHC_TUNING_CTRL);
+ tuning_ctrl |= ESDHC_STD_TUNING_EN |
ESDHC_TUNING_START_TAP;
+ if (imx_data->boarddata.tuning_step)
+ tuning_ctrl |=
imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
+ writel(tuning_ctrl, host->ioaddr +
ESDHC_TUNING_CTRL);
} else {
v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
}
@@ -964,6 +971,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
if (gpio_is_valid(boarddata->wp_gpio))
boarddata->wp_type = ESDHC_WP_GPIO;
+ of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
+
if (of_find_property(np, "no-1-8-v", NULL))
boarddata->support_vsel = false;
else
diff --git a/include/linux/platform_data/mmc-esdhc-imx.h
b/include/linux/platform_data/mmc-esdhc-imx.h
index e1571ef..95ccab3 100644
--- a/include/linux/platform_data/mmc-esdhc-imx.h
+++ b/include/linux/platform_data/mmc-esdhc-imx.h
@@ -45,5 +45,6 @@ struct esdhc_platform_data {
int max_bus_width;
bool support_vsel;
unsigned int delay_line;
+ unsigned int tuning_step; /* The delay cell steps in tuning
procedure */
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
--
1.9.1
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[PATCH v4 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
The imx7d usdhc is derived from imx6sx, the difference is that
imx7d support HS400.
So introduce a new compatible string for imx7d and add HS400
support for imx7d usdhc.
Signed-off-by: Haibo Chen
---
drivers/mmc/host/sdhci-esdhc-imx.c | 81 ++
1 file changed, 81 insertions(+)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index c6b9f64..48f009c 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -44,6 +44,7 @@
#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
+#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
/* Bits 3 and 6 are not SDHCI standard definitions */
#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
/* Tuning bits */
@@ -60,6 +61,16 @@
#define ESDHC_TUNE_CTRL_MIN 0
#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL 0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
+#define ESDHC_STROBE_DLL_CTRL_RESET(1 << 1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
+
+#define ESDHC_STROBE_DLL_STATUS0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
+
#define ESDHC_TUNING_CTRL 0xcc
#define ESDHC_STD_TUNING_EN(1 << 24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
@@ -120,6 +131,11 @@
#define ESDHC_FLAG_ERR004536 BIT(7)
/* The IP supports HS200 mode */
#define ESDHC_FLAG_HS200 BIT(8)
+/* The IP supports HS400 mode */
+#define ESDHC_FLAG_HS400 BIT(9)
+
+/* A higher clock ferquency than this rate requires strobell dll control */
+#define ESDHC_STROBE_DLL_CLK_FREQ 1
struct esdhc_soc_data {
u32 flags;
@@ -156,6 +172,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = {
| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
};
+static struct esdhc_soc_data usdhc_imx7d_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+ | ESDHC_FLAG_HS400,
+};
+
struct pltfm_imx_data {
u32 scratchpad;
struct pinctrl *pinctrl;
@@ -199,6 +221,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
+ { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
@@ -274,6 +297,9 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
| SDHCI_USE_SDR50_TUNING;
+
+ if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
+ val |= SDHCI_SUPPORT_HS400;
}
}
@@ -774,6 +800,7 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
break;
case MMC_TIMING_UHS_SDR104:
case MMC_TIMING_MMC_HS200:
+ case MMC_TIMING_MMC_HS400:
pinctrl = imx_data->pins_200mhz;
break;
default:
@@ -784,6 +811,44 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
return pinctrl_select_state(imx_data->pinctrl, pinctrl);
}
+/*
+ * For HS400 eMMC, there is a data_strobe line, this signal is generated
+ * by the device and used for data output and CRC status response output
+ * in HS400 mode. The frequency of this signal follows the frequency of
+ * CLK generated by host. Host receive the data which is aligned to the
+ * edge of data_strobe line. Due to the time delay between CLK line and
+ * data_strobe line, if the delay time is larger than one clock cycle,
+ * then CLK and data_strobe line will misaligned, read error shows up.
+ * So when the CLK is higher than 100MHz, each clock cycle is short enough,
+ * host should config the delay target.
+ */
+static void esdhc_set_strobe_dll(struct sdhci_host *host)
+{
+ u32 v;
+
+ if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+ /* force a reset on strobe dll */
+ writel(ESDHC_STROBE_DLL_CTRL_RESET,
+ host->ioaddr + ESDHC_STROBE_DLL_CTRL);
+ /*
+* enable strobe dll ctrl and adjust the delay target
+* for the uSDHC loopback read clock
+*/
+ v = ESDHC_STROBE_DLL_CTRL_ENABLE |
+ (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+ writel(v, host->ioaddr + ESDHC_STROB
[PATCH v4 0/6] mmc: imx: a few fixes and new feature
Changes for v4: -Call esdhc_set_strobe_dll() only when device clock is over 100MHz in HS400 mode. -Add detail description of tuning-step. -Change to default watermark level and burst length for all imx SoC, not only imx7d. Haibo Chen (6): mmc: sdhci-esdhc-imx: add imx7d support and support HS400 mmc: sdhci-esdhc-imx: add tuning-step seting support mmc: sdhci-esdhc-imx: add compatible string in bingding doc ARM: dts: imx7d-sdb: add eMMC5.0 support mmc: sdhci-esdhc-imx: change default watermark level and burst length mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1 .../devicetree/bindings/mmc/fsl-imx-esdhc.txt | 6 ++ arch/arm/boot/dts/imx7d-sdb.dts| 13 +++ drivers/mmc/host/sdhci-esdhc-imx.c | 109 - include/linux/platform_data/mmc-esdhc-imx.h| 1 + 4 files changed, 128 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/11] omap_hsmmc: voltage switching and tuning
* Kishon Vijay Abraham I [150730 00:49]: > Patch series implements voltage switching and tuning for omap_hsmmc > driver. > > Did basic read/write test in J6, J6 Eco, Beagle-x15, AM437x EVM, > Beaglebone black, OMAP5 uEVM and OMAP4 PANDA. Your tests are missing omap3? I suggest you add some omap3 tests in general as otherwise you are only testing a subset of the driver features and completely missing things like rutnime PM and save and restore for the deeper idle states. Regards, Ton -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 4/6] ARM: dts: imx7d-sdb: add eMMC5.0 support
imx7d-sdb board has a eMMC5.0 on usdhc3. This eMMC support HS400.
This patch add usdhc3 support for HS400
Signed-off-by: Haibo Chen
---
arch/arm/boot/dts/imx7d-sdb.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index fdd1d7c..8059458 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -241,6 +241,19 @@
status = "okay";
};
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <4>;
+ bus-width = <8>;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
--
1.9.1
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[PATCH v4 3/6] mmc: sdhci-esdhc-imx: add compatible string in bingding doc
Add a required property "fsl,imx7d-usdhc" in binding doc. Add an optional property "fsl,tuning-step" in binding doc. Signed-off-by: Haibo Chen --- Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 211e778..dca56d6 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -15,6 +15,7 @@ Required properties: "fsl,imx6q-usdhc" "fsl,imx6sl-usdhc" "fsl,imx6sx-usdhc" + "fsl,imx7d-usdhc" Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection @@ -27,6 +28,11 @@ Optional properties: transparent level shifters on the outputs of the controller. Two cells are required, first cell specifies minimum slot voltage (mV), second cell specifies maximum slot voltage (mV). Several ranges could be specified. +- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure. + The uSDHC use one delay cell as default increasing step to do tuning process. + This property allows user to change the tuning step to more than one delay + cells which is useful for some special boards or cards when the default + tuning step can't find the proper delay window within limited tuning retries. Examples: -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 5/6] mmc: sdhci-esdhc-imx: change default watermark level and burst length
By default, for all imx SoC types, the watermark level is 16, and the
burst length is 8. But if the SDIO/SD/MMC I/O speed is fast enough,
this default watermark level and burst length will be the performance
bottleneck.
For example, i.MX7D support eMMC HS400 mode, this mode can run in 8 bit,
200MHZ DDR mode. So the I/O speed improve a lot compare to SD3.0.
The default burst length is 8, if we don't change this value, in
HS400 mode, when we do eMMC read operation, we can find that the
clock signal will stop for a period of time. This means the speed
of data moving on AHB bus is slower than I/O speed. So we should
improve the speed of data moving on AHB bus.
This patch set the default burst length as 16, and set the default
watermark level as 64. The test result is the clock signal has
no stop during the eMMC HS400 operation.
Signed-off-by: Haibo Chen
---
drivers/mmc/host/sdhci-esdhc-imx.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 803d24f..97aa944 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -1160,7 +1160,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device
*pdev)
* to something insane. Change it back here.
*/
if (esdhc_is_usdhc(imx_data)) {
- writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
+ writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL);
+
host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
host->mmc->caps |= MMC_CAP_1_8V_DDR;
--
1.9.1
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[PATCH v4 6/6] mmc: sdhci-esdhc-imx: set back the burst_length_enable bit to 1
Currently we find that if a usdhc is choosed to boot system, then ROM code will set the burst length enable bit of this usdhc as 0. This will make performance drop a lot if this usdhc's burst length is configed. So this patch set back the burst_length_enable bit as 1, which is the default value, and means burst length is enabled for INCR. Signed-off-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 16 1 file changed, 16 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 97aa944..3334762 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -32,6 +32,7 @@ #include "sdhci-esdhc.h" #defineESDHC_CTRL_D3CD 0x08 +#define ESDHC_BURST_LEN_EN_INCR(1 << 27) /* VENDOR SPEC register */ #define ESDHC_VENDOR_SPEC 0xc0 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) @@ -1165,6 +1166,21 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; host->mmc->caps |= MMC_CAP_1_8V_DDR; + /* +* ROM code will change the bit burst_length_enable setting +* to zero if this usdhc is choosed to boot system. Change +* it back here, otherwise it will impact the performance a +* lot. This bit is used to enable/disable the burst length +* for the external AHB2AXI bridge, it's usefully especially +* for INCR transfer because without burst length indicator, +* the AHB2AXI bridge does not know the burst length in +* advance. And without burst length indicator, AHB INCR +* transfer can only be converted to singles on the AXI side. +*/ + writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) + | ESDHC_BURST_LEN_EN_INCR, + host->ioaddr + SDHCI_HOST_CONTROL); + if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400
On Wed, Aug 05, 2015 at 03:39:29PM +0800, Chen Haibo-B51421 wrote:
>
>
> > -Original Message-
> > From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
> > Sent: Monday, August 03, 2015 8:10 PM
> > To: Chen Haibo-B51421
> > Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
> > ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; shawn...@kernel.org;
> > ker...@pengutronix.de; li...@arm.linux.org.uk; ulf.hans...@linaro.org;
> > johan.dery...@barco.com; Estevam Fabio-R49496; devicet...@vger.kernel.org;
> > linux-ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> > linux-mmc@vger.kernel.org
> > Subject: Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and
> > support HS400
> >
> > On Sun, Aug 02, 2015 at 04:59:04PM +0800, Chen Haibo-B51421 wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Dong Aisheng [mailto:aisheng.d...@freescale.com]
> > > > Sent: Friday, July 31, 2015 10:15 PM
> > > > To: Chen Haibo-B51421
> > > > Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com;
> > > > ijc+devicet...@hellion.org.uk; ga...@codeaurora.org;
> > > > ijc+shawn...@kernel.org;
> > > > ker...@pengutronix.de; li...@arm.linux.org.uk;
> > > > ulf.hans...@linaro.org; johan.dery...@barco.com; Estevam
> > > > Fabio-R49496; Dong Aisheng-B29396; devicet...@vger.kernel.org;
> > > > linux-ker...@vger.kernel.org; linux-arm- ker...@lists.infradead.org;
> > > > linux-mmc@vger.kernel.org
> > > > Subject: Re: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support
> > > > and support HS400
> > > >
> > > > On Wed, Jul 29, 2015 at 05:03:52PM +0800, Haibo Chen wrote:
> > > > > The imx7d usdhc is derived from imx6sx, the difference is that
> > > > > imx7d support HS400.
> > > > >
> > > > > So introduce a new compatible string for imx7d and add HS400
> > > > > support for imx7d usdhc.
> > > > >
> > > > > Signed-off-by: Haibo Chen
> > > > > ---
> > > > > drivers/mmc/host/sdhci-esdhc-imx.c | 66
> > > > > ++
> > > > > 1 file changed, 66 insertions(+)
> > > > >
> > > > > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c
> > > > > b/drivers/mmc/host/sdhci-esdhc-imx.c
> > > > > index c6b9f64..b441eed 100644
> > > > > --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> > > > > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> > > > > @@ -44,6 +44,7 @@
> > > > > #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
> > > > > #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
> > > > > #define ESDHC_MIX_CTRL_FBCLK_SEL(1 << 25)
> > > > > +#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
> > > > > /* Bits 3 and 6 are not SDHCI standard definitions */
> > > > > #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
> > > > > /* Tuning bits */
> > > > > @@ -60,6 +61,16 @@
> > > > > #define ESDHC_TUNE_CTRL_MIN 0
> > > > > #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
> > > > >
> > > > > +/* strobe dll register */
> > > > > +#define ESDHC_STROBE_DLL_CTRL0x70
> > > > > +#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
> > > > > +#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
> > > > > +#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
> > > > > +
> > > > > +#define ESDHC_STROBE_DLL_STATUS 0x74
> > > > > +#define ESDHC_STROBE_DLL_STS_REF_LOCK(1 << 1)
> > > > > +#define ESDHC_STROBE_DLL_STS_SLV_LOCK0x1
> > > > > +
> > > > > #define ESDHC_TUNING_CTRL0xcc
> > > > > #define ESDHC_STD_TUNING_EN (1 << 24)
> > > > > /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@
> > > > > -120,6 +131,8 @@
> > > > > #define ESDHC_FLAG_ERR004536 BIT(7)
> > > > > /* The IP supports HS200 mode */
> > > > > #define ESDHC_FLAG_HS200 BIT(8)
> > > > > +/* The IP supports HS400 mode */
> > > > > +#define ESDHC_FLAG_SUP_HS400 BIT(9)
> > > > >
> > > > > struct esdhc_soc_data {
> > > > > u32 flags;
> > > > > @@ -156,6 +169,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data
> > = {
> > > > > | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, };
> > > > >
> > > > > +static struct esdhc_soc_data usdhc_imx7d_data = {
> > > > > + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
> > > > > + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> > > > > + | ESDHC_FLAG_SUP_HS400,
> > > > > +};
> > > > > +
> > > > > struct pltfm_imx_data {
> > > > > u32 scratchpad;
> > > > > struct pinctrl *pinctrl;
> > > > > @@ -199,6 +218,7 @@ static const struct of_device_id
> > > > > imx_esdhc_dt_ids[]
> > > > = {
> > > > > { .compatible = "fsl,imx6sx-usdhc", .data =
> > &usdhc_imx6sx_data, },
> > > > > { .compatible = "fsl,imx6sl-usdhc", .data =
> > &usdhc_imx6sl_data, },
> > > > > { .compatible = "fsl,imx6q-usdhc", .data =
> > &usdhc_imx6q_data, },
> > > > > + { .compatible = "fsl,imx7d-usdhc", .data =
> > &usdhc_imx7d_data, },
> > > > > { /* sentinel */ }
> > > > > };
> > > > > MODULE_DEVICE_TABLE
