[LinuxBIOS] r553 - LinuxBIOSv3/arch/x86/geodelx
Author: hailfinger Date: 2008-01-12 02:09:47 +0100 (Sat, 12 Jan 2008) New Revision: 553 Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c Log: After configuring the PLL registers on Geode LX, we have to reset the processor. However, nothing in the log tells the user why the processor is being reset. Example log follows: LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting... Choosing fallback boot. [...] Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. [...] LAR: CHECK normal/initram/segment0 @ 0xfffc49b0 start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x10ca loadaddress 0x Entry point is 0xfffc5aca pll_reset: read msr 0x4c14 _MSR GLCP_SYS_RSTPLL (4c14) value is: 0398:181e Configuring PLL LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting... Choosing fallback boot. [...] Print an informative message before resetting the processor. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c === --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2008-01-10 21:13:19 UTC (rev 552) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2008-01-12 01:09:47 UTC (rev 553) @@ -187,6 +187,8 @@ /* Use SWFLAGS to remember: "we've already been here". */ msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); + printk(BIOS_INFO, "Resetting the processor after PLL " + "configuration for the changes to take effect\n"); /* "Reset the chip" value */ msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll); -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r553 - LinuxBIOSv3/arch/x86/geodelx
Author: hailfinger Date: 2008-01-12 02:09:47 +0100 (Sat, 12 Jan 2008) New Revision: 553 Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c Log: After configuring the PLL registers on Geode LX, we have to reset the processor. However, nothing in the log tells the user why the processor is being reset. Example log follows: LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting... Choosing fallback boot. [...] Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. [...] LAR: CHECK normal/initram/segment0 @ 0xfffc49b0 start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x10ca loadaddress 0x Entry point is 0xfffc5aca pll_reset: read msr 0x4c14 _MSR GLCP_SYS_RSTPLL (4c14) value is: 0398:181e Configuring PLL LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting... Choosing fallback boot. [...] Print an informative message before resetting the processor. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/geodelx/geodelx.c === --- LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2008-01-10 21:13:19 UTC (rev 552) +++ LinuxBIOSv3/arch/x86/geodelx/geodelx.c 2008-01-12 01:09:47 UTC (rev 553) @@ -187,6 +187,8 @@ /* Use SWFLAGS to remember: "we've already been here". */ msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); + printk(BIOS_INFO, "Resetting the processor after PLL " + "configuration for the changes to take effect\n"); /* "Reset the chip" value */ msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll); -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r95 - buildrom-devel/config/platforms
Author: jcrouse Date: 2008-01-11 23:53:36 +0100 (Fri, 11 Jan 2008) New Revision: 95 Modified: buildrom-devel/config/platforms/alix1c.conf buildrom-devel/config/platforms/msm800sev.conf Log: [BUILDROM] Bump the mem800sev and alix1c revisions Bump the linuxbios revision of the mem800sev and alix1c to take advantage of the payload patch added to LBv2. Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]> Acked-by: Ward Vandewege <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/alix1c.conf === --- buildrom-devel/config/platforms/alix1c.conf 2008-01-11 20:46:46 UTC (rev 94) +++ buildrom-devel/config/platforms/alix1c.conf 2008-01-11 22:53:36 UTC (rev 95) @@ -29,7 +29,7 @@ LINUXBIOS_BOARD=alix1c LBV2_CONFIG=Config.lb LBV2_TDIR=alix1c -LBV2_TAG=2807 +LBV2_TAG=3047 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/msm800sev.conf === --- buildrom-devel/config/platforms/msm800sev.conf 2008-01-11 20:46:46 UTC (rev 94) +++ buildrom-devel/config/platforms/msm800sev.conf 2008-01-11 22:53:36 UTC (rev 95) @@ -30,7 +30,7 @@ LINUXBIOS_BOARD=msm800sev LBV2_CONFIG=Config.lb LBV2_TDIR=msm800sev -LBV2_TAG=2810 +LBV2_TAG=3047 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r95 - buildrom-devel/config/platforms
Author: jcrouse Date: 2008-01-11 23:53:36 +0100 (Fri, 11 Jan 2008) New Revision: 95 Modified: buildrom-devel/config/platforms/alix1c.conf buildrom-devel/config/platforms/msm800sev.conf Log: [BUILDROM] Bump the mem800sev and alix1c revisions Bump the linuxbios revision of the mem800sev and alix1c to take advantage of the payload patch added to LBv2. Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]> Acked-by: Ward Vandewege <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/alix1c.conf === --- buildrom-devel/config/platforms/alix1c.conf 2008-01-11 20:46:46 UTC (rev 94) +++ buildrom-devel/config/platforms/alix1c.conf 2008-01-11 22:53:36 UTC (rev 95) @@ -29,7 +29,7 @@ LINUXBIOS_BOARD=alix1c LBV2_CONFIG=Config.lb LBV2_TDIR=alix1c -LBV2_TAG=2807 +LBV2_TAG=3047 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/msm800sev.conf === --- buildrom-devel/config/platforms/msm800sev.conf 2008-01-11 20:46:46 UTC (rev 94) +++ buildrom-devel/config/platforms/msm800sev.conf 2008-01-11 22:53:36 UTC (rev 95) @@ -30,7 +30,7 @@ LINUXBIOS_BOARD=msm800sev LBV2_CONFIG=Config.lb LBV2_TDIR=msm800sev -LBV2_TAG=2810 +LBV2_TAG=3047 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3047 - in trunk/LinuxBIOSv2/targets: digitallogic/msm800sev pcengines/alix1c
Author: rminnich Date: 2008-01-11 23:37:27 +0100 (Fri, 11 Jan 2008) New Revision: 3047 Modified: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb Log: Fix these to use a more standard relative path for payload. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb === --- trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb 2008-01-11 18:23:47 UTC (rev 3046) +++ trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb 2008-01-11 22:37:27 UTC (rev 3047) @@ -22,7 +22,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option LINUXBIOS_EXTRA_VERSION=".0Fallback" - payload /tmp/filo.elf + payload ../payload.elf end buildrom ./linuxbios.rom ROM_SIZE "fallback" Modified: trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb === --- trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb2008-01-11 18:23:47 UTC (rev 3046) +++ trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb2008-01-11 22:37:27 UTC (rev 3047) @@ -19,7 +19,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE = 1 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" - payload /tmp/filo.elf + payload ../payload.elf end buildrom ./linuxbios.rom ROM_SIZE "fallback" -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3047 - in trunk/LinuxBIOSv2/targets: digitallogic/msm800sev pcengines/alix1c
Author: rminnich Date: 2008-01-11 23:37:27 +0100 (Fri, 11 Jan 2008) New Revision: 3047 Modified: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb Log: Fix these to use a more standard relative path for payload. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb === --- trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb 2008-01-11 18:23:47 UTC (rev 3046) +++ trunk/LinuxBIOSv2/targets/digitallogic/msm800sev/Config.lb 2008-01-11 22:37:27 UTC (rev 3047) @@ -22,7 +22,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE=1 option LINUXBIOS_EXTRA_VERSION=".0Fallback" - payload /tmp/filo.elf + payload ../payload.elf end buildrom ./linuxbios.rom ROM_SIZE "fallback" Modified: trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb === --- trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb2008-01-11 18:23:47 UTC (rev 3046) +++ trunk/LinuxBIOSv2/targets/pcengines/alix1c/Config.lb2008-01-11 22:37:27 UTC (rev 3047) @@ -19,7 +19,7 @@ romimage "fallback" option USE_FALLBACK_IMAGE = 1 option LINUXBIOS_EXTRA_VERSION = ".0Fallback" - payload /tmp/filo.elf + payload ../payload.elf end buildrom ./linuxbios.rom ROM_SIZE "fallback" -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r94 - buildrom-devel/packages/linuxbios
Author: ward Date: 2008-01-11 21:46:46 +0100 (Fri, 11 Jan 2008) New Revision: 94 Modified: buildrom-devel/packages/linuxbios/norwich-linuxbios.mk Log: This spurious echo sneaked in in r90 but breaks the build for the norwich board. This is a trivial patch. Signed-off-by: Ward Vandewege <[EMAIL PROTECTED]> Acked-by: Ward Vandewege <[EMAIL PROTECTED]> Modified: buildrom-devel/packages/linuxbios/norwich-linuxbios.mk === --- buildrom-devel/packages/linuxbios/norwich-linuxbios.mk 2008-01-11 20:02:53 UTC (rev 93) +++ buildrom-devel/packages/linuxbios/norwich-linuxbios.mk 2008-01-11 20:46:46 UTC (rev 94) @@ -1,6 +1,5 @@ # This is the Generic LinuxBIOS target -echo $(LBV2_TAG) ifeq ($(CONFIG_PLATFORM),y) ifeq ($(LBV2_TAG),) $(error You need to specify a version to pull in your platform config) -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r94 - buildrom-devel/packages/linuxbios
Author: ward Date: 2008-01-11 21:46:46 +0100 (Fri, 11 Jan 2008) New Revision: 94 Modified: buildrom-devel/packages/linuxbios/norwich-linuxbios.mk Log: This spurious echo sneaked in in r90 but breaks the build for the norwich board. This is a trivial patch. Signed-off-by: Ward Vandewege <[EMAIL PROTECTED]> Acked-by: Ward Vandewege <[EMAIL PROTECTED]> Modified: buildrom-devel/packages/linuxbios/norwich-linuxbios.mk === --- buildrom-devel/packages/linuxbios/norwich-linuxbios.mk 2008-01-11 20:02:53 UTC (rev 93) +++ buildrom-devel/packages/linuxbios/norwich-linuxbios.mk 2008-01-11 20:46:46 UTC (rev 94) @@ -1,6 +1,5 @@ # This is the Generic LinuxBIOS target -echo $(LBV2_TAG) ifeq ($(CONFIG_PLATFORM),y) ifeq ($(LBV2_TAG),) $(error You need to specify a version to pull in your platform config) -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r93 - buildrom-devel/packages/busybox/conf
Author: myles Date: 2008-01-11 21:02:53 +0100 (Fri, 11 Jan 2008) New Revision: 93 Added: buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 Log: Sorry I missed this file in an earlier commit. Signed-off-by: Myles Watson <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Added: buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 === --- buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 (rev 0) +++ buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 2008-01-11 20:02:53 UTC (rev 93) @@ -0,0 +1,598 @@ +# +# Automatically generated make config: don't edit +# +HAVE_DOT_CONFIG=y + +# +# Busybox Settings +# + +# +# General Configuration +# +CONFIG_FEATURE_BUFFERS_USE_MALLOC=y +# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set +# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set +# CONFIG_FEATURE_VERBOSE_USAGE is not set +# CONFIG_FEATURE_INSTALLER is not set +# CONFIG_LOCALE_SUPPORT is not set +# CONFIG_FEATURE_DEVFS is not set +CONFIG_FEATURE_DEVPTS=y +# CONFIG_FEATURE_CLEAN_UP is not set +CONFIG_FEATURE_SUID=y +# CONFIG_FEATURE_SUID_CONFIG is not set +# CONFIG_FEATURE_SUID_CONFIG_QUIET is not set +# CONFIG_SELINUX is not set + +# +# Build Options +# +# CONFIG_STATIC is not set +# CONFIG_DISABLE_SHARED is not set +# CONFIG_BUILD_LIBBUSYBOX is not set +# CONFIG_FEATURE_FULL_LIBBUSYBOX is not set +# CONFIG_FEATURE_SHARED_BUSYBOX is not set +CONFIG_LFS=y +# USING_CROSS_COMPILER is not set +CROSS_COMPILER_PREFIX="" +EXTRA_CFLAGS_OPTIONS="" +# CONFIG_BUILD_AT_ONCE is not set + +# +# Debugging Options +# +# CONFIG_DEBUG is not set +# CONFIG_NO_DEBUG_LIB is not set +# CONFIG_DMALLOC is not set +# CONFIG_EFENCE is not set +CONFIG_DEBUG_YANK_SUSv2=y + +# +# Installation Options +# +# CONFIG_INSTALL_NO_USR is not set +CONFIG_INSTALL_APPLET_SYMLINKS=y +# CONFIG_INSTALL_APPLET_HARDLINKS is not set +# CONFIG_INSTALL_APPLET_DONT is not set +PREFIX="./_install" + +# +# Busybox Library Tuning +# +CONFIG_MD5_SIZE_VS_SPEED=2 + +# +# Applets +# + +# +# Archival Utilities +# +# CONFIG_AR is not set +# CONFIG_FEATURE_AR_LONG_FILENAMES is not set +# CONFIG_BUNZIP2 is not set +# CONFIG_CPIO is not set +# CONFIG_DPKG is not set +# CONFIG_DPKG_DEB is not set +# CONFIG_FEATURE_DPKG_DEB_EXTRACT_ONLY is not set +# CONFIG_GUNZIP is not set +# CONFIG_FEATURE_GUNZIP_UNCOMPRESS is not set +# CONFIG_GZIP is not set +# CONFIG_RPM2CPIO is not set +# CONFIG_RPM is not set +# CONFIG_TAR is not set +# CONFIG_FEATURE_TAR_CREATE is not set +# CONFIG_FEATURE_TAR_BZIP2 is not set +# CONFIG_FEATURE_TAR_LZMA is not set +# CONFIG_FEATURE_TAR_FROM is not set +# CONFIG_FEATURE_TAR_GZIP is not set +# CONFIG_FEATURE_TAR_COMPRESS is not set +# CONFIG_FEATURE_TAR_OLDGNU_COMPATABILITY is not set +# CONFIG_FEATURE_TAR_GNU_EXTENSIONS is not set +# CONFIG_FEATURE_TAR_LONG_OPTIONS is not set +# CONFIG_UNCOMPRESS is not set +# CONFIG_UNLZMA is not set +# CONFIG_FEATURE_LZMA_FAST is not set +# CONFIG_UNZIP is not set +# CONFIG_FEATURE_UNARCHIVE_TAPE is not set +# CONFIG_FEATURE_DEB_TAR_GZ is not set +# CONFIG_FEATURE_DEB_TAR_BZ2 is not set +# CONFIG_FEATURE_DEB_TAR_LZMA is not set + +# +# Coreutils +# +CONFIG_BASENAME=y +# CONFIG_CAL is not set +CONFIG_CAT=y +# CONFIG_CHGRP is not set +# CONFIG_CHMOD is not set +# CONFIG_CHOWN is not set +# CONFIG_CHROOT is not set +# CONFIG_CMP is not set +# CONFIG_COMM is not set +CONFIG_CP=y +# CONFIG_CUT is not set +# CONFIG_DATE is not set +# CONFIG_FEATURE_DATE_ISOFMT is not set +CONFIG_DD=y +# CONFIG_DF is not set +# CONFIG_DIRNAME is not set +# CONFIG_DOS2UNIX is not set +# CONFIG_UNIX2DOS is not set +# CONFIG_DU is not set +# CONFIG_FEATURE_DU_DEFALT_BLOCKSIZE_1K is not set +CONFIG_ECHO=y +CONFIG_FEATURE_FANCY_ECHO=y +# CONFIG_ENV is not set +# CONFIG_EXPR is not set +# CONFIG_EXPR_MATH_SUPPORT_64 is not set +CONFIG_FALSE=y +# CONFIG_FOLD is not set +# CONFIG_HEAD is not set +# CONFIG_FEATURE_FANCY_HEAD is not set +# CONFIG_HOSTID is not set +# CONFIG_ID is not set +# CONFIG_INSTALL is not set +# CONFIG_LENGTH is not set +CONFIG_LN=y +# CONFIG_LOGNAME is not set +CONFIG_LS=y +# CONFIG_FEATURE_LS_FILETYPES is not set +# CONFIG_FEATURE_LS_FOLLOWLINKS is not set +# CONFIG_FEATURE_LS_RECURSIVE is not set +CONFIG_FEATURE_LS_SORTFILES=y +CONFIG_FEATURE_LS_TIMESTAMPS=y +CONFIG_FEATURE_LS_USERNAME=y +# CONFIG_FEATURE_LS_COLOR is not set +# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set +# CONFIG_MD5SUM is not set +CONFIG_MKDIR=y +# CONFIG_MKFIFO is not set +CONFIG_MKNOD=y +CONFIG_MV=y +# CONFIG_NICE is not set +# CONFIG_NOHUP is not set +# CONFIG_OD is not set +# CONFIG_PRINTENV is not set +# CONFIG_PRINTF is not set +CONFIG_PWD=y +# CONFIG_REALPATH is not set +CONFIG_RM=y +# CONFIG_RMDIR is not set +# CONFIG_SEQ is not set +# CONFIG_SHA1SUM is not set +# CONFIG_SLEEP is not set +# CONFIG_FEATURE_FANCY_SLEEP is not set +# CONFIG_SORT is not set +#
[LinuxBIOS] r93 - buildrom-devel/packages/busybox/conf
Author: myles Date: 2008-01-11 21:02:53 +0100 (Fri, 11 Jan 2008) New Revision: 93 Added: buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 Log: Sorry I missed this file in an earlier commit. Signed-off-by: Myles Watson <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Added: buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 === --- buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 (rev 0) +++ buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 2008-01-11 20:02:53 UTC (rev 93) @@ -0,0 +1,598 @@ +# +# Automatically generated make config: don't edit +# +HAVE_DOT_CONFIG=y + +# +# Busybox Settings +# + +# +# General Configuration +# +CONFIG_FEATURE_BUFFERS_USE_MALLOC=y +# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set +# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set +# CONFIG_FEATURE_VERBOSE_USAGE is not set +# CONFIG_FEATURE_INSTALLER is not set +# CONFIG_LOCALE_SUPPORT is not set +# CONFIG_FEATURE_DEVFS is not set +CONFIG_FEATURE_DEVPTS=y +# CONFIG_FEATURE_CLEAN_UP is not set +CONFIG_FEATURE_SUID=y +# CONFIG_FEATURE_SUID_CONFIG is not set +# CONFIG_FEATURE_SUID_CONFIG_QUIET is not set +# CONFIG_SELINUX is not set + +# +# Build Options +# +# CONFIG_STATIC is not set +# CONFIG_DISABLE_SHARED is not set +# CONFIG_BUILD_LIBBUSYBOX is not set +# CONFIG_FEATURE_FULL_LIBBUSYBOX is not set +# CONFIG_FEATURE_SHARED_BUSYBOX is not set +CONFIG_LFS=y +# USING_CROSS_COMPILER is not set +CROSS_COMPILER_PREFIX="" +EXTRA_CFLAGS_OPTIONS="" +# CONFIG_BUILD_AT_ONCE is not set + +# +# Debugging Options +# +# CONFIG_DEBUG is not set +# CONFIG_NO_DEBUG_LIB is not set +# CONFIG_DMALLOC is not set +# CONFIG_EFENCE is not set +CONFIG_DEBUG_YANK_SUSv2=y + +# +# Installation Options +# +# CONFIG_INSTALL_NO_USR is not set +CONFIG_INSTALL_APPLET_SYMLINKS=y +# CONFIG_INSTALL_APPLET_HARDLINKS is not set +# CONFIG_INSTALL_APPLET_DONT is not set +PREFIX="./_install" + +# +# Busybox Library Tuning +# +CONFIG_MD5_SIZE_VS_SPEED=2 + +# +# Applets +# + +# +# Archival Utilities +# +# CONFIG_AR is not set +# CONFIG_FEATURE_AR_LONG_FILENAMES is not set +# CONFIG_BUNZIP2 is not set +# CONFIG_CPIO is not set +# CONFIG_DPKG is not set +# CONFIG_DPKG_DEB is not set +# CONFIG_FEATURE_DPKG_DEB_EXTRACT_ONLY is not set +# CONFIG_GUNZIP is not set +# CONFIG_FEATURE_GUNZIP_UNCOMPRESS is not set +# CONFIG_GZIP is not set +# CONFIG_RPM2CPIO is not set +# CONFIG_RPM is not set +# CONFIG_TAR is not set +# CONFIG_FEATURE_TAR_CREATE is not set +# CONFIG_FEATURE_TAR_BZIP2 is not set +# CONFIG_FEATURE_TAR_LZMA is not set +# CONFIG_FEATURE_TAR_FROM is not set +# CONFIG_FEATURE_TAR_GZIP is not set +# CONFIG_FEATURE_TAR_COMPRESS is not set +# CONFIG_FEATURE_TAR_OLDGNU_COMPATABILITY is not set +# CONFIG_FEATURE_TAR_GNU_EXTENSIONS is not set +# CONFIG_FEATURE_TAR_LONG_OPTIONS is not set +# CONFIG_UNCOMPRESS is not set +# CONFIG_UNLZMA is not set +# CONFIG_FEATURE_LZMA_FAST is not set +# CONFIG_UNZIP is not set +# CONFIG_FEATURE_UNARCHIVE_TAPE is not set +# CONFIG_FEATURE_DEB_TAR_GZ is not set +# CONFIG_FEATURE_DEB_TAR_BZ2 is not set +# CONFIG_FEATURE_DEB_TAR_LZMA is not set + +# +# Coreutils +# +CONFIG_BASENAME=y +# CONFIG_CAL is not set +CONFIG_CAT=y +# CONFIG_CHGRP is not set +# CONFIG_CHMOD is not set +# CONFIG_CHOWN is not set +# CONFIG_CHROOT is not set +# CONFIG_CMP is not set +# CONFIG_COMM is not set +CONFIG_CP=y +# CONFIG_CUT is not set +# CONFIG_DATE is not set +# CONFIG_FEATURE_DATE_ISOFMT is not set +CONFIG_DD=y +# CONFIG_DF is not set +# CONFIG_DIRNAME is not set +# CONFIG_DOS2UNIX is not set +# CONFIG_UNIX2DOS is not set +# CONFIG_DU is not set +# CONFIG_FEATURE_DU_DEFALT_BLOCKSIZE_1K is not set +CONFIG_ECHO=y +CONFIG_FEATURE_FANCY_ECHO=y +# CONFIG_ENV is not set +# CONFIG_EXPR is not set +# CONFIG_EXPR_MATH_SUPPORT_64 is not set +CONFIG_FALSE=y +# CONFIG_FOLD is not set +# CONFIG_HEAD is not set +# CONFIG_FEATURE_FANCY_HEAD is not set +# CONFIG_HOSTID is not set +# CONFIG_ID is not set +# CONFIG_INSTALL is not set +# CONFIG_LENGTH is not set +CONFIG_LN=y +# CONFIG_LOGNAME is not set +CONFIG_LS=y +# CONFIG_FEATURE_LS_FILETYPES is not set +# CONFIG_FEATURE_LS_FOLLOWLINKS is not set +# CONFIG_FEATURE_LS_RECURSIVE is not set +CONFIG_FEATURE_LS_SORTFILES=y +CONFIG_FEATURE_LS_TIMESTAMPS=y +CONFIG_FEATURE_LS_USERNAME=y +# CONFIG_FEATURE_LS_COLOR is not set +# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set +# CONFIG_MD5SUM is not set +CONFIG_MKDIR=y +# CONFIG_MKFIFO is not set +CONFIG_MKNOD=y +CONFIG_MV=y +# CONFIG_NICE is not set +# CONFIG_NOHUP is not set +# CONFIG_OD is not set +# CONFIG_PRINTENV is not set +# CONFIG_PRINTF is not set +CONFIG_PWD=y +# CONFIG_REALPATH is not set +CONFIG_RM=y +# CONFIG_RMDIR is not set +# CONFIG_SEQ is not set +# CONFIG_SHA1SUM is not set +# CONFIG_SLEEP is not set +# CONFIG_FEATURE_FANCY_SLEEP is not set +# CONFIG_SORT is not set +#
[LinuxBIOS] r92 - buildrom-devel/packages/linuxbios
Author: jcrouse
Date: 2008-01-11 20:17:38 +0100 (Fri, 11 Jan 2008)
New Revision: 92
Removed:
buildrom-devel/packages/linuxbios/CL2.5.patch
Log:
Remove a OLPC refugee that I must have missed. Trivial.
Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Deleted: buildrom-devel/packages/linuxbios/CL2.5.patch
===
--- buildrom-devel/packages/linuxbios/CL2.5.patch 2008-01-11 18:22:53 UTC
(rev 91)
+++ buildrom-devel/packages/linuxbios/CL2.5.patch 2008-01-11 19:17:38 UTC
(rev 92)
@@ -1,17 +0,0 @@
-Index: src/mainboard/olpc/rev_a/auto.c
-===
a/src/mainboard/olpc/rev_a/auto.c (revision 2392)
-+++ b/src/mainboard/olpc/rev_a/auto.c (working copy)
-@@ -122,10 +122,11 @@
- /* the msr value reported by quanta is very, very different.
-* we will go with that value for now.
-*/
-- msr.lo = 0x286332a3;
-+ msr.lo = 0x686332a3;
-
- wrmsr(0x2019, msr);
-
-+ print_err("CL2.5 Set\n");
- }
-
- #include "northbridge/amd/gx2/raminit.c"
--
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[LinuxBIOS] r92 - buildrom-devel/packages/linuxbios
Author: jcrouse
Date: 2008-01-11 20:17:38 +0100 (Fri, 11 Jan 2008)
New Revision: 92
Removed:
buildrom-devel/packages/linuxbios/CL2.5.patch
Log:
Remove a OLPC refugee that I must have missed. Trivial.
Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Deleted: buildrom-devel/packages/linuxbios/CL2.5.patch
===
--- buildrom-devel/packages/linuxbios/CL2.5.patch 2008-01-11 18:22:53 UTC
(rev 91)
+++ buildrom-devel/packages/linuxbios/CL2.5.patch 2008-01-11 19:17:38 UTC
(rev 92)
@@ -1,17 +0,0 @@
-Index: src/mainboard/olpc/rev_a/auto.c
-===
a/src/mainboard/olpc/rev_a/auto.c (revision 2392)
-+++ b/src/mainboard/olpc/rev_a/auto.c (working copy)
-@@ -122,10 +122,11 @@
- /* the msr value reported by quanta is very, very different.
-* we will go with that value for now.
-*/
-- msr.lo = 0x286332a3;
-+ msr.lo = 0x686332a3;
-
- wrmsr(0x2019, msr);
-
-+ print_err("CL2.5 Set\n");
- }
-
- #include "northbridge/amd/gx2/raminit.c"
--
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[LinuxBIOS] r3046 - trunk/LinuxBIOSv2/targets
Author: jcrouse Date: 2008-01-11 19:23:47 +0100 (Fri, 11 Jan 2008) New Revision: 3046 Modified: trunk/LinuxBIOSv2/targets/buildtarget Log: Add the ability to extend CFLAGS as needed for several new distros Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Peter Stuge <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/buildtarget === --- trunk/LinuxBIOSv2/targets/buildtarget 2008-01-11 00:32:07 UTC (rev 3045) +++ trunk/LinuxBIOSv2/targets/buildtarget 2008-01-11 18:23:47 UTC (rev 3046) @@ -53,4 +53,25 @@ export PYTHONPATH=$config_dir $PYTHON $config_py $config_lb $lbpath +# now start checking for distro-specific breakage. +## This check is for the no stack protector mess. +EXTRA_CFLAGS= + +if [ -z "$CC" ]; then + CC=gcc +fi + +$CC -fno-stack-protector -S -xc /dev/null -o .$$.tmp + +if [ $? -eq 0 ]; then + EXTRA_CFLAGS=-fno-stack-protector +fi + +rm -rf .$$.tmp + +for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings +do + echo CFLAGS+=$EXTRA_CFLAGS >>$i +done + exit $? -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3046 - trunk/LinuxBIOSv2/targets
Author: jcrouse Date: 2008-01-11 19:23:47 +0100 (Fri, 11 Jan 2008) New Revision: 3046 Modified: trunk/LinuxBIOSv2/targets/buildtarget Log: Add the ability to extend CFLAGS as needed for several new distros Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Peter Stuge <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/buildtarget === --- trunk/LinuxBIOSv2/targets/buildtarget 2008-01-11 00:32:07 UTC (rev 3045) +++ trunk/LinuxBIOSv2/targets/buildtarget 2008-01-11 18:23:47 UTC (rev 3046) @@ -53,4 +53,25 @@ export PYTHONPATH=$config_dir $PYTHON $config_py $config_lb $lbpath +# now start checking for distro-specific breakage. +## This check is for the no stack protector mess. +EXTRA_CFLAGS= + +if [ -z "$CC" ]; then + CC=gcc +fi + +$CC -fno-stack-protector -S -xc /dev/null -o .$$.tmp + +if [ $? -eq 0 ]; then + EXTRA_CFLAGS=-fno-stack-protector +fi + +rm -rf .$$.tmp + +for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings +do + echo CFLAGS+=$EXTRA_CFLAGS >>$i +done + exit $? -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r91 - in buildrom-devel: . packages packages/linuxbios packages/linuxbiosv3 packages/linuxbiosv3/conf packages/roms
not set + +# +# Devices +# +CONFIG_PCI_OPTION_ROM_RUN=y +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set +CONFIG_PCI_OPTION_ROM_RUN_VM86=y +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set +# CONFIG_MULTIPLE_VGA_INIT is not set +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y +CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y +CONFIG_SUPERIO_WINBOND_W83627HF=y +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 + +# +# Payload +# +# CONFIG_PAYLOAD_PREPARSE_ELF is not set +# CONFIG_PAYLOAD_ELF is not set +CONFIG_PAYLOAD_NONE=y Added: buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk === --- buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk (rev 0) +++ buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk 2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,76 @@ +ifeq ($(LBV3_TAG),) +$(error You need to specify a version to pull in your platform config) +endif + +LBV3_URL=svn://openbios.org/repository/LinuxBIOSv3 +LBV3_TARBALL=linuxbios-svn-$(LBV3_TAG).tar.gz +LBV3_DIR=$(BUILD_DIR)/linuxbiosv3 +LBV3_SRC_DIR=$(LBV3_DIR)/svn + +LBV3_STAMP_DIR=$(LBV3_DIR)/stamps +LBV3_LOG_DIR=$(LBV3_DIR)/logs + +ifeq ($(CONFIG_VERBOSE),y) +LBV3_FETCH_LOG=/dev/stdout +LBV3_CONFIG_LOG=/dev/stdout +LBV3_BUILD_LOG=/dev/stdout +else +LBV3_FETCH_LOG=$(LBV3_LOG_DIR)/fetch.log +LBV3_CONFIG_LOG=$(LBV3_LOG_DIR)/config.log +LBV3_BUILD_LOG=$(LBV3_LOG_DIR)/build.log +endif + +TARGET_ROM = $(LINUXBIOS_VENDOR)-$(LINUXBIOS_BOARD).rom + +LBV3_OUTPUT=$(LBV3_SRC_DIR)/build/linuxbios.rom + +LBV3_PATCHES ?= + +$(SOURCE_DIR)/$(LBV3_TARBALL): + @ mkdir -p $(SOURCE_DIR)/linuxbiosv3 + @ $(BIN_DIR)/fetchsvn.sh $(LBV3_URL) \ + $(SOURCE_DIR)/linuxbiosv3 $(LBV3_TAG) \ + $@ > $(LBV3_FETCH_LOG) 2>&1 + +$(LBV3_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(LBV3_TARBALL) + @echo "Unpacking LinuxBIOSv3..." + @ mkdir -p $(LBV3_DIR) + @ tar -C $(LBV3_DIR) -zxf $(SOURCE_DIR)/$(LBV3_TARBALL) + @ touch $@ + +$(LBV3_STAMP_DIR)/.patched: $(LBV3_STAMP_DIR)/.unpacked + @ echo "Patching LinuxBIOSv3..." + @ $(BIN_DIR)/doquilt.sh $(LBV3_SRC_DIR) $(LBV3_PATCHES) + @ touch $@ + +$(LBV3_STAMP_DIR)/.configured: $(LBV3_STAMP_DIR)/.patched + @ echo "Configuring LinuxBIOSv3..." + @ cp $(PACKAGE_DIR)/linuxbiosv3/conf/$(LBV3_CONFIG) $(LBV3_SRC_DIR)/.config + @ make -C $(LBV3_SRC_DIR) oldconfig > $(LBV3_CONFIG_LOG) 2>&1 + @ touch $@ + +$(LBV3_OUTPUT): $(LBV3_STAMP_DIR)/.configured + @ echo "Building LinuxBIOSv3..." + @ $(MAKE) -C $(LBV3_SRC_DIR) > $(LBV3_BUILD_LOG) 2>&1 + +$(LBV3_SRC_DIR)/build/util/lar/lar: $(LBV3_STAMP_DIR)/.configured + @ $(MAKE) -C $(LBV3_SRC_DIR)/util lar > $(LBV3_BUILD_LOG) 2>&1 + +$(STAGING_DIR)/bin/lar: $(LBV3_SRC_DIR)/build/util/lar/lar + @ mkdir -p $(STAGING_DIR)/bin + @ cp $< $@ + + +$(LBV3_STAMP_DIR) $(LBV3_LOG_DIR): + @ mkdir -p $@ + +linuxbiosv3: $(LBV3_LOG_DIR) $(LBV3_STAMP_DIR) $(LBV3_OUTPUT) $(STAGING_DIR)/bin/lar + +linuxbiosv3-clean: + @ echo "Cleaning linuxbiosv3..." + @ $(MAKE) -C $(LBV3_SRC_DIR) clean > /dev/null 2>&1 + +linuxbiosv3-distclean: + @ rm -rf $(LBV3_DIR)/* + @ rm -rf $(STAGING_DIR)/bin/lar + Added: buildrom-devel/packages/roms/rom-geode.inc === --- buildrom-devel/packages/roms/rom-geode.inc (rev 0) +++ buildrom-devel/packages/roms/rom-geode.inc 2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,17 @@ +# This is the geode specific optionrom target +# download VSA + +VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ +GEODE_VSA=lx_vsa.36k.bin + +$(SOURCE_DIR)/$(GEODE_VSA): + @ echo "Fetching the VSA code..." + @ wget -P $(SOURCE_DIR) $(VSA_URL)/$(GEODE_VSA).gz -O $@ + +# Copy the file to the ROM_DIR - it should have the same name that it +# will have in the LAR + +$(ROM_DIR)/vsa: $(SOURCE_DIR)/$(GEODE_VSA): + @ cp $< $@ + +OPTIONROM_TARGETS += $(ROM_DIR)/vsa Added: buildrom-devel/packages/roms/roms.mk === --- buildrom-devel/packages/roms/roms.mk(rev 0) +++ buildrom-devel/packages/roms/roms.mk2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,22 @@ +# Each platform that needs an option ROM or other binary blob is specified +# here + + +OPTIONROM_TARGETS= + +OPTIONROM-y = +OPTIONROM-$(CONFIG_PLATFORM_NORWICH) += rom-geode.inc + +ifneq ($(OPTIONROMS-y),) +include $(OPTIONROM-y) +endif + +$(ROM_DIR): + mkdir -p $(ROM_DIR) + +roms: $(ROM_DIR) $(OPTIONROM_TARGETS) + +roms-clean: + @ rm -rf $(OPTIONROM_TARGETS) + +roms-distclean: roms-clean -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r91 - in buildrom-devel: . packages packages/linuxbios packages/linuxbiosv3 packages/linuxbiosv3/conf packages/roms
not set + +# +# Devices +# +CONFIG_PCI_OPTION_ROM_RUN=y +# CONFIG_PCI_OPTION_ROM_RUN_X86EMU is not set +CONFIG_PCI_OPTION_ROM_RUN_VM86=y +# CONFIG_PCI_OPTION_ROM_RUN_NONE is not set +# CONFIG_MULTIPLE_VGA_INIT is not set +# CONFIG_INITIALIZE_ONBOARD_VGA_FIRST is not set +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION=y +CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y +CONFIG_SUPERIO_WINBOND_W83627HF=y +CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE=32 + +# +# Payload +# +# CONFIG_PAYLOAD_PREPARSE_ELF is not set +# CONFIG_PAYLOAD_ELF is not set +CONFIG_PAYLOAD_NONE=y Added: buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk === --- buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk (rev 0) +++ buildrom-devel/packages/linuxbiosv3/linuxbiosv3.mk 2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,76 @@ +ifeq ($(LBV3_TAG),) +$(error You need to specify a version to pull in your platform config) +endif + +LBV3_URL=svn://openbios.org/repository/LinuxBIOSv3 +LBV3_TARBALL=linuxbios-svn-$(LBV3_TAG).tar.gz +LBV3_DIR=$(BUILD_DIR)/linuxbiosv3 +LBV3_SRC_DIR=$(LBV3_DIR)/svn + +LBV3_STAMP_DIR=$(LBV3_DIR)/stamps +LBV3_LOG_DIR=$(LBV3_DIR)/logs + +ifeq ($(CONFIG_VERBOSE),y) +LBV3_FETCH_LOG=/dev/stdout +LBV3_CONFIG_LOG=/dev/stdout +LBV3_BUILD_LOG=/dev/stdout +else +LBV3_FETCH_LOG=$(LBV3_LOG_DIR)/fetch.log +LBV3_CONFIG_LOG=$(LBV3_LOG_DIR)/config.log +LBV3_BUILD_LOG=$(LBV3_LOG_DIR)/build.log +endif + +TARGET_ROM = $(LINUXBIOS_VENDOR)-$(LINUXBIOS_BOARD).rom + +LBV3_OUTPUT=$(LBV3_SRC_DIR)/build/linuxbios.rom + +LBV3_PATCHES ?= + +$(SOURCE_DIR)/$(LBV3_TARBALL): + @ mkdir -p $(SOURCE_DIR)/linuxbiosv3 + @ $(BIN_DIR)/fetchsvn.sh $(LBV3_URL) \ + $(SOURCE_DIR)/linuxbiosv3 $(LBV3_TAG) \ + $@ > $(LBV3_FETCH_LOG) 2>&1 + +$(LBV3_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(LBV3_TARBALL) + @echo "Unpacking LinuxBIOSv3..." + @ mkdir -p $(LBV3_DIR) + @ tar -C $(LBV3_DIR) -zxf $(SOURCE_DIR)/$(LBV3_TARBALL) + @ touch $@ + +$(LBV3_STAMP_DIR)/.patched: $(LBV3_STAMP_DIR)/.unpacked + @ echo "Patching LinuxBIOSv3..." + @ $(BIN_DIR)/doquilt.sh $(LBV3_SRC_DIR) $(LBV3_PATCHES) + @ touch $@ + +$(LBV3_STAMP_DIR)/.configured: $(LBV3_STAMP_DIR)/.patched + @ echo "Configuring LinuxBIOSv3..." + @ cp $(PACKAGE_DIR)/linuxbiosv3/conf/$(LBV3_CONFIG) $(LBV3_SRC_DIR)/.config + @ make -C $(LBV3_SRC_DIR) oldconfig > $(LBV3_CONFIG_LOG) 2>&1 + @ touch $@ + +$(LBV3_OUTPUT): $(LBV3_STAMP_DIR)/.configured + @ echo "Building LinuxBIOSv3..." + @ $(MAKE) -C $(LBV3_SRC_DIR) > $(LBV3_BUILD_LOG) 2>&1 + +$(LBV3_SRC_DIR)/build/util/lar/lar: $(LBV3_STAMP_DIR)/.configured + @ $(MAKE) -C $(LBV3_SRC_DIR)/util lar > $(LBV3_BUILD_LOG) 2>&1 + +$(STAGING_DIR)/bin/lar: $(LBV3_SRC_DIR)/build/util/lar/lar + @ mkdir -p $(STAGING_DIR)/bin + @ cp $< $@ + + +$(LBV3_STAMP_DIR) $(LBV3_LOG_DIR): + @ mkdir -p $@ + +linuxbiosv3: $(LBV3_LOG_DIR) $(LBV3_STAMP_DIR) $(LBV3_OUTPUT) $(STAGING_DIR)/bin/lar + +linuxbiosv3-clean: + @ echo "Cleaning linuxbiosv3..." + @ $(MAKE) -C $(LBV3_SRC_DIR) clean > /dev/null 2>&1 + +linuxbiosv3-distclean: + @ rm -rf $(LBV3_DIR)/* + @ rm -rf $(STAGING_DIR)/bin/lar + Added: buildrom-devel/packages/roms/rom-geode.inc === --- buildrom-devel/packages/roms/rom-geode.inc (rev 0) +++ buildrom-devel/packages/roms/rom-geode.inc 2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,17 @@ +# This is the geode specific optionrom target +# download VSA + +VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/ +GEODE_VSA=lx_vsa.36k.bin + +$(SOURCE_DIR)/$(GEODE_VSA): + @ echo "Fetching the VSA code..." + @ wget -P $(SOURCE_DIR) $(VSA_URL)/$(GEODE_VSA).gz -O $@ + +# Copy the file to the ROM_DIR - it should have the same name that it +# will have in the LAR + +$(ROM_DIR)/vsa: $(SOURCE_DIR)/$(GEODE_VSA): + @ cp $< $@ + +OPTIONROM_TARGETS += $(ROM_DIR)/vsa Added: buildrom-devel/packages/roms/roms.mk === --- buildrom-devel/packages/roms/roms.mk(rev 0) +++ buildrom-devel/packages/roms/roms.mk2008-01-11 18:22:53 UTC (rev 91) @@ -0,0 +1,22 @@ +# Each platform that needs an option ROM or other binary blob is specified +# here + + +OPTIONROM_TARGETS= + +OPTIONROM-y = +OPTIONROM-$(CONFIG_PLATFORM_NORWICH) += rom-geode.inc + +ifneq ($(OPTIONROMS-y),) +include $(OPTIONROM-y) +endif + +$(ROM_DIR): + mkdir -p $(ROM_DIR) + +roms: $(ROM_DIR) $(OPTIONROM_TARGETS) + +roms-clean: + @ rm -rf $(OPTIONROM_TARGETS) + +roms-distclean: roms-clean -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r90 - in buildrom-devel: . config/platforms packages/linuxbios packages/linuxbios/conf.v3
fig/platforms/qemu.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/qemu.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -12,7 +12,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/qemu.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/qemu.mk # kernel configuration (for LAB) @@ -23,21 +23,19 @@ # Etherboot configuration ETHERBOOT_ARCH=i386 -# LinuxBIOS configuration - -ifeq ($(CONFIG_LINUXBIOS_V3),y) -LINUXBIOS_TAG=HEAD -LINUXBIOS_V3_CONFIG=$(PACKAGE_DIR)/linuxbios/conf.v3/qemu.conf -LINUXBIOS_ROM_NAME=build/linuxbios.rom -else -LINUXBIOS_TAG=2950 -LINUXBIOS_CONFIG=Config.lb +# LinuxBIOSv2 configuration +LBV2_TAG=2950 +LBV2_CONFIG=Config.lb LINUXBIOS_ROM_NAME=qemu.rom -endif +# LinuxBIOS v3 configuration +LBV3_CONFIG=qemu-i386-defconfig +LBV3_TAG=HEAD +LBV3_ROM_NAME=linuxbios.rom + LINUXBIOS_VENDOR=emulation LINUXBIOS_BOARD=qemu-i386 -LINUXBIOS_TDIR=qemu-i386 +LBV2_TDIR=qemu-i386 # FILO configuration Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf === --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -18,7 +18,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/serengeti_cheetah-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/serengeti_cheetah.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/serengeti_cheetah.mk # kernel configuration (for LAB) @@ -42,19 +42,19 @@ # LinuxBIOS configuration +LINUXBIOS_VENDOR=amd +LBV2_CONFIG=Config.lb + ifeq ($(CONFIG_PLATFORM_CHEETAH_FAM10),y) -LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah_fam10 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=serengeti_cheetah_fam10 -LINUXBIOS_TAG=3018 +LBV2_TDIR=serengeti_cheetah_fam10 +LBV2_TAG=3018 LINUXBIOS_ROM_NAME=amd-cheetah-fam10.rom else -LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=serengeti_cheetah -LINUXBIOS_TAG=2950 +LBV2_CONFIG=Config.lb +LBV2_TDIR=serengeti_cheetah +LBV2_TAG=2950 LINUXBIOS_ROM_NAME=serengeti_cheetah.rom endif Modified: buildrom-devel/config/platforms/supermicro-h8dmr.conf === --- buildrom-devel/config/platforms/supermicro-h8dmr.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/supermicro-h8dmr.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/supermicro-h8dmr-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/supermicro-h8dmr-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/supermicro-h8dmr-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=supermicro LINUXBIOS_BOARD=h8dmr -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=h8dmr -LINUXBIOS_TAG=2996 +LBV2_CONFIG=Config.lb +LBV2_TDIR=h8dmr +LBV2_TAG=2996 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/tyan-s2882.conf === --- buildrom-devel/config/platforms/tyan-s2882.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/tyan-s2882.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/tyan-s2882-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2882-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2882-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=tyan LINUXBIOS_BOARD=s2882 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=s2882 -LINUXBIOS_TAG=2887 +LBV2_CONFIG=Config.lb +LBV2_TDIR=s2882 +LBV2_TAG=2887 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/tyan-s2891.conf === --- buildrom-devel/config/platforms/tyan-s2891.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/tyan-s2891.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/tyan-s2891-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2891-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2891-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=tyan LINUXBIOS_BOARD=s2891 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=s2891 -LINUXBIOS_TAG=2792 +LBV2_CONFIG=Config.lb +LBV2_TDIR=s2891 +LBV2_TAG=2792 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk === --- buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk 2008-01-11 17:38:23 UTC (rev 90) @@ -1,37 +1,37
[LinuxBIOS] r90 - in buildrom-devel: . config/platforms packages/linuxbios packages/linuxbios/conf.v3
fig/platforms/qemu.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/qemu.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -12,7 +12,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/qemu.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/qemu.mk # kernel configuration (for LAB) @@ -23,21 +23,19 @@ # Etherboot configuration ETHERBOOT_ARCH=i386 -# LinuxBIOS configuration - -ifeq ($(CONFIG_LINUXBIOS_V3),y) -LINUXBIOS_TAG=HEAD -LINUXBIOS_V3_CONFIG=$(PACKAGE_DIR)/linuxbios/conf.v3/qemu.conf -LINUXBIOS_ROM_NAME=build/linuxbios.rom -else -LINUXBIOS_TAG=2950 -LINUXBIOS_CONFIG=Config.lb +# LinuxBIOSv2 configuration +LBV2_TAG=2950 +LBV2_CONFIG=Config.lb LINUXBIOS_ROM_NAME=qemu.rom -endif +# LinuxBIOS v3 configuration +LBV3_CONFIG=qemu-i386-defconfig +LBV3_TAG=HEAD +LBV3_ROM_NAME=linuxbios.rom + LINUXBIOS_VENDOR=emulation LINUXBIOS_BOARD=qemu-i386 -LINUXBIOS_TDIR=qemu-i386 +LBV2_TDIR=qemu-i386 # FILO configuration Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf === --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -18,7 +18,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/serengeti_cheetah-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/serengeti_cheetah.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/serengeti_cheetah.mk # kernel configuration (for LAB) @@ -42,19 +42,19 @@ # LinuxBIOS configuration +LINUXBIOS_VENDOR=amd +LBV2_CONFIG=Config.lb + ifeq ($(CONFIG_PLATFORM_CHEETAH_FAM10),y) -LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah_fam10 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=serengeti_cheetah_fam10 -LINUXBIOS_TAG=3018 +LBV2_TDIR=serengeti_cheetah_fam10 +LBV2_TAG=3018 LINUXBIOS_ROM_NAME=amd-cheetah-fam10.rom else -LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=serengeti_cheetah -LINUXBIOS_TAG=2950 +LBV2_CONFIG=Config.lb +LBV2_TDIR=serengeti_cheetah +LBV2_TAG=2950 LINUXBIOS_ROM_NAME=serengeti_cheetah.rom endif Modified: buildrom-devel/config/platforms/supermicro-h8dmr.conf === --- buildrom-devel/config/platforms/supermicro-h8dmr.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/supermicro-h8dmr.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/supermicro-h8dmr-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/supermicro-h8dmr-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/supermicro-h8dmr-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=supermicro LINUXBIOS_BOARD=h8dmr -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=h8dmr -LINUXBIOS_TAG=2996 +LBV2_CONFIG=Config.lb +LBV2_TDIR=h8dmr +LBV2_TAG=2996 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/tyan-s2882.conf === --- buildrom-devel/config/platforms/tyan-s2882.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/tyan-s2882.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/tyan-s2882-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2882-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2882-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=tyan LINUXBIOS_BOARD=s2882 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=s2882 -LINUXBIOS_TAG=2887 +LBV2_CONFIG=Config.lb +LBV2_TDIR=s2882 +LBV2_TAG=2887 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/config/platforms/tyan-s2891.conf === --- buildrom-devel/config/platforms/tyan-s2891.conf 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/config/platforms/tyan-s2891.conf 2008-01-11 17:38:23 UTC (rev 90) @@ -17,7 +17,7 @@ # Targets KERNEL_MK=$(PACKAGE_DIR)/kernel/tyan-s2891-kernel.mk -LINUXBIOS_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2891-linuxbios.mk +LBV2_MK=$(PACKAGE_DIR)/linuxbios/tyan-s2891-linuxbios.mk # kernel configuration (for LAB) @@ -38,9 +38,9 @@ LINUXBIOS_VENDOR=tyan LINUXBIOS_BOARD=s2891 -LINUXBIOS_CONFIG=Config.lb -LINUXBIOS_TDIR=s2891 -LINUXBIOS_TAG=2792 +LBV2_CONFIG=Config.lb +LBV2_TDIR=s2891 +LBV2_TAG=2792 LINUXBIOS_ROM_NAME=linuxbios.rom # FILO configuration Modified: buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk === --- buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk 2007-12-22 03:21:44 UTC (rev 89) +++ buildrom-devel/packages/linuxbios/alix1c-linuxbios.mk 2008-01-11 17:38:23 UTC (rev 90) @@ -1,37 +1,37
[LinuxBIOS] r3045 - trunk/util/flashrom
Author: duwe Date: 2008-01-11 01:32:07 +0100 (Fri, 11 Jan 2008) New Revision: 3045 Modified: trunk/util/flashrom/flashrom.c Log: This patch removes '\n' from the help output since this looks a bit strange. After the patch [...] The line length is still below 80 characters. Signed-off-by: Bernhard Walle <[EMAIL PROTECTED]> Acked-by: Torsten Duwe <[EMAIL PROTECTED]> Modified: trunk/util/flashrom/flashrom.c === --- trunk/util/flashrom/flashrom.c 2008-01-10 17:59:25 UTC (rev 3044) +++ trunk/util/flashrom/flashrom.c 2008-01-11 00:32:07 UTC (rev 3045) @@ -206,7 +206,7 @@ " -f | --force: force write without checking image\n" " -l | --layout :read rom layout from file\n" " -i | --image :only flash image name from flash layout\n" -"\n" " If no file is specified, then all that happens\n" +"\n" " If no file is specified, then all that happens" " is that flash info is dumped.\n\n"); exit(1); } -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3045 - trunk/util/flashrom
Author: duwe Date: 2008-01-11 01:32:07 +0100 (Fri, 11 Jan 2008) New Revision: 3045 Modified: trunk/util/flashrom/flashrom.c Log: This patch removes '\n' from the help output since this looks a bit strange. After the patch [...] The line length is still below 80 characters. Signed-off-by: Bernhard Walle <[EMAIL PROTECTED]> Acked-by: Torsten Duwe <[EMAIL PROTECTED]> Modified: trunk/util/flashrom/flashrom.c === --- trunk/util/flashrom/flashrom.c 2008-01-10 17:59:25 UTC (rev 3044) +++ trunk/util/flashrom/flashrom.c 2008-01-11 00:32:07 UTC (rev 3045) @@ -206,7 +206,7 @@ " -f | --force: force write without checking image\n" " -l | --layout :read rom layout from file\n" " -i | --image :only flash image name from flash layout\n" -"\n" " If no file is specified, then all that happens\n" +"\n" " If no file is specified, then all that happens" " is that flash info is dumped.\n\n"); exit(1); } -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r552 - LinuxBIOSv3/arch/x86
Author: hailfinger Date: 2008-01-10 22:13:19 +0100 (Thu, 10 Jan 2008) New Revision: 552 Modified: LinuxBIOSv3/arch/x86/Makefile Log: This fixes a build race (make -j2): make: *** No rule to make target `LinuxBIOSv3/build/stage0-prefixed.o', needed by `LinuxBIOSv3/build/linuxbios.initram'. Stop. Signed-off-by: Robert Millan <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/Makefile === --- LinuxBIOSv3/arch/x86/Makefile 2008-01-09 23:09:23 UTC (rev 551) +++ LinuxBIOSv3/arch/x86/Makefile 2008-01-10 21:13:19 UTC (rev 552) @@ -135,7 +135,7 @@ $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ $(STAGE0_MAINBOARD_OBJ) $(STAGE0_CHIPSET_OBJ) -$(obj)/stage0.o $(obj)/stage0.init: $(STAGE0_OBJ) +$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ) $(Q)# We need to be careful. If stage0.o gets bigger than $(Q)# 0x4000 - 0x100, we will end up with a 4 gig file. $(Q)# I wonder if that behavior is on purpose. -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r552 - LinuxBIOSv3/arch/x86
Author: hailfinger Date: 2008-01-10 22:13:19 +0100 (Thu, 10 Jan 2008) New Revision: 552 Modified: LinuxBIOSv3/arch/x86/Makefile Log: This fixes a build race (make -j2): make: *** No rule to make target `LinuxBIOSv3/build/stage0-prefixed.o', needed by `LinuxBIOSv3/build/linuxbios.initram'. Stop. Signed-off-by: Robert Millan <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/Makefile === --- LinuxBIOSv3/arch/x86/Makefile 2008-01-09 23:09:23 UTC (rev 551) +++ LinuxBIOSv3/arch/x86/Makefile 2008-01-10 21:13:19 UTC (rev 552) @@ -135,7 +135,7 @@ $(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \ $(STAGE0_MAINBOARD_OBJ) $(STAGE0_CHIPSET_OBJ) -$(obj)/stage0.o $(obj)/stage0.init: $(STAGE0_OBJ) +$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ) $(Q)# We need to be careful. If stage0.o gets bigger than $(Q)# 0x4000 - 0x100, we will end up with a 4 gig file. $(Q)# I wonder if that behavior is on purpose. -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3044 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-10 18:59:25 +0100 (Thu, 10 Jan 2008) New Revision: 3044 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: Add a workaround for a bug in some binutils version which strictly interpret whitespace as macro argument delimiter. Since the code is preprocessed by gcc and the tokenizer may insert whitespace, that can fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669 Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:48:25 UTC (rev 3043) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:59:25 UTC (rev 3044) @@ -160,8 +160,15 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + extractmask gas_bug_workaround, %eax + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + extractmask gas_bug_workaround, %edx +/* Without the gas bug workaround, the entire macro would consist only of the + * two lines below. extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ .endm #if CacheSize > 0x1 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3044 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-10 18:59:25 +0100 (Thu, 10 Jan 2008) New Revision: 3044 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: Add a workaround for a bug in some binutils version which strictly interpret whitespace as macro argument delimiter. Since the code is preprocessed by gcc and the tokenizer may insert whitespace, that can fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669 Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:48:25 UTC (rev 3043) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:59:25 UTC (rev 3044) @@ -160,8 +160,15 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) + extractmask gas_bug_workaround, %eax + .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) + extractmask gas_bug_workaround, %edx +/* Without the gas bug workaround, the entire macro would consist only of the + * two lines below. extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ .endm #if CacheSize > 0x1 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3043 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-10 18:48:25 +0100 (Thu, 10 Jan 2008) New Revision: 3043 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: This patch introduces 4k CAR size granularity for the AMD x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Benefits: * a nice code size reduction * less #ifdef clutter for Family 10h * paranoid checks for CAR size * clear abstractions This has been tested by Marc Jones and Jordan Crouse. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 13:27:22 UTC (rev 3042) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:48:25 UTC (rev 3043) @@ -2,6 +2,7 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,82 +121,70 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 - /* enable caching for 64K using fixed mtrr */ - movl$0x268, %ecx /* fix4k_c*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - - movl%edx, %eax - wrmsr - movl$0x269, %ecx - wrmsr +/* 0x06 is the WB IO type for a given 4k segment. + * 0x1e is the MEM IO type for a given 4k segment (K10 and above). + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +#if CAR_FAM10 == 1 +.elseif \segs == 1 + movl $0x1e00, \reg /* WB MEM type */ +.elseif \segs == 2 + movl $0x1e1e, \reg /* WB MEM type */ +.elseif \segs == 3 + movl $0x1e1e1e00, \reg /* WB MEM type */ +.elseif \segs >= 4 + movl $0x1e1e1e1e, \reg /* WB MEM type */ +#else +.elseif \segs == 1 + movl $0x0600, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x0606, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ #endif +.endif +.endm -#if CacheSize == 0xc000 - /* enable caching for 16K using fixed mtrr */ - movl$0x268, %ecx /* fix4k_c4000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - xorl%eax, %eax - wrmsr - /* enable caching for 32K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - movl%edx, %eax - wrmsr +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. #endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif - -#if CacheSize == 0x8000 - /* enable caching for 32K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - movl%edx, %eax - wrmsr +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ +movl$0x268, %ecx /* fix4k_c*/ + simplemask CacheSize, 0x8000 +wrmsr #endif -#if CacheSize < 0x8000 - /* enable caching for 16K/8K/4K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_cc000*/ - #if CacheSize == 0x4000 - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - #endif - #if CacheSize == 0x2000 - #if CAR_FAM10 == 1 - movl
[LinuxBIOS] r3043 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-10 18:48:25 +0100 (Thu, 10 Jan 2008) New Revision: 3043 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: This patch introduces 4k CAR size granularity for the AMD x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Benefits: * a nice code size reduction * less #ifdef clutter for Family 10h * paranoid checks for CAR size * clear abstractions This has been tested by Marc Jones and Jordan Crouse. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 13:27:22 UTC (rev 3042) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-10 17:48:25 UTC (rev 3043) @@ -2,6 +2,7 @@ * This file is part of the LinuxBIOS project. * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -120,82 +121,70 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 - /* enable caching for 64K using fixed mtrr */ - movl$0x268, %ecx /* fix4k_c*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - - movl%edx, %eax - wrmsr - movl$0x269, %ecx - wrmsr +/* 0x06 is the WB IO type for a given 4k segment. + * 0x1e is the MEM IO type for a given 4k segment (K10 and above). + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +#if CAR_FAM10 == 1 +.elseif \segs == 1 + movl $0x1e00, \reg /* WB MEM type */ +.elseif \segs == 2 + movl $0x1e1e, \reg /* WB MEM type */ +.elseif \segs == 3 + movl $0x1e1e1e00, \reg /* WB MEM type */ +.elseif \segs >= 4 + movl $0x1e1e1e1e, \reg /* WB MEM type */ +#else +.elseif \segs == 1 + movl $0x0600, \reg /* WB IO type */ +.elseif \segs == 2 + movl $0x0606, \reg /* WB IO type */ +.elseif \segs == 3 + movl $0x06060600, \reg /* WB IO type */ +.elseif \segs >= 4 + movl $0x06060606, \reg /* WB IO type */ #endif +.endif +.endm -#if CacheSize == 0xc000 - /* enable caching for 16K using fixed mtrr */ - movl$0x268, %ecx /* fix4k_c4000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - xorl%eax, %eax - wrmsr - /* enable caching for 32K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - movl%edx, %eax - wrmsr +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. #endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif - -#if CacheSize == 0x8000 - /* enable caching for 32K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_c8000*/ - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - movl%edx, %eax - wrmsr +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ +movl$0x268, %ecx /* fix4k_c*/ + simplemask CacheSize, 0x8000 +wrmsr #endif -#if CacheSize < 0x8000 - /* enable caching for 16K/8K/4K using fixed mtrr */ - movl$0x269, %ecx /* fix4k_cc000*/ - #if CacheSize == 0x4000 - #if CAR_FAM10 == 1 - movl$0x1e1e1e1e, %edx /* WB MEM type */ - #else - movl$0x06060606, %edx /* WB IO type */ - #endif - #endif - #if CacheSize == 0x2000 - #if CAR_FAM10 == 1 - movl
[LinuxBIOS] r3042 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-10 14:27:22 +0100 (Thu, 10 Jan 2008)
New Revision: 3042
Modified:
trunk/util/flashrom/flashchips.c
Log:
Enable MX25L8005 support in flashrom. The #defines were already there.
Signed-off-by: Harald Gutmann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-09 11:37:58 UTC (rev 3041)
+++ trunk/util/flashrom/flashchips.c2008-01-10 13:27:22 UTC (rev 3042)
@@ -52,6 +52,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"MX25L8005", MX_ID, MX_25L8005, 1024, 256,
+probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF040B", SST_ID, SST_25VF040B, 512,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
--
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[LinuxBIOS] r3042 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-10 14:27:22 +0100 (Thu, 10 Jan 2008)
New Revision: 3042
Modified:
trunk/util/flashrom/flashchips.c
Log:
Enable MX25L8005 support in flashrom. The #defines were already there.
Signed-off-by: Harald Gutmann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-09 11:37:58 UTC (rev 3041)
+++ trunk/util/flashrom/flashchips.c2008-01-10 13:27:22 UTC (rev 3042)
@@ -52,6 +52,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"MX25L8005", MX_ID, MX_25L8005, 1024, 256,
+probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF040B", SST_ID, SST_25VF040B, 512,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
--
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[LinuxBIOS] r551 - LinuxBIOSv3/arch/x86
Author: hailfinger Date: 2008-01-10 00:09:23 +0100 (Thu, 10 Jan 2008) New Revision: 551 Modified: LinuxBIOSv3/arch/x86/stage0_i586.S Log: This patch is an attempt at introducing 4k CAR size granularity for the generic x86 code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. The patch is identical (except one build fix) to what was committed in r3038 to v2. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/stage0_i586.S === --- LinuxBIOSv3/arch/x86/stage0_i586.S 2008-01-09 18:27:49 UTC (rev 550) +++ LinuxBIOSv3/arch/x86/stage0_i586.S 2008-01-09 23:09:23 UTC (rev 551) @@ -301,38 +301,59 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 -/* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x0600, \reg +.elseif \segs == 2 + movl $0x0606, \reg +.elseif \segs == 3 + movl $0x06060600, \reg +.elseif \segs >= 4 + movl $0x06060606, \reg +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ movl$0x268, %ecx /* fix4k_c*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0x8000 wrmsr - movl$0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 -/* enable caching for 32K using fixed mtrr */ +/* enable caching for 0-32K using fixed mtrr */ movl$0x269, %ecx /* fix4k_c8000*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0 wrmsr -#endif -/* enable caching for 16K/8K/4K using fixed mtrr */ -movl$0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 -movl$0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 -movl$0x0606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 -movl$0x0600, %edx /* WB IO type */ -#endif - xorl%eax, %eax - wrmsr - #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r551 - LinuxBIOSv3/arch/x86
Author: hailfinger Date: 2008-01-10 00:09:23 +0100 (Thu, 10 Jan 2008) New Revision: 551 Modified: LinuxBIOSv3/arch/x86/stage0_i586.S Log: This patch is an attempt at introducing 4k CAR size granularity for the generic x86 code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. The patch is identical (except one build fix) to what was committed in r3038 to v2. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/stage0_i586.S === --- LinuxBIOSv3/arch/x86/stage0_i586.S 2008-01-09 18:27:49 UTC (rev 550) +++ LinuxBIOSv3/arch/x86/stage0_i586.S 2008-01-09 23:09:23 UTC (rev 551) @@ -301,38 +301,59 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 -/* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x0600, \reg +.elseif \segs == 2 + movl $0x0606, \reg +.elseif \segs == 3 + movl $0x06060600, \reg +.elseif \segs >= 4 + movl $0x06060606, \reg +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ movl$0x268, %ecx /* fix4k_c*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0x8000 wrmsr - movl$0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 -/* enable caching for 32K using fixed mtrr */ +/* enable caching for 0-32K using fixed mtrr */ movl$0x269, %ecx /* fix4k_c8000*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0 wrmsr -#endif -/* enable caching for 16K/8K/4K using fixed mtrr */ -movl$0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 -movl$0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 -movl$0x0606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 -movl$0x0600, %edx /* WB IO type */ -#endif - xorl%eax, %eax - wrmsr - #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place * on the flash rom. -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r550 - LinuxBIOSv3/lib
Author: mjones
Date: 2008-01-09 19:27:49 +0100 (Wed, 09 Jan 2008)
New Revision: 550
Modified:
LinuxBIOSv3/lib/console.c
Log:
Add hlt() back into the die() function and update the comments.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-07 16:34:34 UTC (rev 549)
+++ LinuxBIOSv3/lib/console.c 2008-01-09 18:27:49 UTC (rev 550)
@@ -83,30 +83,37 @@
}
/**
- * Halt and loop due to a fatal error.
- * There have been several iterations of this function.
+ * Halt and loop due to a fatal error.
+ * There have been several iterations of this function.
* The first simply did a hlt(). Doing a hlt() can make jtag debugging
- * very difficult as one can not break into a hlt instruction on some CPUs.
- * Second was to do a console_tx_byte of a NULL character.
- * A number of concerns were raised about doing this idea.
- * Third idea was to do an inb from port 0x80, the POST port. That design
- * makes us very CPU-specific.
+ * very difficult as one can not break into a hlt instruction on some CPUs.
+ * Second was to do a console_tx_byte of a NULL character.
+ * A number of concerns were raised about doing this idea.
+ * Third idea was to do an inb from port 0x80, the POST port. That design
+ * makes us very CPU-specific.
* The fourth idea was just POSTING the same
- * code over and over. That would erase the most recent POST code,
- * hindering diagnosis.
+ * code over and over. That would erase the most recent POST code,
+ * hindering diagnosis.
*
- * For now, for lack of a good alternative,
- * we will continue to call console_tx_byte. We call with a NULL since
- * it will clear any FIFOs in the path and won't clutter up the output,
- * since NULL doesn't print a visible character on most terminal
- * emulators.
+ * For now, for lack of a better alternative,
+ * we will call console_tx_byte ten times and then halt.
+ * Some CPU JTAG debbuggers might have problems but it is the right thing
+ * to do. We call with a NULL since it will clear any FIFOs in the path and
+ * won't clutter up the output, since NULL doesn't print a visible character
+ * on most terminal emulators.
*
* @param str A string to print for the error
*
*/
void die(const char *str)
{
+ int i;
+
printk(BIOS_EMERG, str);
- while (1)
- console_tx_byte(0, (void *)0);
+
+ while (1) {
+ for (i = 0; i < 10; i++)
+ console_tx_byte(0, (void *)0);
+ hlt();
+ }
}
--
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[LinuxBIOS] r550 - LinuxBIOSv3/lib
Author: mjones
Date: 2008-01-09 19:27:49 +0100 (Wed, 09 Jan 2008)
New Revision: 550
Modified:
LinuxBIOSv3/lib/console.c
Log:
Add hlt() back into the die() function and update the comments.
Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-07 16:34:34 UTC (rev 549)
+++ LinuxBIOSv3/lib/console.c 2008-01-09 18:27:49 UTC (rev 550)
@@ -83,30 +83,37 @@
}
/**
- * Halt and loop due to a fatal error.
- * There have been several iterations of this function.
+ * Halt and loop due to a fatal error.
+ * There have been several iterations of this function.
* The first simply did a hlt(). Doing a hlt() can make jtag debugging
- * very difficult as one can not break into a hlt instruction on some CPUs.
- * Second was to do a console_tx_byte of a NULL character.
- * A number of concerns were raised about doing this idea.
- * Third idea was to do an inb from port 0x80, the POST port. That design
- * makes us very CPU-specific.
+ * very difficult as one can not break into a hlt instruction on some CPUs.
+ * Second was to do a console_tx_byte of a NULL character.
+ * A number of concerns were raised about doing this idea.
+ * Third idea was to do an inb from port 0x80, the POST port. That design
+ * makes us very CPU-specific.
* The fourth idea was just POSTING the same
- * code over and over. That would erase the most recent POST code,
- * hindering diagnosis.
+ * code over and over. That would erase the most recent POST code,
+ * hindering diagnosis.
*
- * For now, for lack of a good alternative,
- * we will continue to call console_tx_byte. We call with a NULL since
- * it will clear any FIFOs in the path and won't clutter up the output,
- * since NULL doesn't print a visible character on most terminal
- * emulators.
+ * For now, for lack of a better alternative,
+ * we will call console_tx_byte ten times and then halt.
+ * Some CPU JTAG debbuggers might have problems but it is the right thing
+ * to do. We call with a NULL since it will clear any FIFOs in the path and
+ * won't clutter up the output, since NULL doesn't print a visible character
+ * on most terminal emulators.
*
* @param str A string to print for the error
*
*/
void die(const char *str)
{
+ int i;
+
printk(BIOS_EMERG, str);
- while (1)
- console_tx_byte(0, (void *)0);
+
+ while (1) {
+ for (i = 0; i < 10; i++)
+ console_tx_byte(0, (void *)0);
+ hlt();
+ }
}
--
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linuxbios@linuxbios.org
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[LinuxBIOS] r3041 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk
Author: hailfinger
Date: 2008-01-09 12:37:58 +0100 (Wed, 09 Jan 2008)
New Revision: 3041
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
Log:
Use macros to improve readability of the device-to-pin IRQ assignments
in GA-2761GXDK mptables.c.
Thanks to Torsten Duwe for initial code.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: ?\232?\148?\161?\230?\152?\142?\232?\128?\128 (Morgan Tsai) <[EMAIL
PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
2008-01-08 19:14:16 UTC (rev 3040)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
2008-01-09 11:37:58 UTC (rev 3041)
@@ -100,44 +100,52 @@
}
}
-/*I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID PIN#
-*/ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x1, apicid_sis966, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, apicid_sis966, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x3, apicid_sis966, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x4, apicid_sis966, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x6, apicid_sis966, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x7, apicid_sis966, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x8, apicid_sis966, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xc, apicid_sis966, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xd, apicid_sis966, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xe, apicid_sis966, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xf, apicid_sis966, 0xf);
+ /* I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID
PIN# */
+ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+1)<<2)|1, apicid_sis966, 0xa);
+/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+ * or its remainings.
+ */
+#define ISA_INT(intr, pin)\
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), apicid_sis966,(pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+2)<<2)|0, apicid_sis966, 0x16); // 22
+ ISA_INT(0x1, 0x1);
+ ISA_INT(0x0, 0x2);
+ ISA_INT(0x3, 0x3);
+ ISA_INT(0x4, 0x4);
+ ISA_INT(0x6, 0x6);
+ ISA_INT(0x7, 0x7);
+ ISA_INT(0x8, 0x8);
+ ISA_INT(0xc, 0xc);
+ ISA_INT(0xd, 0xd);
+ ISA_INT(0xe, 0xe);
+ ISA_INT(0xf, 0xf);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+2)<<2)|1, apicid_sis966, 0x17); // 23
+/* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, fn, pin) \
+smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+6)<<2)|1, apicid_sis966, 0x17); // 23
+PCI_INT(0, sbdn+1, 1, 0xa);
+PCI_INT(0, sbdn+2, 0, 0x16); // 22
+PCI_INT(0, sbdn+2, 1, 0x17); // 23
+PCI_INT(0, sbdn+6, 1, 0x17); // 23
+PCI_INT(0, sbdn+5, 0, 0x14); // 20
+PCI_INT(0, sbdn+5, 1, 0x17); // 23
+PCI_INT(0, sbdn+5, 2, 0x15); // 21
+PCI_INT(0, sbdn+8, 0, 0x16); // 22
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|0, apicid_sis966, 0x14); // 20
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|1, apicid_sis966, 0x17); // 23
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|2, apicid_sis966, 0x15); // 21
-
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+8)<<2)|0, apicid_sis966, 0x16); // 22
-
for(j=7; j>=2; j--) {
if(!bus_sis966[j]) continue;
for(i=0;
[LinuxBIOS] r3041 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk
Author: hailfinger
Date: 2008-01-09 12:37:58 +0100 (Wed, 09 Jan 2008)
New Revision: 3041
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
Log:
Use macros to improve readability of the device-to-pin IRQ assignments
in GA-2761GXDK mptables.c.
Thanks to Torsten Duwe for initial code.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: ?\232?\148?\161?\230?\152?\142?\232?\128?\128 (Morgan Tsai) <[EMAIL
PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
2008-01-08 19:14:16 UTC (rev 3040)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
2008-01-09 11:37:58 UTC (rev 3041)
@@ -100,44 +100,52 @@
}
}
-/*I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID PIN#
-*/ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x1, apicid_sis966, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, apicid_sis966, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x3, apicid_sis966, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x4, apicid_sis966, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x6, apicid_sis966, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x7, apicid_sis966, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x8, apicid_sis966, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xc, apicid_sis966, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xd, apicid_sis966, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xe, apicid_sis966, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xf, apicid_sis966, 0xf);
+ /* I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID
PIN# */
+ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sis966, 0x0);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+1)<<2)|1, apicid_sis966, 0xa);
+/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+ * or its remainings.
+ */
+#define ISA_INT(intr, pin)\
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), apicid_sis966,(pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+2)<<2)|0, apicid_sis966, 0x16); // 22
+ ISA_INT(0x1, 0x1);
+ ISA_INT(0x0, 0x2);
+ ISA_INT(0x3, 0x3);
+ ISA_INT(0x4, 0x4);
+ ISA_INT(0x6, 0x6);
+ ISA_INT(0x7, 0x7);
+ ISA_INT(0x8, 0x8);
+ ISA_INT(0xc, 0xc);
+ ISA_INT(0xd, 0xd);
+ ISA_INT(0xe, 0xe);
+ ISA_INT(0xf, 0xf);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+2)<<2)|1, apicid_sis966, 0x17); // 23
+/* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, fn, pin) \
+smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+6)<<2)|1, apicid_sis966, 0x17); // 23
+PCI_INT(0, sbdn+1, 1, 0xa);
+PCI_INT(0, sbdn+2, 0, 0x16); // 22
+PCI_INT(0, sbdn+2, 1, 0x17); // 23
+PCI_INT(0, sbdn+6, 1, 0x17); // 23
+PCI_INT(0, sbdn+5, 0, 0x14); // 20
+PCI_INT(0, sbdn+5, 1, 0x17); // 23
+PCI_INT(0, sbdn+5, 2, 0x15); // 21
+PCI_INT(0, sbdn+8, 0, 0x16); // 22
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|0, apicid_sis966, 0x14); // 20
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|1, apicid_sis966, 0x17); // 23
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+5)<<2)|2, apicid_sis966, 0x15); // 21
-
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_sis966[0], ((sbdn+8)<<2)|0, apicid_sis966, 0x16); // 22
-
for(j=7; j>=2; j--) {
if(!bus_sis966[j]) continue;
for(i=0;
[LinuxBIOS] r3040 - trunk/LinuxBIOSv2/src/cpu/x86/car
Author: hailfinger Date: 2008-01-08 20:14:16 +0100 (Tue, 08 Jan 2008) New Revision: 3040 Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc Log: Fix compilation of Tyan S2735 which was broken by accident in r3038. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 17:28:35 UTC (rev 3039) +++ trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 19:14:16 UTC (rev 3040) @@ -158,8 +158,8 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset - simplemask_helper (((\carsize - \windowoffset) / 0x1000) - 4), %eax - simplemask_helper (((\carsize - \windowoffset) / 0x1000)), %edx + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx .endm #if CacheSize > 0x1 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3040 - trunk/LinuxBIOSv2/src/cpu/x86/car
Author: hailfinger Date: 2008-01-08 20:14:16 +0100 (Tue, 08 Jan 2008) New Revision: 3040 Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc Log: Fix compilation of Tyan S2735 which was broken by accident in r3038. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 17:28:35 UTC (rev 3039) +++ trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 19:14:16 UTC (rev 3040) @@ -158,8 +158,8 @@ * windowoffset is the 32k-aligned window into CAR size */ .macro simplemask carsize, windowoffset - simplemask_helper (((\carsize - \windowoffset) / 0x1000) - 4), %eax - simplemask_helper (((\carsize - \windowoffset) / 0x1000)), %edx + extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + extractmask (((\carsize - \windowoffset) / 0x1000)), %edx .endm #if CacheSize > 0x1 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3039 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-08 18:28:35 +0100 (Tue, 08 Jan 2008) New Revision: 3039 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: Remove some DOS line endings accidentially introduced in r3014. No code lines affected, so svn blame will not be messed up. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-08 17:06:38 UTC (rev 3038) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-08 17:28:35 UTC (rev 3039) @@ -1,6 +1,6 @@ /* * This file is part of the LinuxBIOS project. - * + * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -15,11 +15,11 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - + */ + #define CacheSize DCACHE_RAM_SIZE #define CacheBase (0xd - CacheSize) - + /* leave some space for global variable to pass to RAM stage */ #define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE @@ -36,7 +36,7 @@ /*for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: - + movb$0xA0, %al outb%al, $0x80 @@ -107,7 +107,7 @@ /* Clear all MTRRs */ xorl%edx, %edx movl$fixed_mtrr_msr, %esi - + clear_fixed_var_mtrr: lodsl (%esi), %eax testl %eax, %eax @@ -245,7 +245,7 @@ movb$0xA1, %al outb%al, $0x80 - + /* enable cache */ movl%cr0, %eax andl$0x9fff, %eax @@ -259,7 +259,7 @@ bt $8, %eax /*BSC */ jnc CAR_FAM10_ap #endif - + movb$0xA2, %al outb%al, $0x80 @@ -280,7 +280,7 @@ /* set up the stack pointer */ movl$(CacheBase + CacheSize - GlobalVarSize), %eax movl%eax, %esp - + movb$0xA3, %al outb%al, $0x80 @@ -316,7 +316,7 @@ jc roll_cfg rolb%cl, %bl roll_cfg: - + /* calculate stack pointer */ movl$CacheSizeAPStack, %eax mull%ebx @@ -337,7 +337,7 @@ /* Restore the BIST result */ movl%ebp, %eax - + /* We need to set ebp ? No need */ movl%esp, %ebp pushl %ebx /* init detected */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3039 - trunk/LinuxBIOSv2/src/cpu/amd/car
Author: hailfinger Date: 2008-01-08 18:28:35 +0100 (Tue, 08 Jan 2008) New Revision: 3039 Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc Log: Remove some DOS line endings accidentially introduced in r3014. No code lines affected, so svn blame will not be messed up. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-08 17:06:38 UTC (rev 3038) +++ trunk/LinuxBIOSv2/src/cpu/amd/car/cache_as_ram.inc 2008-01-08 17:28:35 UTC (rev 3039) @@ -1,6 +1,6 @@ /* * This file is part of the LinuxBIOS project. - * + * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -15,11 +15,11 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - + */ + #define CacheSize DCACHE_RAM_SIZE #define CacheBase (0xd - CacheSize) - + /* leave some space for global variable to pass to RAM stage */ #define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE @@ -36,7 +36,7 @@ /*for normal part %ebx already contain cpu_init_detected from fallback call */ cache_as_ram_setup: - + movb$0xA0, %al outb%al, $0x80 @@ -107,7 +107,7 @@ /* Clear all MTRRs */ xorl%edx, %edx movl$fixed_mtrr_msr, %esi - + clear_fixed_var_mtrr: lodsl (%esi), %eax testl %eax, %eax @@ -245,7 +245,7 @@ movb$0xA1, %al outb%al, $0x80 - + /* enable cache */ movl%cr0, %eax andl$0x9fff, %eax @@ -259,7 +259,7 @@ bt $8, %eax /*BSC */ jnc CAR_FAM10_ap #endif - + movb$0xA2, %al outb%al, $0x80 @@ -280,7 +280,7 @@ /* set up the stack pointer */ movl$(CacheBase + CacheSize - GlobalVarSize), %eax movl%eax, %esp - + movb$0xA3, %al outb%al, $0x80 @@ -316,7 +316,7 @@ jc roll_cfg rolb%cl, %bl roll_cfg: - + /* calculate stack pointer */ movl$CacheSizeAPStack, %eax mull%ebx @@ -337,7 +337,7 @@ /* Restore the BIST result */ movl%ebp, %eax - + /* We need to set ebp ? No need */ movl%esp, %ebp pushl %ebx /* init detected */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3038 - trunk/LinuxBIOSv2/src/cpu/x86/car
Author: hailfinger Date: 2008-01-08 18:06:38 +0100 (Tue, 08 Jan 2008) New Revision: 3038 Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc Log: This patch is an attempt at introducing 4k CAR size granularity for the generic x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Add a copyright header to the code, the header is derived from the one found in the same piece of code in v3. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 10:28:06 UTC (rev 3037) +++ trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 17:06:38 UTC (rev 3038) @@ -1,3 +1,28 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <[EMAIL PROTECTED]> + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan + * (Written by Yinghai Lu <[EMAIL PROTECTED]> for Tyan) + * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH) + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* We will use 4K bytes only */ /* disable HyperThreading is done by eswar*/ /* other's is the same as AMD except remove amd specific msr */ @@ -106,39 +131,59 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 -/* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x0600, \reg +.elseif \segs == 2 + movl $0x0606, \reg +.elseif \segs == 3 + movl $0x06060600, \reg +.elseif \segs >= 4 + movl $0x06060606, \reg +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + simplemask_helper (((\carsize - \windowoffset) / 0x1000) - 4), %eax + simplemask_helper (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ movl$0x268, %ecx /* fix4k_c*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0x8000 wrmsr - movl$0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 -/* enable caching for 32K using fixed mtrr */ +/* enable caching for 0-32K using fixed mtrr */ movl$0x269, %ecx /* fix4k_c8000*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0 wrmsr -#endif -/* enable caching for 16K/8K/4K using fixed mtrr */ -movl$0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 -movl$0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 -movl$0x0606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 -movl$0x0600, %edx /* WB IO type */ -#endif - xorl%eax, %eax - wrmsr - - #else /* disable cache */ movl%cr0, %eax -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3038 - trunk/LinuxBIOSv2/src/cpu/x86/car
Author: hailfinger Date: 2008-01-08 18:06:38 +0100 (Tue, 08 Jan 2008) New Revision: 3038 Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc Log: This patch is an attempt at introducing 4k CAR size granularity for the generic x86 CAR code. For the old supported CAR sizes, the newly generated code is equivalent, so it should be a no-brainer. Add a copyright header to the code, the header is derived from the one found in the same piece of code in v3. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Marc Jones <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc === --- trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 10:28:06 UTC (rev 3037) +++ trunk/LinuxBIOSv2/src/cpu/x86/car/cache_as_ram.inc 2008-01-08 17:06:38 UTC (rev 3038) @@ -1,3 +1,28 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <[EMAIL PROTECTED]> + * Copyright (C) 2005 Eswar Nallusamy, LANL + * Copyright (C) 2005 Tyan + * (Written by Yinghai Lu <[EMAIL PROTECTED]> for Tyan) + * Copyright (C) 2007 coresystems GmbH + * (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH) + * Copyright (C) 2007 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + /* We will use 4K bytes only */ /* disable HyperThreading is done by eswar*/ /* other's is the same as AMD except remove amd specific msr */ @@ -106,39 +131,59 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x1 -/* enable caching for 64K using fixed mtrr */ +/* 0x06 is the WB IO type for a given 4k segment. + * segs is the number of 4k segments in the area of the particular + * register we want to use for CAR. + * reg is the register where the IO type should be stored. + */ +.macro extractmask segs, reg +.if \segs <= 0 + /* The xorl here is superfluous because at the point of first execution +* of this macro, %eax and %edx are cleared. Later invocations of this +* macro will have a monotonically increasing segs parameter. +*/ + xorl \reg, \reg +.elseif \segs == 1 + movl $0x0600, \reg +.elseif \segs == 2 + movl $0x0606, \reg +.elseif \segs == 3 + movl $0x06060600, \reg +.elseif \segs >= 4 + movl $0x06060606, \reg +.endif +.endm + +/* size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size + */ +.macro simplemask carsize, windowoffset + simplemask_helper (((\carsize - \windowoffset) / 0x1000) - 4), %eax + simplemask_helper (((\carsize - \windowoffset) / 0x1000)), %edx +.endm + +#if CacheSize > 0x1 +#error Invalid CAR size, must be at most 64k. +#endif +#if CacheSize < 0x1000 +#error Invalid CAR size, must be at least 4k. This is a processor limitation. +#endif +#if (CacheSize & (0x1000 - 1)) +#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. +#endif + +#if CacheSize > 0x8000 +/* enable caching for 32K-64K using fixed mtrr */ movl$0x268, %ecx /* fix4k_c*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0x8000 wrmsr - movl$0x269, %ecx - wrmsr #endif -#if CacheSize == 0x8000 -/* enable caching for 32K using fixed mtrr */ +/* enable caching for 0-32K using fixed mtrr */ movl$0x269, %ecx /* fix4k_c8000*/ -movl$0x06060606, %eax /* WB IO type */ - movl%eax, %edx + simplemask CacheSize, 0 wrmsr -#endif -/* enable caching for 16K/8K/4K using fixed mtrr */ -movl$0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 -movl$0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 -movl$0x0606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 -movl$0x0600, %edx /* WB IO type */ -#endif - xorl%eax, %eax - wrmsr - - #else /* disable cache */ movl%cr0, %eax -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3037 - trunk/LinuxBIOSv2/src/config
Author: oxygene Date: 2008-01-08 11:28:06 +0100 (Tue, 08 Jan 2008) New Revision: 3037 Modified: trunk/LinuxBIOSv2/src/config/Config.lb Log: Ubuntu's gcc doesn't write "install:" in german locales. Normalize used locale to "C" before parsing output. Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/config/Config.lb === --- trunk/LinuxBIOSv2/src/config/Config.lb 2008-01-07 13:48:51 UTC (rev 3036) +++ trunk/LinuxBIOSv2/src/config/Config.lb 2008-01-08 10:28:06 UTC (rev 3037) @@ -5,7 +5,7 @@ makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) -makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") +makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3037 - trunk/LinuxBIOSv2/src/config
Author: oxygene Date: 2008-01-08 11:28:06 +0100 (Tue, 08 Jan 2008) New Revision: 3037 Modified: trunk/LinuxBIOSv2/src/config/Config.lb Log: Ubuntu's gcc doesn't write "install:" in german locales. Normalize used locale to "C" before parsing output. Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/config/Config.lb === --- trunk/LinuxBIOSv2/src/config/Config.lb 2008-01-07 13:48:51 UTC (rev 3036) +++ trunk/LinuxBIOSv2/src/config/Config.lb 2008-01-08 10:28:06 UTC (rev 3037) @@ -5,7 +5,7 @@ makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name) -makedefine GCC_INC_DIR := $(shell $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") +makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp") makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS) makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin -Wall -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r549 - in LinuxBIOSv3: arch/x86 device include lib
Author: hailfinger
Date: 2008-01-07 17:34:34 +0100 (Mon, 07 Jan 2008)
New Revision: 549
Modified:
LinuxBIOSv3/arch/x86/archtables.c
LinuxBIOSv3/arch/x86/keyboard.c
LinuxBIOSv3/arch/x86/pci_ops_auto.c
LinuxBIOSv3/arch/x86/stage1.c
LinuxBIOSv3/device/device.c
LinuxBIOSv3/device/pci_device.c
LinuxBIOSv3/include/post_code.h
LinuxBIOSv3/lib/elfboot.c
LinuxBIOSv3/lib/stage2.c
Log:
The current parameter situation of post_code() is rather mixed between
numeric constants and #defines for such constants. Since grepping the
tree shouldn't be necessary to find a POST code and we already have
too many duplicated POST codes, gather almost all of them in a common
header file.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/archtables.c
===
--- LinuxBIOSv3/arch/x86/archtables.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/archtables.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -77,7 +77,7 @@
low_table_start = 0;
low_table_end = 16;
- post_code(0x9a);
+ post_code(POST_STAGE2_ARCH_WRITE_TABLES_ENTER);
/* This table must be betweeen 0xf & 0x10 */
// rom_table_end = write_pirq_routing_table(rom_table_end);
@@ -92,7 +92,7 @@
// rom_table_end = (rom_table_end+1023) & ~1023;
/* copy the smp block to address 0 */
- post_code(0x96);
+ post_code(POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
// new_low_table_end = write_smp_table(low_table_end);
Modified: LinuxBIOSv3/arch/x86/keyboard.c
===
--- LinuxBIOSv3/arch/x86/keyboard.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/keyboard.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -7,7 +7,7 @@
{
unsigned long timeout;
for(timeout = 100; timeout && (inb(0x64) & 0x02); timeout--) {
- post_code(0);
+ post_code(POST_KBD_EMPTY_INPUT_BUFFER);
}
return !!timeout;
}
@@ -16,7 +16,7 @@
{
unsigned long timeout;
for(timeout = 100; timeout && ((inb(0x64) & 0x01) == 0); timeout--)
{
- post_code(0);
+ post_code(POST_KBD_EMPTY_OUTPUT_BUFFER);
}
return !!timeout;
}
Modified: LinuxBIOSv3/arch/x86/pci_ops_auto.c
===
--- LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -88,5 +88,5 @@
{
printk(BIOS_INFO, "Finding PCI configuration type.\n");
dev->ops->ops_pci_bus = pci_check_direct();
- post_code(0x5f);
+ post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);
}
Modified: LinuxBIOSv3/arch/x86/stage1.c
===
--- LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/stage1.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -41,13 +41,13 @@
static void stop_ap(void)
{
// nothing yet
- post_code(0xf0);
+ post_code(POST_STAGE1_STOP_AP);
}
static void enable_rom(void)
{
// nothing here yet
- post_code(0xf2);
+ post_code(POST_STAGE1_ENABLE_ROM);
}
@@ -90,7 +90,7 @@
mem->map[0].type = LB_MEM_RAM;
- post_code(0x02);
+ post_code(POST_STAGE1_MAIN);
// before we do anything, we want to stop if we dont run
// on the bootstrap processor.
Modified: LinuxBIOSv3/device/device.c
===
--- LinuxBIOSv3/device/device.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/device/device.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -698,16 +698,16 @@
{
struct device *dev;
- post_code(0x31);
+ post_code(POST_STAGE2_PHASE1_ENTER);
printk(BIOS_DEBUG, "Phase 1: Very early setup...\n");
for (dev = all_devices; dev; dev = dev->next) {
if (dev->ops && dev->ops->phase1_set_device_operations) {
dev->ops->phase1_set_device_operations(dev);
}
}
- post_code(0x3e);
+ post_code(POST_STAGE2_PHASE1_DONE);
printk(BIOS_DEBUG, "Phase 1: done\n");
- post_code(0x3f);
+ post_code(POST_STAGE2_PHASE1_EXIT);
}
/**
@@ -721,7 +721,7 @@
{
struct device *dev;
- post_code(0x41);
+ post_code(POST_STAGE2_PHASE2_ENTER);
printk(BIOS_DEBUG, "Phase 2: Early setup...\n");
for (dev = all_devices; dev; dev = dev->next) {
printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname);
@@ -734,9 +734,9 @@
printk(BIOS_SPEW, "\n");
}
- post_code(0x4e);
+ post_code(POST_STAGE2_PHASE2_
[LinuxBIOS] r549 - in LinuxBIOSv3: arch/x86 device include lib
Author: hailfinger
Date: 2008-01-07 17:34:34 +0100 (Mon, 07 Jan 2008)
New Revision: 549
Modified:
LinuxBIOSv3/arch/x86/archtables.c
LinuxBIOSv3/arch/x86/keyboard.c
LinuxBIOSv3/arch/x86/pci_ops_auto.c
LinuxBIOSv3/arch/x86/stage1.c
LinuxBIOSv3/device/device.c
LinuxBIOSv3/device/pci_device.c
LinuxBIOSv3/include/post_code.h
LinuxBIOSv3/lib/elfboot.c
LinuxBIOSv3/lib/stage2.c
Log:
The current parameter situation of post_code() is rather mixed between
numeric constants and #defines for such constants. Since grepping the
tree shouldn't be necessary to find a POST code and we already have
too many duplicated POST codes, gather almost all of them in a common
header file.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/archtables.c
===
--- LinuxBIOSv3/arch/x86/archtables.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/archtables.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -77,7 +77,7 @@
low_table_start = 0;
low_table_end = 16;
- post_code(0x9a);
+ post_code(POST_STAGE2_ARCH_WRITE_TABLES_ENTER);
/* This table must be betweeen 0xf & 0x10 */
// rom_table_end = write_pirq_routing_table(rom_table_end);
@@ -92,7 +92,7 @@
// rom_table_end = (rom_table_end+1023) & ~1023;
/* copy the smp block to address 0 */
- post_code(0x96);
+ post_code(POST_STAGE2_ARCH_WRITE_TABLES_MIDDLE);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
// new_low_table_end = write_smp_table(low_table_end);
Modified: LinuxBIOSv3/arch/x86/keyboard.c
===
--- LinuxBIOSv3/arch/x86/keyboard.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/keyboard.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -7,7 +7,7 @@
{
unsigned long timeout;
for(timeout = 100; timeout && (inb(0x64) & 0x02); timeout--) {
- post_code(0);
+ post_code(POST_KBD_EMPTY_INPUT_BUFFER);
}
return !!timeout;
}
@@ -16,7 +16,7 @@
{
unsigned long timeout;
for(timeout = 100; timeout && ((inb(0x64) & 0x01) == 0); timeout--)
{
- post_code(0);
+ post_code(POST_KBD_EMPTY_OUTPUT_BUFFER);
}
return !!timeout;
}
Modified: LinuxBIOSv3/arch/x86/pci_ops_auto.c
===
--- LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/pci_ops_auto.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -88,5 +88,5 @@
{
printk(BIOS_INFO, "Finding PCI configuration type.\n");
dev->ops->ops_pci_bus = pci_check_direct();
- post_code(0x5f);
+ post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);
}
Modified: LinuxBIOSv3/arch/x86/stage1.c
===
--- LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/arch/x86/stage1.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -41,13 +41,13 @@
static void stop_ap(void)
{
// nothing yet
- post_code(0xf0);
+ post_code(POST_STAGE1_STOP_AP);
}
static void enable_rom(void)
{
// nothing here yet
- post_code(0xf2);
+ post_code(POST_STAGE1_ENABLE_ROM);
}
@@ -90,7 +90,7 @@
mem->map[0].type = LB_MEM_RAM;
- post_code(0x02);
+ post_code(POST_STAGE1_MAIN);
// before we do anything, we want to stop if we dont run
// on the bootstrap processor.
Modified: LinuxBIOSv3/device/device.c
===
--- LinuxBIOSv3/device/device.c 2008-01-05 01:35:57 UTC (rev 548)
+++ LinuxBIOSv3/device/device.c 2008-01-07 16:34:34 UTC (rev 549)
@@ -698,16 +698,16 @@
{
struct device *dev;
- post_code(0x31);
+ post_code(POST_STAGE2_PHASE1_ENTER);
printk(BIOS_DEBUG, "Phase 1: Very early setup...\n");
for (dev = all_devices; dev; dev = dev->next) {
if (dev->ops && dev->ops->phase1_set_device_operations) {
dev->ops->phase1_set_device_operations(dev);
}
}
- post_code(0x3e);
+ post_code(POST_STAGE2_PHASE1_DONE);
printk(BIOS_DEBUG, "Phase 1: done\n");
- post_code(0x3f);
+ post_code(POST_STAGE2_PHASE1_EXIT);
}
/**
@@ -721,7 +721,7 @@
{
struct device *dev;
- post_code(0x41);
+ post_code(POST_STAGE2_PHASE2_ENTER);
printk(BIOS_DEBUG, "Phase 2: Early setup...\n");
for (dev = all_devices; dev; dev = dev->next) {
printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname);
@@ -734,9 +734,9 @@
printk(BIOS_SPEW, "\n");
}
- post_code(0x4e);
+ post_code(POST_STAGE2_PHASE2_
[LinuxBIOS] r3036 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-07 14:48:51 +0100 (Mon, 07 Jan 2008)
New Revision: 3036
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add support for the SST25VF040B 4 Mbit SPI flash chip.
Straight from the data sheet, not tested.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-07 11:13:16 UTC (rev 3035)
+++ trunk/util/flashrom/flashchips.c2008-01-07 13:48:51 UTC (rev 3036)
@@ -52,6 +52,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"SST25VF040B", SST_ID, SST_25VF040B, 512,256,
+ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,
--
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[LinuxBIOS] r3036 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-07 14:48:51 +0100 (Mon, 07 Jan 2008)
New Revision: 3036
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add support for the SST25VF040B 4 Mbit SPI flash chip.
Straight from the data sheet, not tested.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-07 11:13:16 UTC (rev 3035)
+++ trunk/util/flashrom/flashchips.c2008-01-07 13:48:51 UTC (rev 3036)
@@ -52,6 +52,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"SST25VF040B", SST_ID, SST_25VF040B, 512,256,
+ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,
--
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[LinuxBIOS] r3035 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Author: duwe
Date: 2008-01-07 12:13:16 +0100 (Mon, 07 Jan 2008)
New Revision: 3035
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
Log:
Improve readability and remove redundancy by wrapping
similar smp_write_intsrc calls in preprocessor macros.
Also add some comments about the actual devices the INTs
belong to.
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-06
01:10:54 UTC (rev 3034)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-07
11:13:16 UTC (rev 3035)
@@ -98,46 +98,60 @@
}
}
-/*I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID PIN#
-*/ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x1, apicid_mcp55, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, apicid_mcp55, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x3, apicid_mcp55, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x4, apicid_mcp55, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x6, apicid_mcp55, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x7, apicid_mcp55, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x8, apicid_mcp55, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xc, apicid_mcp55, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xd, apicid_mcp55, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xe, apicid_mcp55, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xf, apicid_mcp55, 0xf);
+ /*I/O Ints: Type TriggerPolarity
Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+ * or its remainings.
+ */
+#define ISA_INT(intr, pin)\
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), apicid_mcp55, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+ ISA_INT(1,1);
+ ISA_INT(0,2);
+ ISA_INT(3,3);
+ ISA_INT(4,4);
+ ISA_INT(6,6);
+ ISA_INT(7,7);
+ ISA_INT(8,8);
+ ISA_INT(12,12);
+ ISA_INT(13,13);
+ ISA_INT(14,14);
+ ISA_INT(15,15);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+/* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, fn, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
+bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+PCI_INT(0,sbdn+1,1, 10); /* SMBus */
+PCI_INT(0,sbdn+2,0, 22); /* USB */
+PCI_INT(0,sbdn+2,1, 23); /* USB */
+PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
+PCI_INT(0,sbdn+5,0, 20); /* SATA */
+PCI_INT(0,sbdn+5,1, 23); /* SATA */
+PCI_INT(0,sbdn+5,2, 21); /* SATA */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
-
+ /* The PCIe slots, each on its own bus */
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
-
[LinuxBIOS] r3035 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Author: duwe
Date: 2008-01-07 12:13:16 +0100 (Mon, 07 Jan 2008)
New Revision: 3035
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
Log:
Improve readability and remove redundancy by wrapping
similar smp_write_intsrc calls in preprocessor macros.
Also add some comments about the actual devices the INTs
belong to.
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-06
01:10:54 UTC (rev 3034)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2008-01-07
11:13:16 UTC (rev 3035)
@@ -98,46 +98,60 @@
}
}
-/*I/O Ints:TypePolarityTrigger Bus ID IRQAPIC ID PIN#
-*/ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x1, apicid_mcp55, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, apicid_mcp55, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x3, apicid_mcp55, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x4, apicid_mcp55, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x6, apicid_mcp55, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x7, apicid_mcp55, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x8, apicid_mcp55, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xc, apicid_mcp55, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xd, apicid_mcp55, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xe, apicid_mcp55, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0xf, apicid_mcp55, 0xf);
+ /*I/O Ints: Type TriggerPolarity
Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa);
+/* ISA ints are edge-triggered, and usually originate from the ISA bus,
+ * or its remainings.
+ */
+#define ISA_INT(intr, pin)\
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, (intr), apicid_mcp55, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22
+ ISA_INT(1,1);
+ ISA_INT(0,2);
+ ISA_INT(3,3);
+ ISA_INT(4,4);
+ ISA_INT(6,6);
+ ISA_INT(7,7);
+ ISA_INT(8,8);
+ ISA_INT(12,12);
+ ISA_INT(13,13);
+ ISA_INT(14,14);
+ ISA_INT(15,15);
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23
+/* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, fn, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
+bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23
+PCI_INT(0,sbdn+1,1, 10); /* SMBus */
+PCI_INT(0,sbdn+2,0, 22); /* USB */
+PCI_INT(0,sbdn+2,1, 23); /* USB */
+PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
+PCI_INT(0,sbdn+5,0, 20); /* SATA */
+PCI_INT(0,sbdn+5,1, 23); /* SATA */
+PCI_INT(0,sbdn+5,2, 21); /* SATA */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21
+PCI_INT(0,sbdn+8,0, 22); /* GBit Ether */
-smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22
-
+ /* The PCIe slots, each on its own bus */
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
-
[LinuxBIOS] r3034 - in trunk/LinuxBIOSv2/src: config devices
Author: duwe
Date: 2008-01-06 02:10:54 +0100 (Sun, 06 Jan 2008)
New Revision: 3034
Modified:
trunk/LinuxBIOSv2/src/config/Options.lb
trunk/LinuxBIOSv2/src/devices/Config.lb
trunk/LinuxBIOSv2/src/devices/pci_device.c
Log:
Since a VGA console and the need to run any option ROMs are
rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.
This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.
Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Luc Verhaegen <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/config/Options.lb
===
--- trunk/LinuxBIOSv2/src/config/Options.lb 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/config/Options.lb 2008-01-06 01:10:54 UTC (rev
3034)
@@ -415,7 +415,7 @@
define CONFIG_CONSOLE_VGA
default 0
export always
- comment "Log messages to VGA"
+ comment "Log messages to any VGA-compatible device (may require
*_ROM_RUN to bring up)"
end
define CONFIG_CONSOLE_VGA_MULTI
default 0
@@ -1027,10 +1027,16 @@
comment "CPU hardware address lines num, for AMD K8 could be 40, and
AMD family 10 could be 48"
end
+define CONFIG_VGA_ROM_RUN
+ default 0
+ export always
+ comment "Init x86 ROMs on VGA-class PCI devices"
+end
+
define CONFIG_PCI_ROM_RUN
default 0
export always
- comment "Init PCI device option rom"
+ comment "Init x86 ROMs on all PCI devices"
end
define CONFIG_PCI_64BIT_PREF_MEM
Modified: trunk/LinuxBIOSv2/src/devices/Config.lb
===
--- trunk/LinuxBIOSv2/src/devices/Config.lb 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/devices/Config.lb 2008-01-06 01:10:54 UTC (rev
3034)
@@ -1,4 +1,5 @@
uses CONFIG_PCI_ROM_RUN
+uses CONFIG_VGA_ROM_RUN
object device.o
object root_device.o
object device_util.o
@@ -15,4 +16,9 @@
if CONFIG_PCI_ROM_RUN
object pci_rom.o
dir emulator
+else
+if CONFIG_VGA_ROM_RUN
+ object pci_rom.o
+ dir emulator
end
+end
Modified: trunk/LinuxBIOSv2/src/devices/pci_device.c
===
--- trunk/LinuxBIOSv2/src/devices/pci_device.c 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/devices/pci_device.c 2008-01-06 01:10:54 UTC (rev
3034)
@@ -643,16 +643,14 @@
((device & 0x) << 16) | (vendor & 0x));
}
+/** default handler: only runs the relevant pci bios. */
void pci_dev_init(struct device *dev)
{
-#if CONFIG_CONSOLE_VGA == 1
- extern int vga_inited;
-#endif
-#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_CONSOLE_VGA == 1
+#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
struct rom_header *rom, *ram;
#if CONFIG_PCI_ROM_RUN != 1
- /* We want to execute VGA option ROMs when CONFIG_CONSOLE_VGA
+ /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
* is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
* all other option ROM types.
*/
@@ -671,14 +669,13 @@
run_bios(dev, ram);
#if CONFIG_CONSOLE_VGA == 1
- /* vga_inited is a trigger of the VGA console code.
-*
-* Only set it if we enabled VGA console, and if we
-* just initialized a VGA card.
-*/
- vga_inited|=dev->class==PCI_CLASS_DISPLAY_VGA;
-#endif
-#endif
+ /* vga_inited is a trigger of the VGA console code. */
+ if (dev->class == PCI_CLASS_DISPLAY_VGA) {
+ extern int vga_inited;
+ vga_inited = 1;
+ }
+#endif /* CONFIG_CONSOLE_VGA */
+#endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
}
/** Default device operation for PCI devices */
--
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[LinuxBIOS] r3034 - in trunk/LinuxBIOSv2/src: config devices
Author: duwe
Date: 2008-01-06 02:10:54 +0100 (Sun, 06 Jan 2008)
New Revision: 3034
Modified:
trunk/LinuxBIOSv2/src/config/Options.lb
trunk/LinuxBIOSv2/src/devices/Config.lb
trunk/LinuxBIOSv2/src/devices/pci_device.c
Log:
Since a VGA console and the need to run any option ROMs are
rather independent, lift the implicit (broken) assumption that
CONSOLE_VGA would also run the ROMs, and transfer it to a new
config option VGA_ROM_RUN.
This change is minimally intrusive, because all board configs
that previously assumed CONSOLE_VGA would also run the ROMs
didn't compile, they had to also specify PCI_ROM_RUN.
Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen
(separate ROM_RUN from VGA console).
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Luc Verhaegen <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/config/Options.lb
===
--- trunk/LinuxBIOSv2/src/config/Options.lb 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/config/Options.lb 2008-01-06 01:10:54 UTC (rev
3034)
@@ -415,7 +415,7 @@
define CONFIG_CONSOLE_VGA
default 0
export always
- comment "Log messages to VGA"
+ comment "Log messages to any VGA-compatible device (may require
*_ROM_RUN to bring up)"
end
define CONFIG_CONSOLE_VGA_MULTI
default 0
@@ -1027,10 +1027,16 @@
comment "CPU hardware address lines num, for AMD K8 could be 40, and
AMD family 10 could be 48"
end
+define CONFIG_VGA_ROM_RUN
+ default 0
+ export always
+ comment "Init x86 ROMs on VGA-class PCI devices"
+end
+
define CONFIG_PCI_ROM_RUN
default 0
export always
- comment "Init PCI device option rom"
+ comment "Init x86 ROMs on all PCI devices"
end
define CONFIG_PCI_64BIT_PREF_MEM
Modified: trunk/LinuxBIOSv2/src/devices/Config.lb
===
--- trunk/LinuxBIOSv2/src/devices/Config.lb 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/devices/Config.lb 2008-01-06 01:10:54 UTC (rev
3034)
@@ -1,4 +1,5 @@
uses CONFIG_PCI_ROM_RUN
+uses CONFIG_VGA_ROM_RUN
object device.o
object root_device.o
object device_util.o
@@ -15,4 +16,9 @@
if CONFIG_PCI_ROM_RUN
object pci_rom.o
dir emulator
+else
+if CONFIG_VGA_ROM_RUN
+ object pci_rom.o
+ dir emulator
end
+end
Modified: trunk/LinuxBIOSv2/src/devices/pci_device.c
===
--- trunk/LinuxBIOSv2/src/devices/pci_device.c 2008-01-04 17:22:44 UTC (rev
3033)
+++ trunk/LinuxBIOSv2/src/devices/pci_device.c 2008-01-06 01:10:54 UTC (rev
3034)
@@ -643,16 +643,14 @@
((device & 0x) << 16) | (vendor & 0x));
}
+/** default handler: only runs the relevant pci bios. */
void pci_dev_init(struct device *dev)
{
-#if CONFIG_CONSOLE_VGA == 1
- extern int vga_inited;
-#endif
-#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_CONSOLE_VGA == 1
+#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
struct rom_header *rom, *ram;
#if CONFIG_PCI_ROM_RUN != 1
- /* We want to execute VGA option ROMs when CONFIG_CONSOLE_VGA
+ /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
* is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
* all other option ROM types.
*/
@@ -671,14 +669,13 @@
run_bios(dev, ram);
#if CONFIG_CONSOLE_VGA == 1
- /* vga_inited is a trigger of the VGA console code.
-*
-* Only set it if we enabled VGA console, and if we
-* just initialized a VGA card.
-*/
- vga_inited|=dev->class==PCI_CLASS_DISPLAY_VGA;
-#endif
-#endif
+ /* vga_inited is a trigger of the VGA console code. */
+ if (dev->class == PCI_CLASS_DISPLAY_VGA) {
+ extern int vga_inited;
+ vga_inited = 1;
+ }
+#endif /* CONFIG_CONSOLE_VGA */
+#endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
}
/** Default device operation for PCI devices */
--
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[LinuxBIOS] r548 - LinuxBIOSv3/arch/x86
Author: hailfinger
Date: 2008-01-05 02:35:57 +0100 (Sat, 05 Jan 2008)
New Revision: 548
Modified:
LinuxBIOSv3/arch/x86/stage1.c
Log:
Fix a simple error in stage1.c (missing else).
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/stage1.c
===
--- LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:33:28 UTC (rev 547)
+++ LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:35:57 UTC (rev 548)
@@ -176,9 +176,9 @@
entry = load_file_segments(&archive, "normal/payload");
if (entry != (void*)-1)
run_address(entry);
+ else
+ die("FATAL: No usable payload found.\n");
- die("FATAL: No usable payload found.\n");
-
die ("FATAL: Last stage returned to LinuxBIOS.\n");
}
--
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[LinuxBIOS] r548 - LinuxBIOSv3/arch/x86
Author: hailfinger
Date: 2008-01-05 02:35:57 +0100 (Sat, 05 Jan 2008)
New Revision: 548
Modified:
LinuxBIOSv3/arch/x86/stage1.c
Log:
Fix a simple error in stage1.c (missing else).
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/stage1.c
===
--- LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:33:28 UTC (rev 547)
+++ LinuxBIOSv3/arch/x86/stage1.c 2008-01-05 01:35:57 UTC (rev 548)
@@ -176,9 +176,9 @@
entry = load_file_segments(&archive, "normal/payload");
if (entry != (void*)-1)
run_address(entry);
+ else
+ die("FATAL: No usable payload found.\n");
- die("FATAL: No usable payload found.\n");
-
die ("FATAL: Last stage returned to LinuxBIOS.\n");
}
--
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[LinuxBIOS] r547 - LinuxBIOSv3/include/arch/x86
Author: hailfinger Date: 2008-01-05 02:33:28 +0100 (Sat, 05 Jan 2008) New Revision: 547 Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: include/arch/x86/amd_geodelx.h had duplicated #defines by accident in r546. Remove them again. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h === --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev 546) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-05 01:33:28 UTC (rev 547) @@ -572,11 +572,6 @@ */ #define LX_STACK_BASE DCACHE_RAM_BASE #define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) #define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ #define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r547 - LinuxBIOSv3/include/arch/x86
Author: hailfinger Date: 2008-01-05 02:33:28 +0100 (Sat, 05 Jan 2008) New Revision: 547 Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: include/arch/x86/amd_geodelx.h had duplicated #defines by accident in r546. Remove them again. Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h === --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev 546) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-05 01:33:28 UTC (rev 547) @@ -572,11 +572,6 @@ */ #define LX_STACK_BASE DCACHE_RAM_BASE #define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) #define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ #define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r546 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Author: hailfinger
Date: 2008-01-05 00:19:49 +0100 (Sat, 05 Jan 2008)
New Revision: 546
Modified:
LinuxBIOSv3/arch/x86/geodelx/stage1.c
LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
These changes implement a fixed Geode LX Cache As Ram that allows a
return from disable_car.
- Move the cache as ram memory to 0x8 instead of 0xc8000, as the C
range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
the wbinvd.
With these changes, I get a payload loaded.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:19:49 UTC (rev
546)
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
static const struct msrinit msr_table[] = {
/* Setup access to cache under 1MB. */
@@ -59,5 +60,12 @@
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
- __asm__("wbinvd\n");
+ /* OK, here is the theory: we should be able to copy
+* the data back over itself, and the wbinvd should then
+* flush to memory. Let's see.
+*/
+ __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S"
(DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+ __asm__ __volatile__ ("wbinvd\n");
+ banner(BIOS_DEBUG, "Disable_car: done wbinvd");
+ banner(BIOS_DEBUG, "disable_car: done");
}
Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev
546)
@@ -566,12 +566,17 @@
/* */
#define DCACHE_RAM_SIZE 0x08000
-#define DCACHE_RAM_BASE 0xc8000
+#define DCACHE_RAM_BASE 0x8
/* This is where the DCache will be mapped and be used as stack. It would be
* cool if it was the same base as LinuxBIOS normal stack.
*/
#define LX_STACK_BASE DCACHE_RAM_BASE
#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
+/* This is where the DCache will be mapped and be used as stack. It would be
+ * cool if it was the same base as LinuxBIOS normal stack.
+ */
+#define LX_STACK_BASE DCACHE_RAM_BASE
+#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */
#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */
--
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[LinuxBIOS] r546 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Author: hailfinger
Date: 2008-01-05 00:19:49 +0100 (Sat, 05 Jan 2008)
New Revision: 546
Modified:
LinuxBIOSv3/arch/x86/geodelx/stage1.c
LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
These changes implement a fixed Geode LX Cache As Ram that allows a
return from disable_car.
- Move the cache as ram memory to 0x8 instead of 0xc8000, as the C
range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
the wbinvd.
With these changes, I get a payload loaded.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/arch/x86/geodelx/stage1.c
===
--- LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/arch/x86/geodelx/stage1.c 2008-01-04 23:19:49 UTC (rev
546)
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
static const struct msrinit msr_table[] = {
/* Setup access to cache under 1MB. */
@@ -59,5 +60,12 @@
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
- __asm__("wbinvd\n");
+ /* OK, here is the theory: we should be able to copy
+* the data back over itself, and the wbinvd should then
+* flush to memory. Let's see.
+*/
+ __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S"
(DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
+ __asm__ __volatile__ ("wbinvd\n");
+ banner(BIOS_DEBUG, "Disable_car: done wbinvd");
+ banner(BIOS_DEBUG, "disable_car: done");
}
Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:14:10 UTC (rev
545)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 23:19:49 UTC (rev
546)
@@ -566,12 +566,17 @@
/* */
#define DCACHE_RAM_SIZE 0x08000
-#define DCACHE_RAM_BASE 0xc8000
+#define DCACHE_RAM_BASE 0x8
/* This is where the DCache will be mapped and be used as stack. It would be
* cool if it was the same base as LinuxBIOS normal stack.
*/
#define LX_STACK_BASE DCACHE_RAM_BASE
#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
+/* This is where the DCache will be mapped and be used as stack. It would be
+ * cool if it was the same base as LinuxBIOS normal stack.
+ */
+#define LX_STACK_BASE DCACHE_RAM_BASE
+#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4)
#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */
#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */
--
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[LinuxBIOS] r545 - LinuxBIOSv3/lib
Author: hailfinger
Date: 2008-01-05 00:14:10 +0100 (Sat, 05 Jan 2008)
New Revision: 545
Modified:
LinuxBIOSv3/lib/console.c
Log:
Change die() to make it JTAG friendly.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544)
+++ LinuxBIOSv3/lib/console.c 2008-01-04 23:14:10 UTC (rev 545)
@@ -82,9 +82,31 @@
printk(BIOS_INFO, console_test);
}
+/**
+ * Halt and loop due to a fatal error.
+ * There have been several iterations of this function.
+ * The first simply did a hlt(). Doing a hlt() can make jtag debugging
+ * very difficult as one can not break into a hlt instruction on some CPUs.
+ * Second was to do a console_tx_byte of a NULL character.
+ * A number of concerns were raised about doing this idea.
+ * Third idea was to do an inb from port 0x80, the POST port. That design
+ * makes us very CPU-specific.
+ * The fourth idea was just POSTING the same
+ * code over and over. That would erase the most recent POST code,
+ * hindering diagnosis.
+ *
+ * For now, for lack of a good alternative,
+ * we will continue to call console_tx_byte. We call with a NULL since
+ * it will clear any FIFOs in the path and won't clutter up the output,
+ * since NULL doesn't print a visible character on most terminal
+ * emulators.
+ *
+ * @param str A string to print for the error
+ *
+ */
void die(const char *str)
{
printk(BIOS_EMERG, str);
while (1)
- hlt();
+ console_tx_byte(0, (void *)0);
}
--
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[LinuxBIOS] r545 - LinuxBIOSv3/lib
Author: hailfinger
Date: 2008-01-05 00:14:10 +0100 (Sat, 05 Jan 2008)
New Revision: 545
Modified:
LinuxBIOSv3/lib/console.c
Log:
Change die() to make it JTAG friendly.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544)
+++ LinuxBIOSv3/lib/console.c 2008-01-04 23:14:10 UTC (rev 545)
@@ -82,9 +82,31 @@
printk(BIOS_INFO, console_test);
}
+/**
+ * Halt and loop due to a fatal error.
+ * There have been several iterations of this function.
+ * The first simply did a hlt(). Doing a hlt() can make jtag debugging
+ * very difficult as one can not break into a hlt instruction on some CPUs.
+ * Second was to do a console_tx_byte of a NULL character.
+ * A number of concerns were raised about doing this idea.
+ * Third idea was to do an inb from port 0x80, the POST port. That design
+ * makes us very CPU-specific.
+ * The fourth idea was just POSTING the same
+ * code over and over. That would erase the most recent POST code,
+ * hindering diagnosis.
+ *
+ * For now, for lack of a good alternative,
+ * we will continue to call console_tx_byte. We call with a NULL since
+ * it will clear any FIFOs in the path and won't clutter up the output,
+ * since NULL doesn't print a visible character on most terminal
+ * emulators.
+ *
+ * @param str A string to print for the error
+ *
+ */
void die(const char *str)
{
printk(BIOS_EMERG, str);
while (1)
- hlt();
+ console_tx_byte(0, (void *)0);
}
--
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[LinuxBIOS] r544 - in LinuxBIOSv3: include lib northbridge/amd/geodelx
Author: hailfinger
Date: 2008-01-05 00:12:22 +0100 (Sat, 05 Jan 2008)
New Revision: 544
Modified:
LinuxBIOSv3/include/console.h
LinuxBIOSv3/lib/console.c
LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
Log:
Add a banner function to lib/console.c that is SHARED so all code can
use it.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/include/console.h
===
--- LinuxBIOSv3/include/console.h 2008-01-04 12:53:09 UTC (rev 543)
+++ LinuxBIOSv3/include/console.h 2008-01-04 23:12:22 UTC (rev 544)
@@ -48,5 +48,6 @@
SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))),
int msg_level, const char *fmt, ...);
+SHARED(banner, void, int msg_level, const char *msg);
#endif /* CONSOLE_H */
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-04 12:53:09 UTC (rev 543)
+++ LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544)
@@ -46,6 +46,29 @@
return i;
}
+/**
+ * Print a nice banner so we know what step we died on.
+ *
+ * @param level The printk level (e.g. BIOS_EMERG)
+ * @param s String to put in the middle of the banner
+ */
+
+void banner(int level, const char *s)
+{
+ int i;
+ /* 10 = signs and a space. */
+ printk(level, "== ");
+ for(i = 11; *s; i++, s++)
+ printk(level, "%c", *s);
+ /* trailing space */
+ printk(level, " ");
+ i++;
+ /* fill it up to 80 columns */
+ for(; i < 80; i++)
+ printk(level, "=");
+ printk(level, "\n");
+}
+
void console_init(void)
{
static const char console_test[] =
Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 12:53:09 UTC
(rev 543)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 23:12:22 UTC
(rev 544)
@@ -36,19 +36,6 @@
u8 spd_read_byte(u16 device, u8 address);
/**
- * Print a nice banner so we know what step we died on.
- *
- * @param s String to put in the middle of the banner
- */
-
-void banner(char *s)
-{
- printk(BIOS_DEBUG, "===");
- printk(BIOS_DEBUG, s);
- printk(BIOS_DEBUG, "==\n");
-}
-
-/**
* Halt and Catch Fire. Print an error, then loop, sending NULLs on serial
port,
* to ensure the message is visible.
*
@@ -83,14 +70,14 @@
dimm_setting = 0;
- banner("Check present");
+ banner(BIOS_DEBUG, "Check present");
/* Check that we have a DIMM. */
if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF)
return;
/* Field: Module Banks per DIMM */
/* EEPROM byte usage: (5) Number of DIMM Banks */
- banner("MODBANKS");
+ banner(BIOS_DEBUG, "MODBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
printk(BIOS_EMERG, "Number of module banks not compatible\n");
@@ -101,7 +88,7 @@
/* Field: Banks per SDRAM device */
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
- banner("FIELDBANKS");
+ banner(BIOS_DEBUG, "FIELDBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
printk(BIOS_EMERG, "Number of device banks not compatible\n");
@@ -117,7 +104,7 @@
*; (31) Module Bank Density
*; Size = Module Density * Module Banks
*/
- banner("SPDNUMROWS");
+ banner(BIOS_DEBUG, "SPDNUMROWS");
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
@@ -127,7 +114,7 @@
}
/* Size = Module Density * Module Banks */
- banner("SPDBANKDENSITY");
+ banner(BIOS_DEBUG, "SPDBANKDENSITY");
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
/* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc
@@ -143,9 +130,9 @@
/* Module Density * Module Banks */
/* Shift to multiply by the number of DIMM banks. */
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;
- banner("BEFORT CTZ");
+ banner(BIOS_DEBUG, "BEFORT CTZ");
dimm_size = __builtin_ctz(dimm_size);
- banner("TEST DIMM SIZE>8");
+ banner(BIOS_DEBUG, "TEST DIMM SIZE>8");
if (dimm_size > 8) {/* 8 is 1 GB only support 1 GB per DIMM */
printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
@@ -177,9 +164,9 @
[LinuxBIOS] r544 - in LinuxBIOSv3: include lib northbridge/amd/geodelx
Author: hailfinger
Date: 2008-01-05 00:12:22 +0100 (Sat, 05 Jan 2008)
New Revision: 544
Modified:
LinuxBIOSv3/include/console.h
LinuxBIOSv3/lib/console.c
LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
Log:
Add a banner function to lib/console.c that is SHARED so all code can
use it.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: LinuxBIOSv3/include/console.h
===
--- LinuxBIOSv3/include/console.h 2008-01-04 12:53:09 UTC (rev 543)
+++ LinuxBIOSv3/include/console.h 2008-01-04 23:12:22 UTC (rev 544)
@@ -48,5 +48,6 @@
SHARED_WITH_ATTRIBUTES(printk, int, __attribute__((format (printf, 2, 3))),
int msg_level, const char *fmt, ...);
+SHARED(banner, void, int msg_level, const char *msg);
#endif /* CONSOLE_H */
Modified: LinuxBIOSv3/lib/console.c
===
--- LinuxBIOSv3/lib/console.c 2008-01-04 12:53:09 UTC (rev 543)
+++ LinuxBIOSv3/lib/console.c 2008-01-04 23:12:22 UTC (rev 544)
@@ -46,6 +46,29 @@
return i;
}
+/**
+ * Print a nice banner so we know what step we died on.
+ *
+ * @param level The printk level (e.g. BIOS_EMERG)
+ * @param s String to put in the middle of the banner
+ */
+
+void banner(int level, const char *s)
+{
+ int i;
+ /* 10 = signs and a space. */
+ printk(level, "== ");
+ for(i = 11; *s; i++, s++)
+ printk(level, "%c", *s);
+ /* trailing space */
+ printk(level, " ");
+ i++;
+ /* fill it up to 80 columns */
+ for(; i < 80; i++)
+ printk(level, "=");
+ printk(level, "\n");
+}
+
void console_init(void)
{
static const char console_test[] =
Modified: LinuxBIOSv3/northbridge/amd/geodelx/raminit.c
===
--- LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 12:53:09 UTC
(rev 543)
+++ LinuxBIOSv3/northbridge/amd/geodelx/raminit.c 2008-01-04 23:12:22 UTC
(rev 544)
@@ -36,19 +36,6 @@
u8 spd_read_byte(u16 device, u8 address);
/**
- * Print a nice banner so we know what step we died on.
- *
- * @param s String to put in the middle of the banner
- */
-
-void banner(char *s)
-{
- printk(BIOS_DEBUG, "===");
- printk(BIOS_DEBUG, s);
- printk(BIOS_DEBUG, "==\n");
-}
-
-/**
* Halt and Catch Fire. Print an error, then loop, sending NULLs on serial
port,
* to ensure the message is visible.
*
@@ -83,14 +70,14 @@
dimm_setting = 0;
- banner("Check present");
+ banner(BIOS_DEBUG, "Check present");
/* Check that we have a DIMM. */
if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF)
return;
/* Field: Module Banks per DIMM */
/* EEPROM byte usage: (5) Number of DIMM Banks */
- banner("MODBANKS");
+ banner(BIOS_DEBUG, "MODBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) && (spd_byte > MAX_MOD_BANKS)) {
printk(BIOS_EMERG, "Number of module banks not compatible\n");
@@ -101,7 +88,7 @@
/* Field: Banks per SDRAM device */
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
- banner("FIELDBANKS");
+ banner(BIOS_DEBUG, "FIELDBANKS");
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) && (spd_byte > MAX_DEV_BANKS)) {
printk(BIOS_EMERG, "Number of device banks not compatible\n");
@@ -117,7 +104,7 @@
*; (31) Module Bank Density
*; Size = Module Density * Module Banks
*/
- banner("SPDNUMROWS");
+ banner(BIOS_DEBUG, "SPDNUMROWS");
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
@@ -127,7 +114,7 @@
}
/* Size = Module Density * Module Banks */
- banner("SPDBANKDENSITY");
+ banner(BIOS_DEBUG, "SPDBANKDENSITY");
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
/* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc
@@ -143,9 +130,9 @@
/* Module Density * Module Banks */
/* Shift to multiply by the number of DIMM banks. */
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;
- banner("BEFORT CTZ");
+ banner(BIOS_DEBUG, "BEFORT CTZ");
dimm_size = __builtin_ctz(dimm_size);
- banner("TEST DIMM SIZE>8");
+ banner(BIOS_DEBUG, "TEST DIMM SIZE>8");
if (dimm_size > 8) {/* 8 is 1 GB only support 1 GB per DIMM */
printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
@@ -177,9 +164,9 @
[LinuxBIOS] r3033 - trunk/util/flashrom
Author: rminnich
Date: 2008-01-04 18:22:44 +0100 (Fri, 04 Jan 2008)
New Revision: 3033
Modified:
trunk/util/flashrom/board_enable.c
Log:
Add board enable for the gigabyte ga_2761gxdk board
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c 2008-01-04 16:22:09 UTC (rev 3032)
+++ trunk/util/flashrom/board_enable.c 2008-01-04 17:22:44 UTC (rev 3033)
@@ -381,6 +381,8 @@
"gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash},
{0x10de, 0x03e0, 0x, 0x, 0x, 0x, 0x, 0x,
"gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash},
+ {0x1039, 0x0761, 0x, 0x, 0x, 0x, 0x, 0x,
+"gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK",
it87xx_probe_spi_flash},
{0x1022, 0x7468, 0x, 0x, 0x, 0x, 0x, 0x,
"iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
{0x10de, 0x005e, 0x, 0x, 0x, 0x, 0x, 0x,
--
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[LinuxBIOS] r3033 - trunk/util/flashrom
Author: rminnich
Date: 2008-01-04 18:22:44 +0100 (Fri, 04 Jan 2008)
New Revision: 3033
Modified:
trunk/util/flashrom/board_enable.c
Log:
Add board enable for the gigabyte ga_2761gxdk board
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c 2008-01-04 16:22:09 UTC (rev 3032)
+++ trunk/util/flashrom/board_enable.c 2008-01-04 17:22:44 UTC (rev 3033)
@@ -381,6 +381,8 @@
"gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash},
{0x10de, 0x03e0, 0x, 0x, 0x, 0x, 0x, 0x,
"gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash},
+ {0x1039, 0x0761, 0x, 0x, 0x, 0x, 0x, 0x,
+"gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK",
it87xx_probe_spi_flash},
{0x1022, 0x7468, 0x, 0x, 0x, 0x, 0x, 0x,
"iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
{0x10de, 0x005e, 0x, 0x, 0x, 0x, 0x, 0x,
--
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[LinuxBIOS] r3032 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-04 17:22:09 +0100 (Fri, 04 Jan 2008)
New Revision: 3032
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/spi.c
Log:
Print at least the vendor for SPI flash chips if the exact chip ID is
unknown.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/flash.h 2008-01-04 16:22:09 UTC (rev 3032)
@@ -59,10 +59,13 @@
* entry of each section should be the manufacturer ID, followed by the
* list of devices from that manufacturer (sorted by device IDs).
*
- * All LPC/FWH parts (parallel flash) have 8-bit device IDs.
+ * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
+ * continuation code.
* All SPI parts have 16-bit device IDs.
*/
+#define GENERIC_DEVICE_ID 0x /* Only match the vendor ID */
+
#define ALLIANCE_ID0x52/* Alliance Semiconductor */
#define AMD_ID 0x01/* AMD */
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/flashchips.c2008-01-04 16:22:09 UTC (rev 3032)
@@ -185,5 +185,13 @@
probe_jedec, erase_chip_jedec, write_49f002},
{"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128,
probe_jedec, erase_chip_jedec, write_49f002},
+ {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID,0, 0,
+probe_spi, NULL, NULL},
+ {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
+ {"SST unknown SPI chip",SST_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
+ {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
{NULL,}
};
Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c 2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/spi.c 2008-01-04 16:22:09 UTC (rev 3032)
@@ -262,14 +262,19 @@
manuf_id = readarr[0];
model_id = (readarr[1] << 8) | readarr[2];
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__,
manuf_id, model_id);
- if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id) {
- /* Print the status register before erase to tell the
+ if (manuf_id == flash->manufacture_id &&
+ model_id == flash->model_id) {
+ /* Print the status register to tell the
* user about possible write protection.
*/
generic_spi_prettyprint_status_register(flash);
return 1;
}
+ /* Test if this is a pure vendor match. */
+ if (manuf_id == flash->manufacture_id &&
+ GENERIC_DEVICE_ID == flash->model_id)
+ return 1;
}
return 0;
--
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[LinuxBIOS] r3032 - trunk/util/flashrom
Author: hailfinger
Date: 2008-01-04 17:22:09 +0100 (Fri, 04 Jan 2008)
New Revision: 3032
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/spi.c
Log:
Print at least the vendor for SPI flash chips if the exact chip ID is
unknown.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/flash.h 2008-01-04 16:22:09 UTC (rev 3032)
@@ -59,10 +59,13 @@
* entry of each section should be the manufacturer ID, followed by the
* list of devices from that manufacturer (sorted by device IDs).
*
- * All LPC/FWH parts (parallel flash) have 8-bit device IDs.
+ * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
+ * continuation code.
* All SPI parts have 16-bit device IDs.
*/
+#define GENERIC_DEVICE_ID 0x /* Only match the vendor ID */
+
#define ALLIANCE_ID0x52/* Alliance Semiconductor */
#define AMD_ID 0x01/* AMD */
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/flashchips.c2008-01-04 16:22:09 UTC (rev 3032)
@@ -185,5 +185,13 @@
probe_jedec, erase_chip_jedec, write_49f002},
{"S29C31004T", SYNCMOS_ID, S29C31004T, 512, 128,
probe_jedec, erase_chip_jedec, write_49f002},
+ {"EON unknown SPI chip", EON_ID_NOPREFIX, GENERIC_DEVICE_ID,0, 0,
+probe_spi, NULL, NULL},
+ {"MX unknown SPI chip", MX_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
+ {"SST unknown SPI chip",SST_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
+ {"ST unknown SPI chip", ST_ID, GENERIC_DEVICE_ID, 0, 0,
+probe_spi, NULL, NULL},
{NULL,}
};
Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c 2007-12-31 14:05:08 UTC (rev 3031)
+++ trunk/util/flashrom/spi.c 2008-01-04 16:22:09 UTC (rev 3032)
@@ -262,14 +262,19 @@
manuf_id = readarr[0];
model_id = (readarr[1] << 8) | readarr[2];
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__,
manuf_id, model_id);
- if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id) {
- /* Print the status register before erase to tell the
+ if (manuf_id == flash->manufacture_id &&
+ model_id == flash->model_id) {
+ /* Print the status register to tell the
* user about possible write protection.
*/
generic_spi_prettyprint_status_register(flash);
return 1;
}
+ /* Test if this is a pure vendor match. */
+ if (manuf_id == flash->manufacture_id &&
+ GENERIC_DEVICE_ID == flash->model_id)
+ return 1;
}
return 0;
--
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[LinuxBIOS] r543 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Author: hailfinger Date: 2008-01-04 13:53:09 +0100 (Fri, 04 Jan 2008) New Revision: 543 Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: Move AMD Geode LX defines for CAR from a .S to a .h so they are available to C. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S === --- LinuxBIOSv3/arch/x86/geodelx/stage0.S 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/arch/x86/geodelx/stage0.S 2008-01-04 12:53:09 UTC (rev 543) @@ -28,24 +28,6 @@ #include "../macros.h" #include -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) - -#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ -#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x4000 /* Bit 30 = Cache Disable */ -#define CR0_NW 0x2000 /* Bit 29 = Not Write Through */ - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 - -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 - .code16 .globl _stage0 _stage0: Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h === --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 12:53:09 UTC (rev 543) @@ -567,7 +567,24 @@ /* */ #define DCACHE_RAM_SIZE 0x08000 #define DCACHE_RAM_BASE 0xc8000 +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) +#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ +#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x4000 /* Bit 30 = Cache Disable */ +#define CR0_NW 0x2000 /* Bit 29 = Not Write Through */ + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + /* POST CODES */ /* standard AMD post definitions -- might as well use them. */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r543 - in LinuxBIOSv3: arch/x86/geodelx include/arch/x86
Author: hailfinger Date: 2008-01-04 13:53:09 +0100 (Fri, 04 Jan 2008) New Revision: 543 Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S LinuxBIOSv3/include/arch/x86/amd_geodelx.h Log: Move AMD Geode LX defines for CAR from a .S to a .h so they are available to C. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: LinuxBIOSv3/arch/x86/geodelx/stage0.S === --- LinuxBIOSv3/arch/x86/geodelx/stage0.S 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/arch/x86/geodelx/stage0.S 2008-01-04 12:53:09 UTC (rev 543) @@ -28,24 +28,6 @@ #include "../macros.h" #include -/* This is where the DCache will be mapped and be used as stack. It would be - * cool if it was the same base as LinuxBIOS normal stack. - */ -#define LX_STACK_BASE DCACHE_RAM_BASE -#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) - -#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ -#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ -#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) -#define CR0_CD 0x4000 /* Bit 30 = Cache Disable */ -#define CR0_NW 0x2000 /* Bit 29 = Not Write Through */ - -#define ROM_CODE_SEG 0x08 -#define ROM_DATA_SEG 0x10 - -#define CACHE_RAM_CODE_SEG 0x18 -#define CACHE_RAM_DATA_SEG 0x20 - .code16 .globl _stage0 _stage0: Modified: LinuxBIOSv3/include/arch/x86/amd_geodelx.h === --- LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-12-11 01:24:52 UTC (rev 542) +++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2008-01-04 12:53:09 UTC (rev 543) @@ -567,7 +567,24 @@ /* */ #define DCACHE_RAM_SIZE 0x08000 #define DCACHE_RAM_BASE 0xc8000 +/* This is where the DCache will be mapped and be used as stack. It would be + * cool if it was the same base as LinuxBIOS normal stack. + */ +#define LX_STACK_BASE DCACHE_RAM_BASE +#define LX_STACK_END LX_STACK_BASE + (DCACHE_RAM_SIZE - 4) +#define LX_NUM_CACHELINES 0x080 /* There are 128 lines per way. */ +#define LX_CACHELINE_SIZE 0x020 /* There are 32 bytes per line. */ +#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE) +#define CR0_CD 0x4000 /* Bit 30 = Cache Disable */ +#define CR0_NW 0x2000 /* Bit 29 = Not Write Through */ + +#define ROM_CODE_SEG 0x08 +#define ROM_DATA_SEG 0x10 + +#define CACHE_RAM_CODE_SEG 0x18 +#define CACHE_RAM_DATA_SEG 0x20 + /* POST CODES */ /* standard AMD post definitions -- might as well use them. */ -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3031 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 15:05:08 +0100 (Mon, 31 Dec 2007)
New Revision: 3031
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
Log:
Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have
exactly the same ID. Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Markus Boas <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 01:49:00 UTC (rev 3030)
+++ trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031)
@@ -109,8 +109,8 @@
#define EN_29F040A 0x7F04
#define EN_29LV010 0x7F6E
#define EN_29LV040A0x7F4F /* EN_29LV040(A) */
-#define EN_29F002AT0x7F92
-#define EN_29F002AB0x7F97
+#define EN_29F002T 0x7F92
+#define EN_29F002B 0x7F97
#define FUJITSU_ID 0x04/* Fujitsu */
/* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-31 01:49:00 UTC (rev 3030)
+++ trunk/util/flashrom/flashchips.c2007-12-31 14:05:08 UTC (rev 3031)
@@ -42,9 +42,10 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"At49F002(N)T",ATMEL_ID, AT_49F002NT,256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
- /* The EN29F002AT can do byte program at arbitrary boundaries. */
- {"EN29F002AT", EON_ID, EN_29F002AT,256, 256,
+ {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
+ {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256,
+probe_jedec, erase_chip_jedec, write_jedec},
{"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 1024,
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
--
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[LinuxBIOS] r3031 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 15:05:08 +0100 (Mon, 31 Dec 2007)
New Revision: 3031
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
Log:
Unfortunately, EN29F002T, EN29F002AT, EN29F002ANT, EN29F002NT all have
exactly the same ID. Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Markus Boas <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 01:49:00 UTC (rev 3030)
+++ trunk/util/flashrom/flash.h 2007-12-31 14:05:08 UTC (rev 3031)
@@ -109,8 +109,8 @@
#define EN_29F040A 0x7F04
#define EN_29LV010 0x7F6E
#define EN_29LV040A0x7F4F /* EN_29LV040(A) */
-#define EN_29F002AT0x7F92
-#define EN_29F002AB0x7F97
+#define EN_29F002T 0x7F92
+#define EN_29F002B 0x7F97
#define FUJITSU_ID 0x04/* Fujitsu */
/* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-31 01:49:00 UTC (rev 3030)
+++ trunk/util/flashrom/flashchips.c2007-12-31 14:05:08 UTC (rev 3031)
@@ -42,9 +42,10 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"At49F002(N)T",ATMEL_ID, AT_49F002NT,256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
- /* The EN29F002AT can do byte program at arbitrary boundaries. */
- {"EN29F002AT", EON_ID, EN_29F002AT,256, 256,
+ {"EN29F002(A)(N)T", EON_ID, EN_29F002T, 256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
+ {"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256,
+probe_jedec, erase_chip_jedec, write_jedec},
{"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 1024,
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
--
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linuxbios@linuxbios.org
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[LinuxBIOS] r3030 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 02:49:00 +0100 (Mon, 31 Dec 2007)
New Revision: 3030
Added:
trunk/util/flashrom/en29f002a.c
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/jedec.c
Log:
Add continuation ID support to jedec.c
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Added: trunk/util/flashrom/en29f002a.c
===
--- trunk/util/flashrom/en29f002a.c (rev 0)
+++ trunk/util/flashrom/en29f002a.c 2007-12-31 01:49:00 UTC (rev 3030)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2007 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ EN29F512 has 1C,21
+ EN29F010 has 1C,20
+ EN29F040A has 1C,04
+ EN29LV010 has 1C,6E and uses short F0 reset sequence
+ EN29LV040(A) has 1C,4F and uses short F0 reset sequence
+ */
+int probe_en29f512(struct flashchip *flash)
+{
+ volatile uint8_t *bios = flash->virtual_memory;
+ uint8_t id1, id2;
+
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0x2AA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0x90;
+
+ myusec_delay(10);
+
+ id1 = *(volatile uint8_t *)(bios + 0x100);
+ id2 = *(volatile uint8_t *)(bios + 0x101);
+
+ /* exit by writing F0 anywhere? or the code below */
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0x2AA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0xF0;
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id)
+ return 1;
+
+ return 0;
+}
+
+/*
+ EN29F002AT has 1C,92
+ EN29F002AB has 1C,97
+ */
+int probe_en29f002a(struct flashchip *flash)
+{
+ volatile uint8_t *bios = flash->virtual_memory;
+ uint8_t id1, id2;
+
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0xAAA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0x90;
+
+ myusec_delay(10);
+
+ id1 = *(volatile uint8_t *)(bios + 0x100);
+ id2 = *(volatile uint8_t *)(bios + 0x101);
+
+ /* exit by writing F0 anywhere? or the code below */
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0xAAA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0xF0;
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id)
+ return 1;
+
+ return 0;
+}
+
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 01:18:26 UTC (rev 3029)
+++ trunk/util/flashrom/flash.h 2007-12-31 01:49:00 UTC (rev 3030)
@@ -32,8 +32,12 @@
struct flashchip {
const char *name;
- int manufacture_id;
- int model_id;
+ /* With 32bit manufacture_id and model_id we can cover IDs up to
+* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
+* Identification code.
+*/
+ uint32_t manufacture_id;
+ uint32_t model_id;
int total_size;
int page_size;
@@ -85,8 +89,14 @@
/*
* EN25 chips are SPI, first byte of device ID is memory type,
* second byte of device ID is l
[LinuxBIOS] r3030 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 02:49:00 +0100 (Mon, 31 Dec 2007)
New Revision: 3030
Added:
trunk/util/flashrom/en29f002a.c
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/jedec.c
Log:
Add continuation ID support to jedec.c
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Added: trunk/util/flashrom/en29f002a.c
===
--- trunk/util/flashrom/en29f002a.c (rev 0)
+++ trunk/util/flashrom/en29f002a.c 2007-12-31 01:49:00 UTC (rev 3030)
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2007 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ EN29F512 has 1C,21
+ EN29F010 has 1C,20
+ EN29F040A has 1C,04
+ EN29LV010 has 1C,6E and uses short F0 reset sequence
+ EN29LV040(A) has 1C,4F and uses short F0 reset sequence
+ */
+int probe_en29f512(struct flashchip *flash)
+{
+ volatile uint8_t *bios = flash->virtual_memory;
+ uint8_t id1, id2;
+
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0x2AA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0x90;
+
+ myusec_delay(10);
+
+ id1 = *(volatile uint8_t *)(bios + 0x100);
+ id2 = *(volatile uint8_t *)(bios + 0x101);
+
+ /* exit by writing F0 anywhere? or the code below */
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0x2AA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0xF0;
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id)
+ return 1;
+
+ return 0;
+}
+
+/*
+ EN29F002AT has 1C,92
+ EN29F002AB has 1C,97
+ */
+int probe_en29f002a(struct flashchip *flash)
+{
+ volatile uint8_t *bios = flash->virtual_memory;
+ uint8_t id1, id2;
+
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0xAAA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0x90;
+
+ myusec_delay(10);
+
+ id1 = *(volatile uint8_t *)(bios + 0x100);
+ id2 = *(volatile uint8_t *)(bios + 0x101);
+
+ /* exit by writing F0 anywhere? or the code below */
+ *(volatile uint8_t *)(bios + 0x555) = 0xAA;
+ *(volatile uint8_t *)(bios + 0xAAA) = 0x55;
+ *(volatile uint8_t *)(bios + 0x555) = 0xF0;
+
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, id1, id2);
+
+ if (id1 == flash->manufacture_id && id2 == flash->model_id)
+ return 1;
+
+ return 0;
+}
+
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-31 01:18:26 UTC (rev 3029)
+++ trunk/util/flashrom/flash.h 2007-12-31 01:49:00 UTC (rev 3030)
@@ -32,8 +32,12 @@
struct flashchip {
const char *name;
- int manufacture_id;
- int model_id;
+ /* With 32bit manufacture_id and model_id we can cover IDs up to
+* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
+* Identification code.
+*/
+ uint32_t manufacture_id;
+ uint32_t model_id;
int total_size;
int page_size;
@@ -85,8 +89,14 @@
/*
* EN25 chips are SPI, first byte of device ID is memory type,
* second byte of device ID is l
[LinuxBIOS] r3029 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 02:18:26 +0100 (Mon, 31 Dec 2007)
New Revision: 3029
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/m29f400bt.c
Log:
This fixes a few vendor IDs to conform with JEDEC publication 106W
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.
This patch should have no effect on code generation.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-30 11:59:10 UTC (rev 3028)
+++ trunk/util/flashrom/flash.h 2007-12-31 01:18:26 UTC (rev 3029)
@@ -59,16 +59,16 @@
* All SPI parts have 16-bit device IDs.
*/
-#define ALLIANCE_ID0x52/* Alliance */
+#define ALLIANCE_ID0x52/* Alliance Semiconductor */
#define AMD_ID 0x01/* AMD */
#define AM_29F040B 0xA4
#define AM_29LV040B0x4F
#define AM_29F016D 0xAD
-#define AMIC_ID0x37/* AMIC */
+#define AMIC_ID0x7F37 /* AMIC */
-#define ASD_ID 0x25/* ASD */
+#define ASD_ID 0x25/* ASD, not listed in JEP106W */
#define ASD_AE49F2008 0x52
#define ATMEL_ID 0x1F/* Atmel */
@@ -79,14 +79,14 @@
#define CATALYST_ID0x31/* Catalyst */
-#define EMST_ID0x8C/* EMST / EFST */
+#define EMST_ID0x8C/* EMST / EFST Elite Flash
Storage*/
#define EMST_F49B002UA 0x00
/*
* EN25 chips are SPI, first byte of device ID is memory type,
* second byte of device ID is log(bitsize)-9.
*/
-#define EON_ID 0x1C/* EON */
+#define EON_ID 0x1C/* EON Silicon Devices */
#define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
#define EN_25B10 0x2011
#define EN_25B20 0x2012
@@ -96,17 +96,24 @@
#define EN_25B32 0x2016
#define FUJITSU_ID 0x04/* Fujitsu */
-#define MBM29F400TC0x23
+/* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
+ * try to read it from a location not mentioned in the data sheet.
+ */
+#define MBM29F400TC_STRANGE0x23
+#define MBM29F400BC0x7B
+#define MBM29F400TC0x77
#define HYUNDAI_ID 0xAD/* Hyundai */
-#define IMT_ID 0x7F/* IMT */
+#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
+#define IM_29F004B 0xAE
+#define IM_29F004T 0xAF
#define INTEL_ID 0x89/* Intel */
-#define ISSI_ID0xD5/* ISSI */
+#define ISSI_ID0xD5/* ISSI Integrated Silicon
Solutions */
-#define MSYSTEMS_ID0x156F /* M-Systems */
+#define MSYSTEMS_ID0x156F /* M-Systems, not listed in JEP106W */
#define MSYSTEMS_MD22000xDB
#define MSYSTEMS_MD28000x30/* hmm -- both 0x30 */
#define MSYSTEMS_MD28020x30/* hmm -- both 0x30 */
@@ -128,6 +135,9 @@
#define MX_25L3235D0x2416
#define MX_29F002 0xB0
+/* Programmable Micro Corp is listed in JEP106W in bank 2, so it should have
+ * a 0x7F continuation code prefix.
+ */
#define PMC_ID 0x9D/* PMC */
#define PMC_49FL0020x6D
#define PMC_49FL0040x6E
@@ -171,7 +181,7 @@
* ST25P chips are SPI, first byte of device ID is memory type, second
* byte of device ID is related to log(bitsize) at least for some chips.
*/
-#define ST_ID 0x20/* ST */
+#define ST_ID 0x20/* ST / SGS/Thomson */
#define ST_M25P05A 0x2010
#define ST_M25P10A 0x2011
#define ST_M25P20 0x2012
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-30 11:59:10 UTC (rev 3028)
+++ trunk/util/flashrom/flashchips.c2007-12-31 01:18:26 UTC (rev 3029)
@@ -42,7 +42,7 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"At49F002(N)T",ATMEL_ID, AT_49F002NT,256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
- {"MBM29F400TC", FUJITSU_ID, MBM29F400TC,512, 64 * 1024,
+ {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 1024,
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
Modified: trunk/util/flashrom/m29f400bt.c
[LinuxBIOS] r3029 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-31 02:18:26 +0100 (Mon, 31 Dec 2007)
New Revision: 3029
Modified:
trunk/util/flashrom/flash.h
trunk/util/flashrom/flashchips.c
trunk/util/flashrom/m29f400bt.c
Log:
This fixes a few vendor IDs to conform with JEDEC publication 106W
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.
This patch should have no effect on code generation.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2007-12-30 11:59:10 UTC (rev 3028)
+++ trunk/util/flashrom/flash.h 2007-12-31 01:18:26 UTC (rev 3029)
@@ -59,16 +59,16 @@
* All SPI parts have 16-bit device IDs.
*/
-#define ALLIANCE_ID0x52/* Alliance */
+#define ALLIANCE_ID0x52/* Alliance Semiconductor */
#define AMD_ID 0x01/* AMD */
#define AM_29F040B 0xA4
#define AM_29LV040B0x4F
#define AM_29F016D 0xAD
-#define AMIC_ID0x37/* AMIC */
+#define AMIC_ID0x7F37 /* AMIC */
-#define ASD_ID 0x25/* ASD */
+#define ASD_ID 0x25/* ASD, not listed in JEP106W */
#define ASD_AE49F2008 0x52
#define ATMEL_ID 0x1F/* Atmel */
@@ -79,14 +79,14 @@
#define CATALYST_ID0x31/* Catalyst */
-#define EMST_ID0x8C/* EMST / EFST */
+#define EMST_ID0x8C/* EMST / EFST Elite Flash
Storage*/
#define EMST_F49B002UA 0x00
/*
* EN25 chips are SPI, first byte of device ID is memory type,
* second byte of device ID is log(bitsize)-9.
*/
-#define EON_ID 0x1C/* EON */
+#define EON_ID 0x1C/* EON Silicon Devices */
#define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
#define EN_25B10 0x2011
#define EN_25B20 0x2012
@@ -96,17 +96,24 @@
#define EN_25B32 0x2016
#define FUJITSU_ID 0x04/* Fujitsu */
-#define MBM29F400TC0x23
+/* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
+ * try to read it from a location not mentioned in the data sheet.
+ */
+#define MBM29F400TC_STRANGE0x23
+#define MBM29F400BC0x7B
+#define MBM29F400TC0x77
#define HYUNDAI_ID 0xAD/* Hyundai */
-#define IMT_ID 0x7F/* IMT */
+#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
+#define IM_29F004B 0xAE
+#define IM_29F004T 0xAF
#define INTEL_ID 0x89/* Intel */
-#define ISSI_ID0xD5/* ISSI */
+#define ISSI_ID0xD5/* ISSI Integrated Silicon
Solutions */
-#define MSYSTEMS_ID0x156F /* M-Systems */
+#define MSYSTEMS_ID0x156F /* M-Systems, not listed in JEP106W */
#define MSYSTEMS_MD22000xDB
#define MSYSTEMS_MD28000x30/* hmm -- both 0x30 */
#define MSYSTEMS_MD28020x30/* hmm -- both 0x30 */
@@ -128,6 +135,9 @@
#define MX_25L3235D0x2416
#define MX_29F002 0xB0
+/* Programmable Micro Corp is listed in JEP106W in bank 2, so it should have
+ * a 0x7F continuation code prefix.
+ */
#define PMC_ID 0x9D/* PMC */
#define PMC_49FL0020x6D
#define PMC_49FL0040x6E
@@ -171,7 +181,7 @@
* ST25P chips are SPI, first byte of device ID is memory type, second
* byte of device ID is related to log(bitsize) at least for some chips.
*/
-#define ST_ID 0x20/* ST */
+#define ST_ID 0x20/* ST / SGS/Thomson */
#define ST_M25P05A 0x2010
#define ST_M25P10A 0x2011
#define ST_M25P20 0x2012
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-30 11:59:10 UTC (rev 3028)
+++ trunk/util/flashrom/flashchips.c2007-12-31 01:18:26 UTC (rev 3029)
@@ -42,7 +42,7 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"At49F002(N)T",ATMEL_ID, AT_49F002NT,256, 256,
probe_jedec, erase_chip_jedec, write_jedec},
- {"MBM29F400TC", FUJITSU_ID, MBM29F400TC,512, 64 * 1024,
+ {"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 1024,
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
Modified: trunk/util/flashrom/m29f400bt.c
[LinuxBIOS] r3027 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 12:05:59 +0100 (Sat, 29 Dec 2007)
New Revision: 3027
Modified:
trunk/util/flashrom/flashchips.c
Log:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-29 10:15:58 UTC (rev 3026)
+++ trunk/util/flashrom/flashchips.c2007-12-29 11:05:59 UTC (rev 3027)
@@ -46,7 +46,7 @@
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
- {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024,
+ {"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
@@ -142,23 +142,23 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"M29F040B",ST_ID, ST_M29F040B,512, 64 * 1024,
probe_29f040b, erase_29f040b, write_29f040b},
- {"M25P05-A",ST_ID, ST_M25P05A, 64, 32 * 1024,
+ {"M25P05-A",ST_ID, ST_M25P05A, 64, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P10-A",ST_ID, ST_M25P10A, 128, 32 * 1024,
+ {"M25P10-A",ST_ID, ST_M25P10A, 128,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P20", ST_ID, ST_M25P20, 256, 64 * 1024,
+ {"M25P20", ST_ID, ST_M25P20, 256,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P40", ST_ID, ST_M25P40, 512, 64 * 1024,
+ {"M25P40", ST_ID, ST_M25P40, 512,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024,
+ {"M25P80", ST_ID, ST_M25P80, 1024, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P16", ST_ID, ST_M25P16, 2048, 64 * 1024,
+ {"M25P16", ST_ID, ST_M25P16, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P32", ST_ID, ST_M25P32, 4096, 64 * 1024,
+ {"M25P32", ST_ID, ST_M25P32, 4096, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P64", ST_ID, ST_M25P64, 8192, 64 * 1024,
+ {"M25P64", ST_ID, ST_M25P64, 8192, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P128", ST_ID, ST_M25P128, 16384, 256 * 1024,
+ {"M25P128", ST_ID, ST_M25P128, 16384, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"82802ab", 137,173,512, 64 * 1024,
probe_82802ab, erase_82802ab, write_82802ab},
--
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[LinuxBIOS] r3027 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 12:05:59 +0100 (Sat, 29 Dec 2007)
New Revision: 3027
Modified:
trunk/util/flashrom/flashchips.c
Log:
All SPI chips mentioned in flashchips.c had their sector size listed as
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-29 10:15:58 UTC (rev 3026)
+++ trunk/util/flashrom/flashchips.c2007-12-29 11:05:59 UTC (rev 3027)
@@ -46,7 +46,7 @@
probe_m29f400bt, erase_m29f400bt, write_linuxbios_m29f400bt},
{"MX29F002",MX_ID, MX_29F002, 256, 64 * 1024,
probe_29f002, erase_29f002, write_29f002},
- {"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024,
+ {"MX25L4005", MX_ID, MX_25L4005, 512, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
@@ -142,23 +142,23 @@
probe_jedec, erase_chip_jedec, write_jedec},
{"M29F040B",ST_ID, ST_M29F040B,512, 64 * 1024,
probe_29f040b, erase_29f040b, write_29f040b},
- {"M25P05-A",ST_ID, ST_M25P05A, 64, 32 * 1024,
+ {"M25P05-A",ST_ID, ST_M25P05A, 64, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P10-A",ST_ID, ST_M25P10A, 128, 32 * 1024,
+ {"M25P10-A",ST_ID, ST_M25P10A, 128,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P20", ST_ID, ST_M25P20, 256, 64 * 1024,
+ {"M25P20", ST_ID, ST_M25P20, 256,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P40", ST_ID, ST_M25P40, 512, 64 * 1024,
+ {"M25P40", ST_ID, ST_M25P40, 512,256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P80", ST_ID, ST_M25P80, 1024, 64 * 1024,
+ {"M25P80", ST_ID, ST_M25P80, 1024, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P16", ST_ID, ST_M25P16, 2048, 64 * 1024,
+ {"M25P16", ST_ID, ST_M25P16, 2048, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P32", ST_ID, ST_M25P32, 4096, 64 * 1024,
+ {"M25P32", ST_ID, ST_M25P32, 4096, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P64", ST_ID, ST_M25P64, 8192, 64 * 1024,
+ {"M25P64", ST_ID, ST_M25P64, 8192, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
- {"M25P128", ST_ID, ST_M25P128, 16384, 256 * 1024,
+ {"M25P128", ST_ID, ST_M25P128, 16384, 256,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"82802ab", 137,173,512, 64 * 1024,
probe_82802ab, erase_82802ab, write_82802ab},
--
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[LinuxBIOS] r3026 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 11:15:58 +0100 (Sat, 29 Dec 2007)
New Revision: 3026
Modified:
trunk/util/flashrom/spi.c
Log:
Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c 2007-12-29 10:14:38 UTC (rev 3025)
+++ trunk/util/flashrom/spi.c 2007-12-29 10:15:58 UTC (rev 3026)
@@ -78,6 +78,8 @@
uint16_t it8716f_flashport = 0;
+void generic_spi_prettyprint_status_register(struct flashchip *flash);
+
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
{
@@ -220,7 +222,7 @@
{
if (it8716f_flashport)
return it8716f_spi_command(it8716f_flashport, writecnt,
readcnt, writearr, readarr);
- printf("%s called, but no SPI chipset detected\n", __FUNCTION__);
+ printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
return 1;
}
@@ -230,7 +232,7 @@
if (generic_spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd,
readarr))
return 1;
- printf("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
readarr[2]);
+ printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
readarr[2]);
return 0;
}
@@ -260,8 +262,14 @@
manuf_id = readarr[0];
model_id = (readarr[1] << 8) | readarr[2];
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__,
manuf_id, model_id);
- if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id)
+ if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id) {
+ /* Print the status register before erase to tell the
+* user about possible write protection.
+*/
+ generic_spi_prettyprint_status_register(flash);
+
return 1;
+ }
}
return 0;
@@ -277,13 +285,48 @@
return readarr[0];
}
+/* Prettyprint the status register. Works for
+ * ST M25P series
+ * MX MX25L series
+ */
+void generic_spi_prettyprint_status_register_st_m25p(uint8_t status)
+{
+ printf_debug("Chip status register: Status Register Write Disable "
+ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 6 is "
+ "%sset\n", (status & (1 << 6)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 5 is "
+ "%sset\n", (status & (1 << 5)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 2 (BP2) is "
+ "%sset\n", (status & (1 << 4)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 1 (BP1) is "
+ "%sset\n", (status & (1 << 3)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 0 (BP0) is "
+ "%sset\n", (status & (1 << 2)) ? "" : "not ");
+ printf_debug("Chip status register: Write Enable Latch (WEL) is "
+ "%sset\n", (status & (1 << 1)) ? "" : "not ");
+ printf_debug("Chip status register: Write In Progress (WIP) is "
+ "%sset\n", (status & (1 << 0)) ? "" : "not ");
+}
+
+void generic_spi_prettyprint_status_register(struct flashchip *flash)
+{
+ uint8_t status;
+
+ status = generic_spi_read_status_register();
+ printf_debug("Chip status register is %02x\n", status);
+ switch (flash->manufacture_id) {
+ case ST_ID:
+ case MX_ID:
+ if ((flash->model_id & 0xff00) == 0x2000)
+ generic_spi_prettyprint_status_register_st_m25p(status);
+ break;
+ }
+}
+
int generic_spi_chip_erase_c7(struct flashchip *flash)
{
const unsigned char cmd[] = JEDEC_CE_C7;
- uint8_t statusreg;
-
- statusreg = generic_spi_read_status_register();
- printf("chip status register before erase is %02x\n", statusreg);
generic_spi_write_enable();
/* Send CE (Chip Erase) */
--
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[LinuxBIOS] r3026 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 11:15:58 +0100 (Sat, 29 Dec 2007)
New Revision: 3026
Modified:
trunk/util/flashrom/spi.c
Log:
Print the chip status register for all SPI chips on probe if verbose
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c 2007-12-29 10:14:38 UTC (rev 3025)
+++ trunk/util/flashrom/spi.c 2007-12-29 10:15:58 UTC (rev 3026)
@@ -78,6 +78,8 @@
uint16_t it8716f_flashport = 0;
+void generic_spi_prettyprint_status_register(struct flashchip *flash);
+
/* Generic Super I/O helper functions */
uint8_t regval(uint16_t port, uint8_t reg)
{
@@ -220,7 +222,7 @@
{
if (it8716f_flashport)
return it8716f_spi_command(it8716f_flashport, writecnt,
readcnt, writearr, readarr);
- printf("%s called, but no SPI chipset detected\n", __FUNCTION__);
+ printf_debug("%s called, but no SPI chipset detected\n", __FUNCTION__);
return 1;
}
@@ -230,7 +232,7 @@
if (generic_spi_command(JEDEC_RDID_OUTSIZE, JEDEC_RDID_INSIZE, cmd,
readarr))
return 1;
- printf("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
readarr[2]);
+ printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
readarr[2]);
return 0;
}
@@ -260,8 +262,14 @@
manuf_id = readarr[0];
model_id = (readarr[1] << 8) | readarr[2];
printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__,
manuf_id, model_id);
- if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id)
+ if (manuf_id == flash->manufacture_id && model_id ==
flash->model_id) {
+ /* Print the status register before erase to tell the
+* user about possible write protection.
+*/
+ generic_spi_prettyprint_status_register(flash);
+
return 1;
+ }
}
return 0;
@@ -277,13 +285,48 @@
return readarr[0];
}
+/* Prettyprint the status register. Works for
+ * ST M25P series
+ * MX MX25L series
+ */
+void generic_spi_prettyprint_status_register_st_m25p(uint8_t status)
+{
+ printf_debug("Chip status register: Status Register Write Disable "
+ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 6 is "
+ "%sset\n", (status & (1 << 6)) ? "" : "not ");
+ printf_debug("Chip status register: Bit 5 is "
+ "%sset\n", (status & (1 << 5)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 2 (BP2) is "
+ "%sset\n", (status & (1 << 4)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 1 (BP1) is "
+ "%sset\n", (status & (1 << 3)) ? "" : "not ");
+ printf_debug("Chip status register: Block Protect 0 (BP0) is "
+ "%sset\n", (status & (1 << 2)) ? "" : "not ");
+ printf_debug("Chip status register: Write Enable Latch (WEL) is "
+ "%sset\n", (status & (1 << 1)) ? "" : "not ");
+ printf_debug("Chip status register: Write In Progress (WIP) is "
+ "%sset\n", (status & (1 << 0)) ? "" : "not ");
+}
+
+void generic_spi_prettyprint_status_register(struct flashchip *flash)
+{
+ uint8_t status;
+
+ status = generic_spi_read_status_register();
+ printf_debug("Chip status register is %02x\n", status);
+ switch (flash->manufacture_id) {
+ case ST_ID:
+ case MX_ID:
+ if ((flash->model_id & 0xff00) == 0x2000)
+ generic_spi_prettyprint_status_register_st_m25p(status);
+ break;
+ }
+}
+
int generic_spi_chip_erase_c7(struct flashchip *flash)
{
const unsigned char cmd[] = JEDEC_CE_C7;
- uint8_t statusreg;
-
- statusreg = generic_spi_read_status_register();
- printf("chip status register before erase is %02x\n", statusreg);
generic_spi_write_enable();
/* Send CE (Chip Erase) */
--
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[LinuxBIOS] r3025 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 11:14:38 +0100 (Sat, 29 Dec 2007)
New Revision: 3025
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-28 00:23:29 UTC (rev 3024)
+++ trunk/util/flashrom/flashchips.c2007-12-29 10:14:38 UTC (rev 3025)
@@ -48,6 +48,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
+ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,
probe_jedec, erase_chip_jedec, write_jedec},
{"SST28SF040A", SST_ID, SST_28SF040,512, 256,
--
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[LinuxBIOS] r3025 - trunk/util/flashrom
Author: hailfinger
Date: 2007-12-29 11:14:38 +0100 (Sat, 29 Dec 2007)
New Revision: 3025
Modified:
trunk/util/flashrom/flashchips.c
Log:
Add 25VF016B support to flashrom. Untested, but verified against the
data sheet.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2007-12-28 00:23:29 UTC (rev 3024)
+++ trunk/util/flashrom/flashchips.c2007-12-29 10:14:38 UTC (rev 3025)
@@ -48,6 +48,8 @@
probe_29f002, erase_29f002, write_29f002},
{"MX25L4005", MX_ID, MX_25L4005, 512, 4 * 1024,
probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
+ {"SST25VF016B", SST_ID, SST_25VF016B, 2048, 256,
+ probe_spi, generic_spi_chip_erase_c7, generic_spi_chip_write},
{"SST29EE020A", SST_ID, SST_29EE020A, 256, 128,
probe_jedec, erase_chip_jedec, write_jedec},
{"SST28SF040A", SST_ID, SST_28SF040,512, 256,
--
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[LinuxBIOS] r3024 - trunk/LinuxBIOSv2/src/include/device
Author: hailfinger Date: 2007-12-28 01:23:29 +0100 (Fri, 28 Dec 2007) New Revision: 3024 Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h Log: Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs. Signed-off-by: Ed Swierk <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h === --- trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-21 17:21:03 UTC (rev 3023) +++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-28 00:23:29 UTC (rev 3024) @@ -2326,6 +2326,17 @@ #define PCI_DEVICE_ID_INTEL_6300ESB_PCI_X 0x25ae #define PCI_DEVICE_ID_INTEL_6300ESB_WDT0x25ab +/* Intel 3100 */ +#define PCI_DEVICE_ID_INTEL_3100_ISA0x2670 +#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c +#define PCI_DEVICE_ID_INTEL_3100_PCI0x244e +#define PCI_DEVICE_ID_INTEL_3100_USB0x2688 +#define PCI_DEVICE_ID_INTEL_3100_SMB0x269b +#define PCI_DEVICE_ID_INTEL_3100_USB2 0x2689 +#define PCI_DEVICE_ID_INTEL_3100_USB3 0x268c +#define PCI_DEVICE_ID_INTEL_3100_SATA 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_SATA_R 0x2681 + #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 @@ -2352,6 +2363,8 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PA1 0x3596 #define PCI_DEVICE_ID_INTEL_PCIE_PB0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC0x3599 +#define PCI_DEVICE_ID_INTEL_PCIE_QA0x35b6 +#define PCI_DEVICE_ID_INTEL_PCIE_QA1 0x35b7 #define PCI_VENDOR_ID_COMPUTONE0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3024 - trunk/LinuxBIOSv2/src/include/device
Author: hailfinger Date: 2007-12-28 01:23:29 +0100 (Fri, 28 Dec 2007) New Revision: 3024 Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h Log: Add Intel 3100 integrated northbridge/southbridge/superio PCI IDs. Signed-off-by: Ed Swierk <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/include/device/pci_ids.h === --- trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-21 17:21:03 UTC (rev 3023) +++ trunk/LinuxBIOSv2/src/include/device/pci_ids.h 2007-12-28 00:23:29 UTC (rev 3024) @@ -2326,6 +2326,17 @@ #define PCI_DEVICE_ID_INTEL_6300ESB_PCI_X 0x25ae #define PCI_DEVICE_ID_INTEL_6300ESB_WDT0x25ab +/* Intel 3100 */ +#define PCI_DEVICE_ID_INTEL_3100_ISA0x2670 +#define PCI_DEVICE_ID_INTEL_3100_EHCI 0x268c +#define PCI_DEVICE_ID_INTEL_3100_PCI0x244e +#define PCI_DEVICE_ID_INTEL_3100_USB0x2688 +#define PCI_DEVICE_ID_INTEL_3100_SMB0x269b +#define PCI_DEVICE_ID_INTEL_3100_USB2 0x2689 +#define PCI_DEVICE_ID_INTEL_3100_USB3 0x268c +#define PCI_DEVICE_ID_INTEL_3100_SATA 0x2680 +#define PCI_DEVICE_ID_INTEL_3100_SATA_R 0x2681 + #define PCI_DEVICE_ID_INTEL_80310 0x530d #define PCI_DEVICE_ID_INTEL_82810_MC1 0x7120 #define PCI_DEVICE_ID_INTEL_82810_IG1 0x7121 @@ -2352,6 +2363,8 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PA1 0x3596 #define PCI_DEVICE_ID_INTEL_PCIE_PB0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC0x3599 +#define PCI_DEVICE_ID_INTEL_PCIE_QA0x35b6 +#define PCI_DEVICE_ID_INTEL_PCIE_QA1 0x35b7 #define PCI_VENDOR_ID_COMPUTONE0x8e0e #define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291 -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r89 - in buildrom-devel: config/platforms packages/linuxbios packages/linuxbios/patches
Author: myles Date: 2007-12-22 04:21:44 +0100 (Sat, 22 Dec 2007) New Revision: 89 Added: buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch Modified: buildrom-devel/config/platforms/Config.in buildrom-devel/config/platforms/platforms.conf buildrom-devel/config/platforms/serengeti_cheetah.conf buildrom-devel/packages/linuxbios/serengeti_cheetah.mk Log: This adds support for the AMD Serengeti Cheetah board with a family 10 processor to buildrom. Signed-off-by: Marc Jones <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/Config.in === --- buildrom-devel/config/platforms/Config.in 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/Config.in 2007-12-22 03:21:44 UTC (rev 89) @@ -104,6 +104,11 @@ select PLATFORM select PLATFORM_SUPPORT_64BIT +config PLATFORM_CHEETAH_FAM10 + bool "AMD Serengeti-Cheetah with fam10 processor" + depends VENDOR_AMD + select PLATFORM + select PLATFORM_SUPPORT_64BIT endchoice config BUILD_QEMU Modified: buildrom-devel/config/platforms/platforms.conf === --- buildrom-devel/config/platforms/platforms.conf 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/platforms.conf 2007-12-22 03:21:44 UTC (rev 89) @@ -16,6 +16,7 @@ PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf PLATFORM-$(CONFIG_PLATFORM_SUPERMICRO_H8DMR) = supermicro-h8dmr.conf PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf +PLATFORM-$(CONFIG_PLATFORM_CHEETAH_FAM10) = serengeti_cheetah.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-i386) = qemu.conf Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf === --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-22 03:21:44 UTC (rev 89) @@ -1,5 +1,5 @@ # Support for the AMD Serengeti_Cheetah Platform -# This should work for most K8+8111 platforms +# This should work for most K8/fam10+8111 platforms Platform configuration @@ -42,12 +42,21 @@ # LinuxBIOS configuration +ifeq ($(CONFIG_PLATFORM_CHEETAH_FAM10),y) LINUXBIOS_VENDOR=amd +LINUXBIOS_BOARD=serengeti_cheetah_fam10 +LINUXBIOS_CONFIG=Config.lb +LINUXBIOS_TDIR=serengeti_cheetah_fam10 +LINUXBIOS_TAG=3018 +LINUXBIOS_ROM_NAME=amd-cheetah-fam10.rom +else +LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=serengeti_cheetah LINUXBIOS_TAG=2950 LINUXBIOS_ROM_NAME=serengeti_cheetah.rom +endif # FILO configuration Added: buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch === --- buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch (rev 0) +++ buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch 2007-12-22 03:21:44 UTC (rev 89) @@ -0,0 +1,44 @@ +Index: svn/targets/amd/serengeti_cheetah_fam10/Config.lb +======= +--- svn/targets/amd/serengeti_cheetah_fam10/Config.lb (revision 3018) svn/targets/amd/serengeti_cheetah_fam10/Config.lb (working copy) +@@ -29,29 +29,14 @@ + # At a maximum only compile in this level of debugging + option MAXIMUM_CONSOLE_LOGLEVEL=11 + +-# 512KB ROM +-option ROM_SIZE=512*1024 ++# 1024KB ROM ++option ROM_SIZE=1024*1024 ++option FALLBACK_SIZE=ROM_SIZE-FAILOVER_SIZE + +-# Cheetah Family 10 +-#romimage "normal" +-# 1MB ROM +-# option ROM_SIZE = 0x10 +-# option USE_FAILOVER_IMAGE=0 +-# option USE_FALLBACK_IMAGE=0 +-# option ROM_IMAGE_SIZE=0x2 +-# option ROM_IMAGE_SIZE=0x3 +-# option XIP_ROM_SIZE=0x4 +-# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +-# payload ../payload.elf +-#end +- + romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 +-# option ROM_IMAGE_SIZE=0x13800 +-# option ROM_IMAGE_SIZE=0x19800 +- option ROM_IMAGE_SIZE=0x3f000 +-# option ROM_IMAGE_SIZE=0x15800 ++ option ROM_IMAGE_SIZE=0x3 + option XIP_ROM_SIZE=0x4 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload ../payload.elf +@@ -65,6 +50,5 @@ + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + end + +-#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover" + buildrom ./amd-cheetah-fam1
[LinuxBIOS] r89 - in buildrom-devel: config/platforms packages/linuxbios packages/linuxbios/patches
Author: myles Date: 2007-12-22 04:21:44 +0100 (Sat, 22 Dec 2007) New Revision: 89 Added: buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch Modified: buildrom-devel/config/platforms/Config.in buildrom-devel/config/platforms/platforms.conf buildrom-devel/config/platforms/serengeti_cheetah.conf buildrom-devel/packages/linuxbios/serengeti_cheetah.mk Log: This adds support for the AMD Serengeti Cheetah board with a family 10 processor to buildrom. Signed-off-by: Marc Jones <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/Config.in === --- buildrom-devel/config/platforms/Config.in 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/Config.in 2007-12-22 03:21:44 UTC (rev 89) @@ -104,6 +104,11 @@ select PLATFORM select PLATFORM_SUPPORT_64BIT +config PLATFORM_CHEETAH_FAM10 + bool "AMD Serengeti-Cheetah with fam10 processor" + depends VENDOR_AMD + select PLATFORM + select PLATFORM_SUPPORT_64BIT endchoice config BUILD_QEMU Modified: buildrom-devel/config/platforms/platforms.conf === --- buildrom-devel/config/platforms/platforms.conf 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/platforms.conf 2007-12-22 03:21:44 UTC (rev 89) @@ -16,6 +16,7 @@ PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf PLATFORM-$(CONFIG_PLATFORM_SUPERMICRO_H8DMR) = supermicro-h8dmr.conf PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf +PLATFORM-$(CONFIG_PLATFORM_CHEETAH_FAM10) = serengeti_cheetah.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-i386) = qemu.conf Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf === --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-20 18:02:49 UTC (rev 88) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2007-12-22 03:21:44 UTC (rev 89) @@ -1,5 +1,5 @@ # Support for the AMD Serengeti_Cheetah Platform -# This should work for most K8+8111 platforms +# This should work for most K8/fam10+8111 platforms Platform configuration @@ -42,12 +42,21 @@ # LinuxBIOS configuration +ifeq ($(CONFIG_PLATFORM_CHEETAH_FAM10),y) LINUXBIOS_VENDOR=amd +LINUXBIOS_BOARD=serengeti_cheetah_fam10 +LINUXBIOS_CONFIG=Config.lb +LINUXBIOS_TDIR=serengeti_cheetah_fam10 +LINUXBIOS_TAG=3018 +LINUXBIOS_ROM_NAME=amd-cheetah-fam10.rom +else +LINUXBIOS_VENDOR=amd LINUXBIOS_BOARD=serengeti_cheetah LINUXBIOS_CONFIG=Config.lb LINUXBIOS_TDIR=serengeti_cheetah LINUXBIOS_TAG=2950 LINUXBIOS_ROM_NAME=serengeti_cheetah.rom +endif # FILO configuration Added: buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch === --- buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch (rev 0) +++ buildrom-devel/packages/linuxbios/patches/serengeti_cheetah_fam10-lab.patch 2007-12-22 03:21:44 UTC (rev 89) @@ -0,0 +1,44 @@ +Index: svn/targets/amd/serengeti_cheetah_fam10/Config.lb +======= +--- svn/targets/amd/serengeti_cheetah_fam10/Config.lb (revision 3018) svn/targets/amd/serengeti_cheetah_fam10/Config.lb (working copy) +@@ -29,29 +29,14 @@ + # At a maximum only compile in this level of debugging + option MAXIMUM_CONSOLE_LOGLEVEL=11 + +-# 512KB ROM +-option ROM_SIZE=512*1024 ++# 1024KB ROM ++option ROM_SIZE=1024*1024 ++option FALLBACK_SIZE=ROM_SIZE-FAILOVER_SIZE + +-# Cheetah Family 10 +-#romimage "normal" +-# 1MB ROM +-# option ROM_SIZE = 0x10 +-# option USE_FAILOVER_IMAGE=0 +-# option USE_FALLBACK_IMAGE=0 +-# option ROM_IMAGE_SIZE=0x2 +-# option ROM_IMAGE_SIZE=0x3 +-# option XIP_ROM_SIZE=0x4 +-# option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal" +-# payload ../payload.elf +-#end +- + romimage "fallback" + option USE_FAILOVER_IMAGE=0 + option USE_FALLBACK_IMAGE=1 +-# option ROM_IMAGE_SIZE=0x13800 +-# option ROM_IMAGE_SIZE=0x19800 +- option ROM_IMAGE_SIZE=0x3f000 +-# option ROM_IMAGE_SIZE=0x15800 ++ option ROM_IMAGE_SIZE=0x3 + option XIP_ROM_SIZE=0x4 + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback" + payload ../payload.elf +@@ -65,6 +50,5 @@ + option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover" + end + +-#buildrom ./amd-cheetah-fam10.rom ROM_SIZE "normal" "fallback" "failover" + buildrom ./amd-cheetah-fam1
[LinuxBIOS] r3023 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Author: duwe
Date: 2007-12-21 18:21:03 +0100 (Fri, 21 Dec 2007)
New Revision: 3023
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
Log:
Add an interrupt entry for the onboard firewire controller,
Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
(verified on an v1.0 board).
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2007-12-21
16:38:21 UTC (rev 3022)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2007-12-21
17:21:03 UTC (rev 3023)
@@ -137,7 +137,7 @@
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i,
apicid_mcp55, 0x10 + (3+i+j)%4);
}
-
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[1], ((0x0a)<<2)|0, apicid_mcp55, 0x12);
/*Local Ints: TypePolarityTrigger Bus ID IRQAPIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, MP_APIC_ALL, 0x1);
--
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[LinuxBIOS] r3023 - trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli
Author: duwe
Date: 2007-12-21 18:21:03 +0100 (Fri, 21 Dec 2007)
New Revision: 3023
Modified:
trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
Log:
Add an interrupt entry for the onboard firewire controller,
Bus 1, device 10 (function 0 only), routed to IO-APIC pin 18
(verified on an v1.0 board).
Signed-off-by: Torsten Duwe <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c
===
--- trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2007-12-21
16:38:21 UTC (rev 3022)
+++ trunk/LinuxBIOSv2/src/mainboard/gigabyte/m57sli/mptable.c 2007-12-21
17:21:03 UTC (rev 3023)
@@ -137,7 +137,7 @@
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i,
apicid_mcp55, 0x10 + (3+i+j)%4);
}
-
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_mcp55[1], ((0x0a)<<2)|0, apicid_mcp55, 0x12);
/*Local Ints: TypePolarityTrigger Bus ID IRQAPIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x0, MP_APIC_ALL, 0x1);
--
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[LinuxBIOS] r3022 - trunk/LinuxBIOSv2/targets/asus/a8n_e
Author: uwe Date: 2007-12-21 17:38:21 +0100 (Fri, 21 Dec 2007) New Revision: 3022 Modified: trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb Log: Change default payload to /tmp/filo.elf (trivial). It's easier to tell users "copy your payload to /tmp/filo.elf" than have them guess paths or modify Config.lb files etc. Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]> Acked-by: Uwe Hermann <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb === --- trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb 2007-12-19 19:30:36 UTC (rev 3021) +++ trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb 2007-12-21 16:38:21 UTC (rev 3022) @@ -28,8 +28,7 @@ option ROM_IMAGE_SIZE=0x2 option XIP_ROM_SIZE=0x2 option LINUXBIOS_EXTRA_VERSION="_Normal" -# payload ../../../../../../payloads/dummy.elf - payload ../../../../../../payloads/filo.elf + payload /tmp/filo.elf end romimage "fallback" @@ -38,8 +37,7 @@ option ROM_IMAGE_SIZE=0x2 option XIP_ROM_SIZE=0x2 option LINUXBIOS_EXTRA_VERSION="_Fallback" -# payload ../../../../../../payloads/memtest.elf - payload ../../../../../../payloads/filo.elf + payload /tmp/filo.elf end romimage "failover" -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3022 - trunk/LinuxBIOSv2/targets/asus/a8n_e
Author: uwe Date: 2007-12-21 17:38:21 +0100 (Fri, 21 Dec 2007) New Revision: 3022 Modified: trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb Log: Change default payload to /tmp/filo.elf (trivial). It's easier to tell users "copy your payload to /tmp/filo.elf" than have them guess paths or modify Config.lb files etc. Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]> Acked-by: Uwe Hermann <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb === --- trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb 2007-12-19 19:30:36 UTC (rev 3021) +++ trunk/LinuxBIOSv2/targets/asus/a8n_e/Config.lb 2007-12-21 16:38:21 UTC (rev 3022) @@ -28,8 +28,7 @@ option ROM_IMAGE_SIZE=0x2 option XIP_ROM_SIZE=0x2 option LINUXBIOS_EXTRA_VERSION="_Normal" -# payload ../../../../../../payloads/dummy.elf - payload ../../../../../../payloads/filo.elf + payload /tmp/filo.elf end romimage "fallback" @@ -38,8 +37,7 @@ option ROM_IMAGE_SIZE=0x2 option XIP_ROM_SIZE=0x2 option LINUXBIOS_EXTRA_VERSION="_Fallback" -# payload ../../../../../../payloads/memtest.elf - payload ../../../../../../payloads/filo.elf + payload /tmp/filo.elf end romimage "failover" -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r88 - buildrom-devel/config/platforms
Author: jcrouse Date: 2007-12-20 19:02:49 +0100 (Thu, 20 Dec 2007) New Revision: 88 Modified: buildrom-devel/config/platforms/platforms.conf Log: Remove an old line that is no longer need - I missed it in a previous patch. Very trivial. Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/platforms.conf === --- buildrom-devel/config/platforms/platforms.conf 2007-12-19 20:13:22 UTC (rev 87) +++ buildrom-devel/config/platforms/platforms.conf 2007-12-20 18:02:49 UTC (rev 88) @@ -16,7 +16,6 @@ PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf PLATFORM-$(CONFIG_PLATFORM_SUPERMICRO_H8DMR) = supermicro-h8dmr.conf PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf -PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH_64) = serengeti_cheetah-x86_64.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-i386) = qemu.conf -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r88 - buildrom-devel/config/platforms
Author: jcrouse Date: 2007-12-20 19:02:49 +0100 (Thu, 20 Dec 2007) New Revision: 88 Modified: buildrom-devel/config/platforms/platforms.conf Log: Remove an old line that is no longer need - I missed it in a previous patch. Very trivial. Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]> Modified: buildrom-devel/config/platforms/platforms.conf === --- buildrom-devel/config/platforms/platforms.conf 2007-12-19 20:13:22 UTC (rev 87) +++ buildrom-devel/config/platforms/platforms.conf 2007-12-20 18:02:49 UTC (rev 88) @@ -16,7 +16,6 @@ PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf PLATFORM-$(CONFIG_PLATFORM_SUPERMICRO_H8DMR) = supermicro-h8dmr.conf PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH) = serengeti_cheetah.conf -PLATFORM-$(CONFIG_PLATFORM_SERENGETI_CHEETAH_64) = serengeti_cheetah-x86_64.conf PLATFORM-$(CONFIG_PLATFORM_GA_2761GXDK) = ga-2761gxdk.conf PLATFORM-$(CONFIG_PLATFORM_QEMU-i386) = qemu.conf -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r87 - buildrom-devel/packages/kexec-boot-loader
Author: myles Date: 2007-12-19 21:13:22 +0100 (Wed, 19 Dec 2007) New Revision: 87 Modified: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch Log: Trivial removal of doubled patch lines, didn't break the build, just not needed. Signed-off-by: Myles Watson <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Modified: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch === --- buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 19:52:21 UTC (rev 86) +++ buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 20:13:22 UTC (rev 87) @@ -15,22 +15,3 @@ + $(PROGS): $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ - kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 -+++ kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 -@@ -18,6 +18,15 @@ - - all: olpc-boot-loader - -+kexec/x86-setup-32.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ -+ -+kexec/x86-setup-16.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ -+ -+kexec/x86-setup-16-debug.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ -+ - $(PROGS): - $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ - -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r87 - buildrom-devel/packages/kexec-boot-loader
Author: myles Date: 2007-12-19 21:13:22 +0100 (Wed, 19 Dec 2007) New Revision: 87 Modified: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch Log: Trivial removal of doubled patch lines, didn't break the build, just not needed. Signed-off-by: Myles Watson <[EMAIL PROTECTED]> Acked-by: Myles Watson <[EMAIL PROTECTED]> Modified: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch === --- buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 19:52:21 UTC (rev 86) +++ buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 20:13:22 UTC (rev 87) @@ -15,22 +15,3 @@ + $(PROGS): $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ - kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 -+++ kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 -@@ -18,6 +18,15 @@ - - all: olpc-boot-loader - -+kexec/x86-setup-32.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ -+ -+kexec/x86-setup-16.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ -+ -+kexec/x86-setup-16-debug.o: -+ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ -+ - $(PROGS): - $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ - -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r86 - buildrom-devel/packages/kexec-boot-loader
Author: myles Date: 2007-12-19 20:52:21 +0100 (Wed, 19 Dec 2007) New Revision: 86 Added: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch Modified: buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk Log: This patch explicitly uses gcc to build the .S files, so that the correct flags get passed in. Added: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch === --- buildrom-devel/packages/kexec-boot-loader/cross_compile.patch (rev 0) +++ buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 19:52:21 UTC (rev 86) @@ -0,0 +1,36 @@ +--- kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 +@@ -18,6 +18,15 @@ + + all: olpc-boot-loader + ++kexec/x86-setup-32.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16-debug.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ ++ + $(PROGS): + $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ + +--- kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 +@@ -18,6 +18,15 @@ + + all: olpc-boot-loader + ++kexec/x86-setup-32.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16-debug.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ ++ + $(PROGS): + $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ + Modified: buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk === --- buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk 2007-12-14 14:23:56 UTC (rev 85) +++ buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk 2007-12-19 19:52:21 UTC (rev 86) @@ -16,6 +16,8 @@ KBL_TARGET=$(INITRD_DIR)/kbl endif +KBL_PATCHES += $(PACKAGE_DIR)/kexec-boot-loader/cross_compile.patch + ifeq ($(CONFIG_VERBOSE),y) KBL_BUILD_LOG=/dev/stdout KBL_INSTALL_LOG=/dev/stdout -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r86 - buildrom-devel/packages/kexec-boot-loader
Author: myles Date: 2007-12-19 20:52:21 +0100 (Wed, 19 Dec 2007) New Revision: 86 Added: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch Modified: buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk Log: This patch explicitly uses gcc to build the .S files, so that the correct flags get passed in. Added: buildrom-devel/packages/kexec-boot-loader/cross_compile.patch === --- buildrom-devel/packages/kexec-boot-loader/cross_compile.patch (rev 0) +++ buildrom-devel/packages/kexec-boot-loader/cross_compile.patch 2007-12-19 19:52:21 UTC (rev 86) @@ -0,0 +1,36 @@ +--- kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 +@@ -18,6 +18,15 @@ + + all: olpc-boot-loader + ++kexec/x86-setup-32.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16-debug.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ ++ + $(PROGS): + $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ + +--- kexec-boot-loader.org/Makefile 2007-12-07 10:28:26.0 -0700 kexec-boot-loader/Makefile 2007-12-07 10:28:47.0 -0700 +@@ -18,6 +18,15 @@ + + all: olpc-boot-loader + ++kexec/x86-setup-32.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-32.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16.S -nostdlib -c -o $@ ++ ++kexec/x86-setup-16-debug.o: ++ $(CC) $(CFLAGS) kexec/x86-setup-16-debug.S -nostdlib -c -o $@ ++ + $(PROGS): + $(CC) $(CFLAGS) [EMAIL PROTECTED] -nostdlib -o $@ + Modified: buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk === --- buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk 2007-12-14 14:23:56 UTC (rev 85) +++ buildrom-devel/packages/kexec-boot-loader/kexec-boot-loader.mk 2007-12-19 19:52:21 UTC (rev 86) @@ -16,6 +16,8 @@ KBL_TARGET=$(INITRD_DIR)/kbl endif +KBL_PATCHES += $(PACKAGE_DIR)/kexec-boot-loader/cross_compile.patch + ifeq ($(CONFIG_VERBOSE),y) KBL_BUILD_LOG=/dev/stdout KBL_INSTALL_LOG=/dev/stdout -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3021 - in trunk/LinuxBIOSv2: src/northbridge/amd/amdfam10 targets/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 20:30:36 +0100 (Wed, 19 Dec 2007) New Revision: 3021 Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb Log: More abuild fixes, this should be the last (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb === --- trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb2007-12-19 18:29:59 UTC (rev 3020) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb2007-12-19 19:30:36 UTC (rev 3021) @@ -34,42 +34,42 @@ object amdfam10_acpi.o makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" + action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" action "mv ssdt.hex ssdt.c" end object ./ssdt.o makerule sspr1.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" + action "iasl -p $(PWD)/sspr1 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex" action "mv sspr1.hex sspr1.c" end object ./sspr1.o makerule sspr2.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" + action "iasl -p $(PWD)/sspr2 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex" action "mv sspr2.hex sspr2.c" end object ./sspr2.o makerule sspr3.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" + action "iasl -p $(PWD)/sspr3 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex" action "mv sspr3.hex sspr3.c" end object ./sspr3.o makerule sspr4.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" + action "iasl -p $(PWD)/sspr4 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex" action "mv sspr4.hex sspr4.c" end object ./sspr4.o makerule sspr5.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" + action "iasl -p $(PWD)/sspr5 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex" action "mv sspr5.hex sspr5.c" end Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb === --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2007-12-19 19:30:36 UTC (rev 3021) @@ -0,0 +1,29 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=1024*1024 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x2 + option LINUXBIOS_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION=".0-failover" +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" \ No newline at end of file -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3021 - in trunk/LinuxBIOSv2: src/northbridge/amd/amdfam10 targets/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 20:30:36 +0100 (Wed, 19 Dec 2007) New Revision: 3021 Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb Log: More abuild fixes, this should be the last (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb === --- trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb2007-12-19 18:29:59 UTC (rev 3020) +++ trunk/LinuxBIOSv2/src/northbridge/amd/amdfam10/Config.lb2007-12-19 19:30:36 UTC (rev 3021) @@ -34,42 +34,42 @@ object amdfam10_acpi.o makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" + action "iasl -p $(PWD)/ssdt -tc $(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt.hex" action "mv ssdt.hex ssdt.c" end object ./ssdt.o makerule sspr1.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" + action "iasl -p $(PWD)/sspr1 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr1.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr1/g' sspr1.hex" action "mv sspr1.hex sspr1.c" end object ./sspr1.o makerule sspr2.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" + action "iasl -p $(PWD)/sspr2 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr2.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr2/g' sspr2.hex" action "mv sspr2.hex sspr2.c" end object ./sspr2.o makerule sspr3.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" + action "iasl -p $(PWD)/sspr3 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr3.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr3/g' sspr3.hex" action "mv sspr3.hex sspr3.c" end object ./sspr3.o makerule sspr4.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" + action "iasl -p $(PWD)/sspr4 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr4.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr4/g' sspr4.hex" action "mv sspr4.hex sspr4.c" end object ./sspr4.o makerule sspr5.c depends "$(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" - action "iasl -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" + action "iasl -p $(PWD)/sspr5 -tc $(TOP)/src/northbridge/amd/amdfam10/sspr5.dsl" action "perl -pi -e 's/AmlCode/AmlCode_sspr5/g' sspr5.hex" action "mv sspr5.hex sspr5.c" end Added: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb === --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb (rev 0) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb 2007-12-19 19:30:36 UTC (rev 3021) @@ -0,0 +1,29 @@ +# This will make a target directory of ./VENDOR_MAINBOARD + +target VENDOR_MAINBOARD +mainboard VENDOR/MAINBOARD + +option CC="CROSSCC" +option CROSS_COMPILE="CROSS_PREFIX" +option HOSTCC="CROSS_HOSTCC" + +__COMPRESSION__ + +option ROM_SIZE=1024*1024 + +romimage "fallback" + option USE_FALLBACK_IMAGE=1 + option ROM_IMAGE_SIZE=0x2 + option LINUXBIOS_EXTRA_VERSION=".0-fallback" + payload __PAYLOAD__ +end + +romimage "failover" + option USE_FAILOVER_IMAGE=1 + option USE_FALLBACK_IMAGE=0 + option ROM_IMAGE_SIZE=FAILOVER_SIZE + option XIP_ROM_SIZE=FAILOVER_SIZE + option LINUXBIOS_EXTRA_VERSION=".0-failover" +end + +buildrom ./linuxbios.rom ROM_SIZE "fallback" "failover" \ No newline at end of file -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3020 - trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 19:29:59 +0100 (Wed, 19 Dec 2007) New Revision: 3020 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb Log: Fix for newer iasl versions (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb === --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 17:59:50 UTC (rev 3019) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 18:29:59 UTC (rev 3020) @@ -90,7 +90,7 @@ object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o @@ -100,28 +100,28 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -tc $(MAINBOARD)/dx/pci5.asl" + action "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3020 - trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 19:29:59 +0100 (Wed, 19 Dec 2007) New Revision: 3020 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb Log: Fix for newer iasl versions (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb === --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 17:59:50 UTC (rev 3019) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 18:29:59 UTC (rev 3020) @@ -90,7 +90,7 @@ object fadt.o makerule dsdt.c depends "$(MAINBOARD)/dx/dsdt_lb.dsl" - action "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" + action "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "mv dsdt_lb.hex dsdt.c" end object ./dsdt.o @@ -100,28 +100,28 @@ if ACPI_SSDTX_NUM makerule ssdt2.c depends "$(MAINBOARD)/dx/pci2.asl" - action "iasl -tc $(MAINBOARD)/dx/pci2.asl" + action "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex" action "mv pci2.hex ssdt2.c" end object ./ssdt2.o makerule ssdt3.c depends "$(MAINBOARD)/dx/pci3.asl" - action "iasl -tc $(MAINBOARD)/dx/pci3.asl" + action "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex" action "mv pci3.hex ssdt3.c" end object ./ssdt3.o makerule ssdt4.c depends "$(MAINBOARD)/dx/pci4.asl" - action "iasl -tc $(MAINBOARD)/dx/pci4.asl" + action "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex" action "mv pci4.hex ssdt4.c" end object ./ssdt4.o makerule ssdt5.c depends "$(MAINBOARD)/dx/pci5.asl" - action "iasl -tc $(MAINBOARD)/dx/pci5.asl" + action "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "mv pci5.hex ssdt5.c" end -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3019 - trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10
Author: stepan Date: 2007-12-19 18:59:50 +0100 (Wed, 19 Dec 2007) New Revision: 3019 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: trivial fix for abuild. Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb === --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2007-12-19 08:07:37 UTC (rev 3018) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2007-12-19 17:59:50 UTC (rev 3019) @@ -42,6 +42,8 @@ uses ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3019 - trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10
Author: stepan Date: 2007-12-19 18:59:50 +0100 (Wed, 19 Dec 2007) New Revision: 3019 Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb Log: trivial fix for abuild. Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb === --- trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2007-12-19 08:07:37 UTC (rev 3018) +++ trunk/LinuxBIOSv2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2007-12-19 17:59:50 UTC (rev 3019) @@ -42,6 +42,8 @@ uses ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_ROM_PAYLOAD_START +uses CONFIG_COMPRESSED_PAYLOAD_LZMA +uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses PAYLOAD_SIZE uses _ROMBASE uses XIP_ROM_SIZE -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3018 - trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 09:07:37 +0100 (Wed, 19 Dec 2007) New Revision: 3018 Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb Log: Small fix to make the abuild happy, add ROM_SIZE to target/*/Config.lb, using the default from src/mainboard/*/Options.lb (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb === --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 01:52:11 UTC (rev 3017) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 08:07:37 UTC (rev 3018) @@ -29,6 +29,9 @@ # At a maximum only compile in this level of debugging option MAXIMUM_CONSOLE_LOGLEVEL=11 +# 512KB ROM +option ROM_SIZE=512*1024 + # Cheetah Family 10 #romimage "normal" # 1MB ROM -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
[LinuxBIOS] r3018 - trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10
Author: cozzie Date: 2007-12-19 09:07:37 +0100 (Wed, 19 Dec 2007) New Revision: 3018 Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb Log: Small fix to make the abuild happy, add ROM_SIZE to target/*/Config.lb, using the default from src/mainboard/*/Options.lb (trivial) Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> Acked-by: Corey Osgood <[EMAIL PROTECTED]> Modified: trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb === --- trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 01:52:11 UTC (rev 3017) +++ trunk/LinuxBIOSv2/targets/amd/serengeti_cheetah_fam10/Config.lb 2007-12-19 08:07:37 UTC (rev 3018) @@ -29,6 +29,9 @@ # At a maximum only compile in this level of debugging option MAXIMUM_CONSOLE_LOGLEVEL=11 +# 512KB ROM +option ROM_SIZE=512*1024 + # Cheetah Family 10 #romimage "normal" # 1MB ROM -- linuxbios mailing list linuxbios@linuxbios.org http://www.linuxbios.org/mailman/listinfo/linuxbios
