[PATCH 1/3] PPC440EP SoC and Bamboo board support
Hello, This adds support for the AMCC PPC440EP SoC and the Bamboo reference board. This patch makes use of fpu.S. Signed-off by: Wade Farnsworth -- next part -- A non-text attachment was scrubbed... Name: 440ep-ppc.patch Type: text/x-patch Size: 58807 bytes Desc: not available Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050726/e35722dd/attachment.bin
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Wed, 2005-04-06 at 10:37, Eugene Surovegin wrote:
> On Wed, Apr 06, 2005 at 10:21:25AM -0700, Wade Farnsworth wrote:
> >
> > This patch adds support for the IBM/AMCC PPC440EP SoC and the Bamboo
> > reference board.
>
> [snip]
>
> > + * Bamboo external IRQ triggering/polarity settings
> > + */
> > +unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet
> > transceiver */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector
> > */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
> > + (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
> > + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
> > +};
>
> You need to define ppc4xx_core_uic_cfg[] in ibm440ep.c for this thing
> to work, otherwise it's ignored.
Thanks, Eugene. This patch includes that array.
-Wade
Signed-off by: Wade Farnsworth
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[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Wed, Apr 06, 2005 at 10:21:25AM -0700, Wade Farnsworth wrote:
>
> This patch adds support for the IBM/AMCC PPC440EP SoC and the Bamboo
> reference board.
[snip]
> + * Bamboo external IRQ triggering/polarity settings
> + */
> +unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet
> transceiver */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector
> */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
> + (IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
> +};
You need to define ppc4xx_core_uic_cfg[] in ibm440ep.c for this thing
to work, otherwise it's ignored.
--
Eugene
[PATCH 1/3] PPC440EP SoC and Bamboo board support
Hi all, This patch adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference board. -Wade Farnsworth Signed-off by: Wade Farnsworth -- next part -- A non-text attachment was scrubbed... Name: ibm440ep-ppc.patch Type: text/x-patch Size: 61322 bytes Desc: not available Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050406/9ca259fc/attachment.bin
[PATCH 1/3] PPC440EP SoC and Bamboo board support
Do you need a 'special' toolchain to work around Errata 42 (isync before blrl) for user-space, or are the kernel-land fixes sufficient? -- Jason McMullan TimeSys Corporation -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: This is a digitally signed message part Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050316/f96821c8/attachment.pgp
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Wed, 2005-03-16 at 10:26, Jason McMullan wrote: > Do you need a 'special' toolchain to work around Errata 42 (isync before > blrl) for user-space, or are the kernel-land fixes sufficient? Yes, this work around also needs to be in gcc. I know this has been fixed in MontaVista's toolchain, but I don't know if the work around has been pushed up to the main gcc tree. -Wade Farnsworth
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Tue, 2005-03-15 at 18:43, Josh Boyer wrote: > On Tue, 2005-03-15 at 10:17 -0700, Wade Farnsworth wrote: > > Hello all, > > > > This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference > > board. Any comments would be appreciated. > > Isn't the NAND chip on that board a 64MiB chip? If so, the > BAMBOO_NAND_FLASH_SIZE define is wrong. It should be 0x400. > > Also, are there any plans to add MTD support for the NAND controller > found on those boards? > > thx, > josh Yes, you're right. I'll fix that. I'm working on MTD support, including support for the NAND controller. Thanks, Wade Farnsworth
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Tue, 2005-03-15 at 10:17 -0700, Wade Farnsworth wrote: > Hello all, > > This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference > board. Any comments would be appreciated. Isn't the NAND chip on that board a 64MiB chip? If so, the BAMBOO_NAND_FLASH_SIZE define is wrong. It should be 0x400. Also, are there any plans to add MTD support for the NAND controller found on those boards? thx, josh
[PATCH 1/3] PPC440EP SoC and Bamboo board support
I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect. According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask, so the correct code should look more like: memory_size = 0x - (memory_size - 1); PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS); (assuming 'memory_size' is a power of 2) -- Jason McMullan TimeSys Corporation -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 189 bytes Desc: This is a digitally signed message part Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050315/df535600/attachment.pgp
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Tue, 2005-03-15 at 13:58, Jason McMullan wrote: > I think your setup for BAMBOO_PCIL0_PTM1MS is actually incorrect. > According to the AMCC 440EP docs, BAMBOO_PCIL0_PTM1MS is a mask, > so the correct code should look more like: > > memory_size = 0x - (memory_size - 1); > PCI_WRITEL(memory_size | 1, BAMBOO_PCIL0_PTM1MS); > > (assuming 'memory_size' is a power of 2) Jason, I think you're right. Your way is much more concise too. Thanks, Wade Farnsworth
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Tue, 2005-03-15 at 11:41, Eugene Surovegin wrote: [snip] > > > diff -uprN linux-2.6.11-bk7/include/asm-ppc/reg.h > > linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h > > --- linux-2.6.11-bk7/include/asm-ppc/reg.h 2005-03-11 16:25:22.0 > > -0700 > > +++ linux-2.6.11-bk7-440ep/include/asm-ppc/reg.h2005-03-14 > > 10:05:47.0 -0700 > > @@ -449,6 +449,8 @@ > > #define PVR_STB03XXX 0x4031 > > #define PVR_NP405H 0x4141 > > #define PVR_NP405L 0x4161 > > +#define PVR_440EP_RA 0x42221850 > > +#define PVR_440EP_RB 0x422218D3 > > > I don't think it's needed. There are plans to get rid of all not-used > PVR defines. The PVR for the Rev A is needed for a workaround in the IBM EMAC code (see patch 3/3). If there is a better way to do this, or if it would be better to put the PVR define somewhere else, please let me know. Thanks for your comments. Regards, Wade Farnsworth
[PATCH 1/3] PPC440EP SoC and Bamboo board support
On Tue, Mar 15, 2005 at 10:17:19AM -0700, Wade Farnsworth wrote:
> Hello all,
>
> This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference
> board. Any comments would be appreciated.
[snip]
> diff -uprN linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c
> linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c
> --- linux-2.6.11-bk7/arch/ppc/platforms/4xx/ibm440ep.c1969-12-31
> 17:00:00.0 -0700
> +++ linux-2.6.11-bk7-440ep/arch/ppc/platforms/4xx/ibm440ep.c 2005-03-11
> 16:26:19.0 -0700
> @@ -0,0 +1,176 @@
> +/*
> + * arch/ppc/platforms/4xx/ibm440ep.c
> + *
> + * PPC440EP I/O descriptions
> + *
> + * Wade Farnsworth
> + * Copyright 2004 MontaVista Software Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#include
> +#include
> +#include
> +#include
> +
> +static struct ocp_func_emac_data ibm440ep_emac0_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0,/* ZMII device index */
> + .zmii_mux = 0,/* ZMII input of this EMAC */
> + .mal_idx= 0,/* MAL device index */
> + .mal_rx_chan= 0,/* MAL rx channel number */
> + .mal_tx_chan= 0,/* MAL tx channel number */
> + .wol_irq= 61, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx= -1, /* No TAH */
> +};
> +
> +static struct ocp_func_emac_data ibm440ep_emac1_def = {
> + .rgmii_idx = -1, /* No RGMII */
> + .rgmii_mux = -1, /* No RGMII */
> + .zmii_idx = 0,/* ZMII device index */
> + .zmii_mux = 1,/* ZMII input of this EMAC */
> + .mal_idx= 0,/* MAL device index */
> + .mal_rx_chan= 1,/* MAL rx channel number */
> + .mal_tx_chan= 2,/* MAL tx channel number */
> + .wol_irq= 63, /* WOL interrupt number */
> + .mdio_idx = -1, /* No shared MDIO */
> + .tah_idx= -1, /* No TAH */
> +};
> +OCP_SYSFS_EMAC_DATA()
> +
> +static struct ocp_func_mal_data ibm440ep_mal0_def = {
> + .num_tx_chans = 4,/* Number of TX channels */
> + .num_rx_chans = 2,/* Number of RX channels */
> + .txeob_irq = 10, /* TX End Of Buffer IRQ */
> + .rxeob_irq = 11, /* RX End Of Buffer IRQ */
> + .txde_irq = 33, /* TX Descriptor Error IRQ */
> + .rxde_irq = 34, /* RX Descriptor Error IRQ */
> + .serr_irq = 32, /* MAL System Error IRQ*/
> +};
> +OCP_SYSFS_MAL_DATA()
> +
> +static struct ocp_func_iic_data ibm440ep_iic0_def = {
> + .fast_mode = 0,/* Use standad mode (100Khz) */
> +};
> +
> +static struct ocp_func_iic_data ibm440ep_iic1_def = {
> + .fast_mode = 0,/* Use standad mode (100Khz) */
> +};
> +OCP_SYSFS_IIC_DATA()
> +
> +struct ocp_def core_ocp[] = {
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_OPB,
> + .index= 0,
> + .paddr= 0xEF60,
> + .irq = OCP_IRQ_NA,
> + .pm = OCP_CPM_NA,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index= 0,
> + .paddr= PPC440EP_UART0_ADDR,
> + .irq = UART0_INT,
> + .pm = IBM_CPM_UART0,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index= 1,
> + .paddr= PPC440EP_UART1_ADDR,
> + .irq = UART1_INT,
> + .pm = IBM_CPM_UART1,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index= 2,
> + .paddr= PPC440EP_UART2_ADDR,
> + .irq = UART2_INT,
> + .pm = IBM_CPM_UART2,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_16550,
> + .index= 3,
> + .paddr= PPC440EP_UART3_ADDR,
> + .irq = UART3_INT,
> + .pm = IBM_CPM_UART3,
> + },
> + { .vendor = OCP_VENDOR_IBM,
> + .function = OCP_FUNC_IIC,
> + .index= 0,
> + .paddr= PPC440EP_IIC0_ADDR,
Do we need PPC440EP_IIC0_ADDR define? I think not, please, don't
introduce useless defines which are only used in one file. Use numbers
directly, it helps readability. Please, look at how this is
handled in other 4xx platfo
[PATCH 1/3] PPC440EP SoC and Bamboo board support
Hello all, This adds support for the IBM/AMCC PPC440EP SoC and the Bamboo reference board. Any comments would be appreciated. Regards, Wade Farnsworth Signed-off-by: Wade Farnsworth -- next part -- A non-text attachment was scrubbed... Name: ibm440ep-ppc.patch Type: text/x-patch Size: 82336 bytes Desc: not available Url : http://ozlabs.org/pipermail/linuxppc-embedded/attachments/20050315/4a67c59b/attachment.bin
