[Mesa-dev] [Bug 96176] Cannot build non-intel drivers without python3.
https://bugs.freedesktop.org/show_bug.cgi?id=96176 Bug ID: 96176 Summary: Cannot build non-intel drivers without python3. Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: All Status: NEW Keywords: bisected, regression Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org CC: emil.l.veli...@gmail.com mesa: 998829f4045a98d16797e9d2f5094c35eb272909 (master 11.3.0-devel) Regression introduced with this commit. commit 2cd687ce97f39bd98fab4d72d607b7a1644cd2a0 Author: Emil Velikov Date: Wed May 4 11:47:14 2016 +0100 configure.ac: error out when building from git without python3 Bail early, as opposed to later on during the build. Signed-off-by: Emil Velikov -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl: add GL_EXT_clip_cull_distance define, add helpers
Reviewed-by: Tobias Klausmann
On 25.05.2016 01:59, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
This addresses the feedback I got after pushing the enablement patch.
docs/relnotes/11.3.0.html | 1 +
src/compiler/glsl/builtin_variables.cpp | 10 --
src/compiler/glsl/glcpp/glcpp-parse.y | 2 ++
src/compiler/glsl/glsl_parser_extras.h | 12
4 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 5871ec8..8d6caa2 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe
GL_ATI_fragment_shader on all Gallium drivers
GL_EXT_base_instance on all drivers that support GL_ARB_base_instance
+GL_EXT_clip_cull_distance on all drivers that support
GL_ARB_cull_distance
GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers that
support GL_ARB_draw_buffers_blend
GL_OES_sample_shading on i965, nvc0, r600, radeonsi
GL_OES_sample_variables on i965, nvc0, r600, radeonsi
diff --git a/src/compiler/glsl/builtin_variables.cpp
b/src/compiler/glsl/builtin_variables.cpp
index 3d34028..15d791c 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -674,14 +674,13 @@ builtin_variable_generator::generate_constants()
state->Const.MaxProgramTexelOffset);
}
- if (state->is_version(130, 0) || state->EXT_clip_cull_distance_enable) {
+ if (state->has_clip_distance()) {
add_const("gl_MaxClipDistances", state->Const.MaxClipPlanes);
}
if (state->is_version(130, 0)) {
add_const("gl_MaxVaryingComponents", state->ctx->Const.MaxVarying * 4);
}
- if (state->is_version(450, 0) || state->ARB_cull_distance_enable ||
- state->EXT_clip_cull_distance_enable) {
+ if (state->has_cull_distance()) {
add_const("gl_MaxCullDistances", state->Const.MaxClipPlanes);
add_const("gl_MaxCombinedClipAndCullDistances",
state->Const.MaxClipPlanes);
@@ -1259,12 +1258,11 @@ builtin_variable_generator::generate_varyings()
}
}
- if (state->is_version(130, 0) || state->EXT_clip_cull_distance_enable) {
+ if (state->has_clip_distance()) {
add_varying(VARYING_SLOT_CLIP_DIST0, array(float_t, 0),
"gl_ClipDistance");
}
- if (state->is_version(450, 0) || state->ARB_cull_distance_enable ||
- state->EXT_clip_cull_distance_enable) {
+ if (state->has_cull_distance()) {
add_varying(VARYING_SLOT_CULL_DIST0, array(float_t, 0),
"gl_CullDistance");
}
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 820458a..8048f8d 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -2310,6 +2310,8 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
add_builtin_define(parser,
"GL_OES_texture_storage_multisample_2d_array", 1);
if (extensions->ARB_blend_func_extended)
add_builtin_define(parser, "GL_EXT_blend_func_extended", 1);
+ if (extensions->ARB_cull_distance)
+add_builtin_define(parser, "GL_EXT_clip_cull_distance", 1);
if (version >= 310) {
if (extensions->ARB_shader_image_load_store)
diff --git a/src/compiler/glsl/glsl_parser_extras.h
b/src/compiler/glsl/glsl_parser_extras.h
index 3afc9cb..2e77b24 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -272,6 +272,18 @@ struct _mesa_glsl_parse_state {
is_version(150, 320);
}
+ bool has_clip_distance() const
+ {
+ return EXT_clip_cull_distance_enable || is_version(130, 0);
+ }
+
+ bool has_cull_distance() const
+ {
+ return EXT_clip_cull_distance_enable ||
+ ARB_cull_distance_enable ||
+ is_version(450, 0);
+ }
+
void process_version_directive(YYLTYPE *locp, int version,
const char *ident);
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Re: [Mesa-dev] [PATCH] mesa: Add .gitignore entries for make check binaries
On Tue, May 24, 2016 at 9:07 PM, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > Signed-off-by: Kristian Høgsberg Kristensen > --- > src/compiler/.gitignore | 4 > src/compiler/nir/tests/.gitignore| 1 + > src/mesa/drivers/dri/i965/.gitignore | 3 +++ > src/util/.gitignore | 1 + > src/util/tests/hash_table/.gitignore | 1 + > 5 files changed, 10 insertions(+) > create mode 100644 src/compiler/nir/tests/.gitignore > > diff --git a/src/compiler/.gitignore b/src/compiler/.gitignore > index 6fb069f..c0e6299 100644 > --- a/src/compiler/.gitignore > +++ b/src/compiler/.gitignore > @@ -1 +1,5 @@ > glsl_compiler > +subtest-cr > +subtest-cr-lf > +subtest-lf > +subtest-lf-cr > diff --git a/src/compiler/nir/tests/.gitignore > b/src/compiler/nir/tests/.gitignore > new file mode 100644 > index 000..12332f6 > --- /dev/null > +++ b/src/compiler/nir/tests/.gitignore > @@ -0,0 +1 @@ > +control_flow_tests > diff --git a/src/mesa/drivers/dri/i965/.gitignore > b/src/mesa/drivers/dri/i965/.gitignore > index 70aae3f..a6ecc92 100644 > --- a/src/mesa/drivers/dri/i965/.gitignore > +++ b/src/mesa/drivers/dri/i965/.gitignore > @@ -4,3 +4,6 @@ test_eu_compact > test_vec4_copy_propagation > test_vec4_register_coalesce > test_vf_float_conversions > +test_fs_cmod_propagation > +test_fs_saturate_propagation > +test_vec4_cmod_propagation > diff --git a/src/util/.gitignore b/src/util/.gitignore > index ecf4985..497662a 100644 > --- a/src/util/.gitignore > +++ b/src/util/.gitignore > @@ -1,2 +1,3 @@ > format_srgb.c > u_atomic_test > +roundeven_test > diff --git a/src/util/tests/hash_table/.gitignore > b/src/util/tests/hash_table/.gitignore > index 1b9aaf4..a0d50ab 100644 > --- a/src/util/tests/hash_table/.gitignore > +++ b/src/util/tests/hash_table/.gitignore > @@ -8,3 +8,4 @@ null_destroy > random_entry > remove_null > replacement > +clear > -- Acked-by: Matt Turner (I see a lot of tests I added. I always do out-of-tree builds, so I don't ever see this) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/2] scons 2.5.0 support
> Sure. Unfortunately, the series does not apply cleanly on ToT master: > > % git am p[12].txt > Applying: scons: whitespace cleanup > Using index info to reconstruct a base tree... > error: patch failed: src/gallium/state_trackers/wgl/SConscript:12 > error: src/gallium/state_trackers/wgl/SConscript: patch does not apply > Did you hand edit your patch? > It does not apply to blobs recorded in its index. > Cannot fall back to three-way merge. > Patch failed at 0001 scons: whitespace cleanup > The copy of the patch that failed is found in: >/home/brianp/mesa/.git/rebase-apply/patch > When you have resolved this problem, run "git am --continue". > If you prefer to skip this patch, run "git am --skip" instead. > To restore the original branch and stop patching, run "git am --abort". That's very odd. I'm on master from anongit.freedesktop.org/mesa/mesa and I had no issues rebasing. > Can you update the patches and send them to me? Thanks. Sure. I'll take the opportunity to add the lines suggested by Emil and also document the shell command used to generate the first patch. Best regards, -- Giuseppe "Oblomov" Bilotta ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Add .gitignore entries for make check binaries
From: Kristian Høgsberg Kristensen Signed-off-by: Kristian Høgsberg Kristensen --- src/compiler/.gitignore | 4 src/compiler/nir/tests/.gitignore| 1 + src/mesa/drivers/dri/i965/.gitignore | 3 +++ src/util/.gitignore | 1 + src/util/tests/hash_table/.gitignore | 1 + 5 files changed, 10 insertions(+) create mode 100644 src/compiler/nir/tests/.gitignore diff --git a/src/compiler/.gitignore b/src/compiler/.gitignore index 6fb069f..c0e6299 100644 --- a/src/compiler/.gitignore +++ b/src/compiler/.gitignore @@ -1 +1,5 @@ glsl_compiler +subtest-cr +subtest-cr-lf +subtest-lf +subtest-lf-cr diff --git a/src/compiler/nir/tests/.gitignore b/src/compiler/nir/tests/.gitignore new file mode 100644 index 000..12332f6 --- /dev/null +++ b/src/compiler/nir/tests/.gitignore @@ -0,0 +1 @@ +control_flow_tests diff --git a/src/mesa/drivers/dri/i965/.gitignore b/src/mesa/drivers/dri/i965/.gitignore index 70aae3f..a6ecc92 100644 --- a/src/mesa/drivers/dri/i965/.gitignore +++ b/src/mesa/drivers/dri/i965/.gitignore @@ -4,3 +4,6 @@ test_eu_compact test_vec4_copy_propagation test_vec4_register_coalesce test_vf_float_conversions +test_fs_cmod_propagation +test_fs_saturate_propagation +test_vec4_cmod_propagation diff --git a/src/util/.gitignore b/src/util/.gitignore index ecf4985..497662a 100644 --- a/src/util/.gitignore +++ b/src/util/.gitignore @@ -1,2 +1,3 @@ format_srgb.c u_atomic_test +roundeven_test diff --git a/src/util/tests/hash_table/.gitignore b/src/util/tests/hash_table/.gitignore index 1b9aaf4..a0d50ab 100644 --- a/src/util/tests/hash_table/.gitignore +++ b/src/util/tests/hash_table/.gitignore @@ -8,3 +8,4 @@ null_destroy random_entry remove_null replacement +clear -- 2.5.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/draw: Use the correct buffer index for interleaved VBO sizes
On Tue, May 24, 2016 at 7:48 PM, Kristian Høgsberg wrote: > On Tue, May 24, 2016 at 5:01 PM, Jason Ekstrand > wrote: > > The buffer_range_* arrays are indexed by buffer index not element index. > > Reviewed-by: Kristian Høgsberg > Thanks! > > --- > > src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 -- > > 1 file changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c > b/src/mesa/drivers/dri/i965/brw_draw_upload.c > > index 3349161..f4d1b2c 100644 > > --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c > > +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c > > @@ -529,8 +529,10 @@ brw_prepare_vertices(struct brw_context *brw) > >input->buffer = brw->vb.enabled[k]->buffer; > >input->offset = glarray->Ptr - other->Ptr; > > > > - buffer_range_start[k] = MIN2(buffer_range_start[k], > start); > > - buffer_range_end[k] = MAX2(buffer_range_end[k], start + > range); > > + buffer_range_start[input->buffer] = > > + MIN2(buffer_range_start[input->buffer], start); > > + buffer_range_end[input->buffer] = > > + MAX2(buffer_range_end[input->buffer], start + range); > >break; > > } > > } > > -- > > 2.5.0.400.gff86faf > > > > ___ > > mesa-dev mailing list > > mesa-dev@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa/bufferobj: use mapping range in BufferSubData.
From: Dave Airlie
According to GL4.5 spec:
An INVALID_OPERATION error is generated if any part of the speci-
fied buffer range is mapped with MapBufferRange or MapBuffer (see sec-
tion 6.3), unless it was mapped with MAP_PERSISTENT_BIT set in the Map-
BufferRange access flags.
So we should use the if range is mapped path.
This fixes:
GL45-CTS.buffer_storage.map_persistent_buffer_sub_data
Signed-off-by: Dave Airlie
---
src/mesa/main/bufferobj.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 33bc574..795cb16 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1765,7 +1765,7 @@ _mesa_buffer_sub_data(struct gl_context *ctx, struct
gl_buffer_object *bufObj,
const char *func)
{
if (!buffer_object_subdata_range_good(ctx, bufObj, offset, size,
- false, func)) {
+ true, func)) {
/* error already recorded */
return;
}
--
2.5.5
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Re: [Mesa-dev] [PATCH v3] mesa: Enable GL_KHR_robustness
On Tue, May 24, 2016 at 8:19 PM, Ilia Mirkin wrote: > On Tue, May 24, 2016 at 10:41 PM, Kristian Høgsberg > wrote: >> From: Kristian Høgsberg Kristensen >> >> GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry >> points that we already implement. This patch adds a new dispatch >> table that returns GL_CONTEXT_LOST from all entry points and >> implements the GL_LOSE_CONTEXT_ON_RESET by setting that table when we >> learn that we've lost the context. >> >> With the GL_CONTEXT_LOST reporting in place and dispatch for the new >> entry points we can turn on GL_KHR_robustness. >> >> Signed-off-by: Kristian Høgsberg Kristensen >> Reviewed-by: Ian Romanick >> >> --- >> >> v3: Only advertise for GLES2.0+, fix typo and dispatch_sanity >> issue. Reword commit message to say we're enabling GL_KHR_robustness, >> not just turning on GL_CONTEXT_LOST. >> >> docs/GL3.txt | 2 +- >> docs/relnotes/11.3.0.html | 1 + >> src/mapi/glapi/gen/KHR_robustness.xml | 66 + >> src/mapi/glapi/gen/KHR_robustness_es.xml | 63 >> src/mapi/glapi/gen/Makefile.am| 2 + >> src/mapi/glapi/gen/es_EXT.xml | 2 + >> src/mapi/glapi/gen/gl_API.xml | 3 + >> src/mesa/drivers/dri/i965/brw_context.h | 2 + >> src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ >> src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + >> src/mesa/drivers/dri/i965/intel_extensions.c | 1 + >> src/mesa/main/context.c | 1 + >> src/mesa/main/context.h | 2 + >> src/mesa/main/extensions_table.h | 1 + >> src/mesa/main/getstring.c | 82 >> ++- >> src/mesa/main/mtypes.h| 7 ++- >> src/mesa/main/tests/dispatch_sanity.cpp | 15 - >> 17 files changed, 269 insertions(+), 4 deletions(-) >> create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml >> create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml >> >> diff --git a/docs/GL3.txt b/docs/GL3.txt >> index b5f03af..21ab46a 100644 >> --- a/docs/GL3.txt >> +++ b/docs/GL3.txt >> @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: >>GL_ARB_shader_texture_image_samples DONE (i965, nv50, >> nvc0, r600, radeonsi) >>GL_ARB_texture_barrierDONE (i965, nv50, >> nvc0, r600, radeonsi) >>GL_KHR_context_flush_control DONE (all - but >> needs GLX/EGL extension to be useful) >> - GL_KHR_robustness not started (90% >> done with the ARB variant) >> + GL_KHR_robustness DONE (i965) >>GL_EXT_shader_integer_mix DONE (all drivers >> that support GLSL) >> >> These are the extensions cherry-picked to make GLES 3.1 >> diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html >> index 5871ec8..d5bb292 100644 >> --- a/docs/relnotes/11.3.0.html >> +++ b/docs/relnotes/11.3.0.html >> @@ -59,6 +59,7 @@ Note: some of the new features are only available with >> certain drivers. >> GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe >> GL_ATI_fragment_shader on all Gallium drivers >> GL_EXT_base_instance on all drivers that support >> GL_ARB_base_instance >> +GL_KHR_robustness on i965 >> GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all >> drivers that support GL_ARB_draw_buffers_blend >> GL_OES_sample_shading on i965, nvc0, r600, radeonsi >> GL_OES_sample_variables on i965, nvc0, r600, radeonsi >> diff --git a/src/mapi/glapi/gen/KHR_robustness.xml >> b/src/mapi/glapi/gen/KHR_robustness.xml >> new file mode 100644 >> index 000..56bcfcc >> --- /dev/null >> +++ b/src/mapi/glapi/gen/KHR_robustness.xml >> @@ -0,0 +1,66 @@ >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> +> alias="GetGraphicsResetStatusARB"> >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml >> b/src/mapi/glapi/gen/KHR_robustness_es.xml >> new file mode 100644 >> index 000..84f6fd2 >> --- /dev/null >> +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml >> @@ -0,0 +1,63 @@ >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> +> value="0x0004"/> >> + >> + >> + >> +> + alias="GetGraphicsResetStatusARB" es2="2.0"> >> +
Re: [Mesa-dev] [PATCH 00/29] Make more use of bitmasks
Hi Brian, On Tuesday, May 24, 2016 11:29:56 Brian Paul wrote: > On 05/24/2016 12:41 AM, mathias.froehl...@gmx.net wrote: > > From: Mathias Fröhlich > > > > Hi all, > > > > following a series with performance improvements > > for cpu/draw bound applications. This part makes > > more use of the bitmask/ffs technique for iterating > > a set of enabled items. The gains are not huge > > but they are noticable for some of my favourite > > workloads. > > > > Please review! > > Overall looks good to me (though, see Roland's comment). I like the > clean-ups. > > Reviewed-by: Brian Paul > > However, in gallium we have a u_bit_scan() helper function for looping > over bitmasks. I wonder if we should use something like that in Mesa > too. What do you think? > Thanks! I was not aware of u_bit_scan but I like the way it is done. Even though, can we leave this series as is and do something like that on top? Mathias___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 01/29] mesa: Add gl_point_attrib::CoordReplaceBits bitfield.
On Tuesday, May 24, 2016 17:42:17 Roland Scheidegger wrote:
> Am 24.05.2016 um 08:41 schrieb mathias.froehl...@gmx.net:
> > From: Mathias Fröhlich
> >
> > The aim is to replace the CoordReplace array by
> > a bitfield. Until all drivers are converted,
> > establish the bitfield in paralell to the
> > CoordReplace array.
> >
> > Signed-off-by: Mathias Fröhlich
> > ---
> > src/mesa/main/attrib.c| 2 +-
> > src/mesa/main/ffvertex_prog.c | 2 +-
> > src/mesa/main/mtypes.h| 1 +
> > src/mesa/main/points.c| 1 +
> > src/mesa/main/texenv.c| 34 ++
> > 5 files changed, 26 insertions(+), 14 deletions(-)
> >
> > diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c
> > index 61f7036..6f39cb0 100644
> > --- a/src/mesa/main/attrib.c
> > +++ b/src/mesa/main/attrib.c
> > @@ -1247,7 +1247,7 @@ _mesa_PopAttrib(void)
> >GLuint u;
> >for (u = 0; u < ctx->Const.MaxTextureUnits; u++) {
> > _mesa_TexEnvi(GL_POINT_SPRITE_NV, GL_COORD_REPLACE_NV,
> > - (GLint) point->CoordReplace[u]);
> > + !!(point->CoordReplaceBits & (1u <<
> > u)));
> >}
> >_mesa_set_enable(ctx,
> > GL_POINT_SPRITE_NV,point->PointSprite);
> >if (ctx->Extensions.NV_point_sprite)
> > diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c
> > index d72bc71..adf71dc 100644
> > --- a/src/mesa/main/ffvertex_prog.c
> > +++ b/src/mesa/main/ffvertex_prog.c
> > @@ -243,7 +243,7 @@ static void make_state_key( struct gl_context *ctx,
> > struct state_key *key )
> > key->unit[i].texunit_really_enabled = 1;
> >
> >if (ctx->Point.PointSprite)
> > -if (ctx->Point.CoordReplace[i])
> > +if (ctx->Point.CoordReplaceBits & (1u << i))
> > key->unit[i].coord_replace = 1;
> >
> >if (ctx->Texture._TexMatEnabled & ENABLE_TEXMAT(i))
> > diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
> > index f6c6d97..e714239 100644
> > --- a/src/mesa/main/mtypes.h
> > +++ b/src/mesa/main/mtypes.h
> > @@ -757,6 +757,7 @@ struct gl_point_attrib
> > GLboolean _Attenuated; /**< True if Params != [1, 0, 0] */
> > GLboolean PointSprite; /**< GL_NV/ARB_point_sprite */
> > GLboolean CoordReplace[MAX_TEXTURE_COORD_UNITS]; /**<
> > GL_ARB_point_sprite*/
> > + GLbitfield CoordReplaceBits; /**< GL_ARB_point_sprite*/
> > GLenum SpriteRMode; /**< GL_NV_point_sprite (only!) */
> > GLenum SpriteOrigin;/**< GL_ARB_point_sprite */
> > };
> > diff --git a/src/mesa/main/points.c b/src/mesa/main/points.c
> > index c2f2b63..3fbd5d3 100644
> > --- a/src/mesa/main/points.c
> > +++ b/src/mesa/main/points.c
> > @@ -256,4 +256,5 @@ _mesa_init_point(struct gl_context *ctx)
> > for (i = 0; i < ARRAY_SIZE(ctx->Point.CoordReplace); i++) {
> >ctx->Point.CoordReplace[i] = GL_FALSE; /* GL_ARB/NV_point_sprite */
> > }
> > + ctx->Point.CoordReplaceBits = 0; /* GL_ARB/NV_point_sprite */
> > }
> > diff --git a/src/mesa/main/texenv.c b/src/mesa/main/texenv.c
> > index 93c6806..0556b75 100644
> > --- a/src/mesa/main/texenv.c
> > +++ b/src/mesa/main/texenv.c
> > @@ -460,20 +460,24 @@ _mesa_TexEnvfv( GLenum target, GLenum pname, const
> > GLfloat *param )
> > return;
> >}
> >if (pname == GL_COORD_REPLACE_NV) {
> > - if (iparam0 == GL_TRUE || iparam0 == GL_FALSE) {
> > -/* It's kind of weird to set point state via glTexEnv,
> > - * but that's what the spec calls for.
> > - */
> > -const GLboolean state = (GLboolean) iparam0;
> > -if (ctx->Point.CoordReplace[ctx->Texture.CurrentUnit] == state)
> > + /* It's kind of weird to set point state via glTexEnv,
> > + * but that's what the spec calls for.
> > + */
> > + if (iparam0 == GL_TRUE) {
> > +if (ctx->Point.CoordReplaceBits & (1u <<
> > ctx->Texture.CurrentUnit))
> > return;
> > -FLUSH_VERTICES(ctx, _NEW_POINT);
> > -ctx->Point.CoordReplace[ctx->Texture.CurrentUnit] = state;
> > - }
> > - else {
> > +ctx->Point.CoordReplaceBits |= (1u <<
> > ctx->Texture.CurrentUnit);
> > +ctx->Point.CoordReplace[ctx->Texture.CurrentUnit] = GL_TRUE;
> > + } else if (iparam0 == GL_FALSE) {
> > +if (~(ctx->Point.CoordReplaceBits) & (1u <<
> > ctx->Texture.CurrentUnit))
> > + return;
> > +ctx->Point.CoordReplaceBits &= (1u <<
> > ctx->Texture.CurrentUnit);
> That probably should be &= ~(1u << ctx->Texture.CurrentUnit);
Sure! Good catch! Thanks!
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Re: [Mesa-dev] [PATCH] gallium/radeon: add the kernel version into the renderer string
On 25.05.2016 09:09, Mike Lothian wrote: > Do you need the DRM version number if you'll be displaying the kernel > version anyway? Yes, because the DRM version depends on the kernel driver being used. The patch is Reviewed-by: Michel Dänzer -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v3] mesa: Enable GL_KHR_robustness
On Tue, May 24, 2016 at 10:41 PM, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry > points that we already implement. This patch adds a new dispatch > table that returns GL_CONTEXT_LOST from all entry points and > implements the GL_LOSE_CONTEXT_ON_RESET by setting that table when we > learn that we've lost the context. > > With the GL_CONTEXT_LOST reporting in place and dispatch for the new > entry points we can turn on GL_KHR_robustness. > > Signed-off-by: Kristian Høgsberg Kristensen > Reviewed-by: Ian Romanick > > --- > > v3: Only advertise for GLES2.0+, fix typo and dispatch_sanity > issue. Reword commit message to say we're enabling GL_KHR_robustness, > not just turning on GL_CONTEXT_LOST. > > docs/GL3.txt | 2 +- > docs/relnotes/11.3.0.html | 1 + > src/mapi/glapi/gen/KHR_robustness.xml | 66 + > src/mapi/glapi/gen/KHR_robustness_es.xml | 63 > src/mapi/glapi/gen/Makefile.am| 2 + > src/mapi/glapi/gen/es_EXT.xml | 2 + > src/mapi/glapi/gen/gl_API.xml | 3 + > src/mesa/drivers/dri/i965/brw_context.h | 2 + > src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + > src/mesa/drivers/dri/i965/intel_extensions.c | 1 + > src/mesa/main/context.c | 1 + > src/mesa/main/context.h | 2 + > src/mesa/main/extensions_table.h | 1 + > src/mesa/main/getstring.c | 82 > ++- > src/mesa/main/mtypes.h| 7 ++- > src/mesa/main/tests/dispatch_sanity.cpp | 15 - > 17 files changed, 269 insertions(+), 4 deletions(-) > create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml > create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index b5f03af..21ab46a 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: >GL_ARB_shader_texture_image_samples DONE (i965, nv50, > nvc0, r600, radeonsi) >GL_ARB_texture_barrierDONE (i965, nv50, > nvc0, r600, radeonsi) >GL_KHR_context_flush_control DONE (all - but > needs GLX/EGL extension to be useful) > - GL_KHR_robustness not started (90% > done with the ARB variant) > + GL_KHR_robustness DONE (i965) >GL_EXT_shader_integer_mix DONE (all drivers > that support GLSL) > > These are the extensions cherry-picked to make GLES 3.1 > diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html > index 5871ec8..d5bb292 100644 > --- a/docs/relnotes/11.3.0.html > +++ b/docs/relnotes/11.3.0.html > @@ -59,6 +59,7 @@ Note: some of the new features are only available with > certain drivers. > GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe > GL_ATI_fragment_shader on all Gallium drivers > GL_EXT_base_instance on all drivers that support > GL_ARB_base_instance > +GL_KHR_robustness on i965 > GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all > drivers that support GL_ARB_draw_buffers_blend > GL_OES_sample_shading on i965, nvc0, r600, radeonsi > GL_OES_sample_variables on i965, nvc0, r600, radeonsi > diff --git a/src/mapi/glapi/gen/KHR_robustness.xml > b/src/mapi/glapi/gen/KHR_robustness.xml > new file mode 100644 > index 000..56bcfcc > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness.xml > @@ -0,0 +1,66 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + alias="GetGraphicsResetStatusARB"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml > b/src/mapi/glapi/gen/KHR_robustness_es.xml > new file mode 100644 > index 000..84f6fd2 > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml > @@ -0,0 +1,63 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + value="0x0004"/> > + > + > + > + + alias="GetGraphicsResetStatusARB" es2="2.0"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > +
[Mesa-dev] [PATCH 11/12] i965: enable ARB_enhanced_layouts for gen8+
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index feea6ca..5d831e5 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -379,6 +379,7 @@ intelInitExtensions(struct gl_context *ctx)
}
if (brw->gen >= 8) {
+ ctx->Extensions.ARB_enhanced_layouts = true;
ctx->Extensions.ARB_shader_precision = true;
ctx->Extensions.ARB_stencil_texturing = true;
ctx->Extensions.ARB_texture_stencil8 = true;
--
2.5.5
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[Mesa-dev] [PATCH 09/12] i965: add indirect packing support for tcs and tes
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 51da3bd..a19ece7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2399,8 +2399,19 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
const fs_reg srcs[] = { icp_handle, indirect_offset };
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
-
-inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
payload);
+if (first_component != 0) {
+ unsigned read_components = num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
+ payload);
+ for (unsigned i = 0; i < num_components; i++) {
+ bld.MOV(offset(dst, bld, i),
+ offset(tmp, bld, i + first_component));
+ }
+} else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst,
+ payload);
+}
inst->offset = imm_offset;
inst->base_mrf = -1;
inst->mlen = 2;
@@ -2870,11 +2881,25 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld,
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
- inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest, payload);
+ if (first_component != 0) {
+unsigned read_components =
+instr->num_components + first_component;
+fs_reg tmp = bld.vgrf(dest.type, read_components);
+inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
+payload);
+inst->regs_written = read_components;
+for (unsigned i = 0; i < instr->num_components; i++) {
+ bld.MOV(offset(dest, bld, i),
+ offset(tmp, bld, i + first_component));
+}
+ } else {
+inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest,
+payload);
+inst->regs_written = instr->num_components;
+ }
inst->mlen = 2;
inst->offset = imm_offset;
inst->base_mrf = -1;
- inst->regs_written = instr->num_components;
}
break;
}
--
2.5.5
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[Mesa-dev] [PATCH 10/12] i965: add indirect packing support to gs load inputs
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a19ece7..16fd7d6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2126,14 +2126,24 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
} else {
/* Indirect indexing - use per-slot offsets as well. */
const fs_reg srcs[] = { icp_handle, get_nir_src(offset_src) };
+ unsigned read_components = num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
-
- inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
+ if (first_component != 0) {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp, payload);
+ inst->regs_written = read_components;
+ for (unsigned i = 0; i < num_components; i++) {
+bld.MOV(offset(dst, bld, i),
+offset(tmp, bld, i + first_component));
+ }
+ } else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dst, payload);
+ inst->regs_written = num_components;
+ }
inst->offset = base_offset;
inst->base_mrf = -1;
inst->mlen = 2;
- inst->regs_written = num_components;
}
if (is_point_size) {
--
2.5.5
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[Mesa-dev] [PATCH 01/12] nir: add new intrinsic field for storing component offset
This offset is used for packing.
---
src/compiler/nir/nir.h| 6 ++
src/compiler/nir/nir_intrinsics.h | 8
src/compiler/nir/nir_lower_io.c | 8
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 78913d3..7ddad73 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -987,6 +987,11 @@ typedef enum {
*/
NIR_INTRINSIC_BINDING = 7,
+ /**
+* Component offset.
+*/
+ NIR_INTRINSIC_COMPONENT = 8,
+
NIR_INTRINSIC_NUM_INDEX_FLAGS,
} nir_intrinsic_index_flag;
@@ -1053,6 +1058,7 @@ INTRINSIC_IDX_ACCESSORS(ucp_id, UCP_ID, unsigned)
INTRINSIC_IDX_ACCESSORS(range, RANGE, unsigned)
INTRINSIC_IDX_ACCESSORS(desc_set, DESC_SET, unsigned)
INTRINSIC_IDX_ACCESSORS(binding, BINDING, unsigned)
+INTRINSIC_IDX_ACCESSORS(component, COMPONENT, unsigned)
/**
* \group texture information
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index bd00fbb..648932d 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -334,9 +334,9 @@ LOAD(uniform, 1, 2, BASE, RANGE, xx,
NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC
/* src[] = { buffer_index, offset }. No const_index */
LOAD(ubo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
/* src[] = { offset }. const_index[] = { base } */
-LOAD(input, 1, 1, BASE, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
+LOAD(input, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
/* src[] = { vertex, offset }. const_index[] = { base } */
-LOAD(per_vertex_input, 2, 1, BASE, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE |
NIR_INTRINSIC_CAN_REORDER)
+LOAD(per_vertex_input, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE
| NIR_INTRINSIC_CAN_REORDER)
/* src[] = { buffer_index, offset }. No const_index */
LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
/* src[] = { offset }. const_index[] = { base } */
@@ -360,9 +360,9 @@ LOAD(push_constant, 1, 2, BASE, RANGE, xx,
INTRINSIC(store_##name, srcs, ARR(0, 1, 1, 1), false, 0, 0, num_indices,
idx0, idx1, idx2, flags)
/* src[] = { value, offset }. const_index[] = { base, write_mask } */
-STORE(output, 2, 2, BASE, WRMASK, xx, 0)
+STORE(output, 2, 2, BASE, WRMASK, COMPONENT, 0)
/* src[] = { value, vertex, offset }. const_index[] = { base, write_mask } */
-STORE(per_vertex_output, 3, 2, BASE, WRMASK, xx, 0)
+STORE(per_vertex_output, 3, 2, BASE, WRMASK, COMPONENT, 0)
/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
STORE(ssbo, 3, 1, WRMASK, xx, xx, 0)
/* src[] = { value, offset }. const_index[] = { base, write_mask } */
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index a839924..0d6d8e4 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -274,6 +274,10 @@ nir_lower_io_block(nir_block *block,
nir_intrinsic_set_base(load,
intrin->variables[0]->var->data.driver_location);
+ if (mode == nir_var_shader_in) {
+nir_intrinsic_set_component(load,
+ intrin->variables[0]->var->data.location_frac);
+ }
if (load->intrinsic == nir_intrinsic_load_uniform) {
nir_intrinsic_set_range(load,
@@ -322,6 +326,10 @@ nir_lower_io_block(nir_block *block,
nir_intrinsic_set_base(store,
intrin->variables[0]->var->data.driver_location);
+ if (mode == nir_var_shader_out) {
+nir_intrinsic_set_component(store,
+ intrin->variables[0]->var->data.location_frac);
+ }
nir_intrinsic_set_write_mask(store, nir_intrinsic_write_mask(intrin));
if (per_vertex)
--
2.5.5
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[Mesa-dev] [PATCH 12/12] docs: mark ARB_enhanced_layouts as DONE for i965
--- docs/GL3.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 2dff3cd..edc04a1 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -193,11 +193,11 @@ GL 4.4, GLSL 4.40: GL_MAX_VERTEX_ATTRIB_STRIDE DONE (all drivers) GL_ARB_buffer_storage DONE (i965, nv50, nvc0, r600, radeonsi) GL_ARB_clear_texture DONE (i965, nv50, nvc0) - GL_ARB_enhanced_layouts in progress (Timothy) + GL_ARB_enhanced_layouts DONE (i965) - compile-time constant expressions DONE - explicit byte offsets for blocksDONE - forced alignment within blocks DONE - - specified vec4-slot component numbers in progress + - specified vec4-slot component numbers DONE (i965) - specified transform/feedback layout DONE - input/output block locationsDONE GL_ARB_multi_bind DONE (all drivers) -- 2.5.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 07/12] i965: add component packing support for tcs
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index e0d88c6..51da3bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2651,6 +2651,9 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
fs_reg tmp =
fs_reg(VGRF, alloc.allocate(2 * iter_components), value.type);
+ unsigned first_component = nir_intrinsic_component(instr);
+ mask = mask << first_component;
+
for (unsigned iter = 0; iter < num_iterations; iter++) {
if (!is_64bit && mask != WRITEMASK_XYZW) {
srcs[header_regs++] = brw_imm_ud(mask << 16);
@@ -2688,11 +2691,12 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld,
}
for (unsigned i = 0; i < iter_components; i++) {
-if (!(mask & (1 << i)))
+if (!(mask & (1 << (i + first_component
continue;
if (!is_64bit) {
- srcs[header_regs + i] = offset(value, bld, BRW_GET_SWZ(swiz,
i));
+ srcs[header_regs + i + first_component] =
+ offset(value, bld, BRW_GET_SWZ(swiz, i));
} else {
/* We need to shuffle the 64-bit data to match the layout
* expected by our 32-bit URB write messages. We use a temporary
@@ -2715,7 +2719,8 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
}
unsigned mlen =
-header_regs + (is_64bit ? 2 * iter_components : iter_components);
+header_regs + (is_64bit ? 2 * iter_components : iter_components) +
+first_component;
fs_reg payload =
bld.vgrf(BRW_REGISTER_TYPE_UD, mlen);
bld.LOAD_PAYLOAD(payload, srcs, mlen, header_regs);
--
2.5.5
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[Mesa-dev] [PATCH 08/12] i965: add support for packing arrays
Here we add a new param to the type_size functions in order to pass
in the size of a varying once packing is taken into account.
---
src/compiler/nir/nir.h | 6 +++--
src/compiler/nir/nir_lower_io.c| 35 +-
src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++--
src/mesa/drivers/dri/i965/brw_fs.cpp | 23 ++---
src/mesa/drivers/dri/i965/brw_nir.c| 22
src/mesa/drivers/dri/i965/brw_shader.h | 6 +++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 7 ++
src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
src/mesa/state_tracker/st_glsl_types.cpp | 3 ++-
src/mesa/state_tracker/st_glsl_types.h | 2 +-
11 files changed, 78 insertions(+), 36 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index e06c4d5..39887cc 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2316,11 +2316,13 @@ void nir_shader_gather_info(nir_shader *shader,
nir_function_impl *entrypoint);
void nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
unsigned base_offset,
- int (*type_size)(const struct glsl_type *));
+ int (*type_size)(const struct glsl_type *,
+ unsigned
num_packed_components));
void nir_lower_io(nir_shader *shader,
nir_variable_mode modes,
- int (*type_size)(const struct glsl_type *));
+ int (*type_size)(const struct glsl_type *,
+ unsigned num_packed_components));
nir_src *nir_get_io_offset_src(nir_intrinsic_instr *instr);
nir_src *nir_get_io_vertex_index_src(nir_intrinsic_instr *instr);
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 2079004..c3c0e2e 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -37,14 +37,16 @@
struct lower_io_state {
nir_builder builder;
void *mem_ctx;
- int (*type_size)(const struct glsl_type *type);
+ int (*type_size)(const struct glsl_type *type,
+unsigned num_packed_components);
nir_variable_mode modes;
};
void
nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
unsigned base_offset,
- int (*type_size)(const struct glsl_type *))
+ int (*type_size)(const struct glsl_type *,
+ unsigned num_packed_components))
{
unsigned location = 0;
@@ -80,7 +82,7 @@ nir_assign_var_locations(struct exec_list *var_list, unsigned
*size,
} else {
var->data.driver_location = location;
}
- location += type_size(var->type);
+ location += type_size(var->type, var->data.num_packed_components);
}
*size = location;
@@ -112,7 +114,9 @@ is_per_vertex_output(struct lower_io_state *state,
nir_variable *var)
static nir_ssa_def *
get_io_offset(nir_builder *b, nir_deref_var *deref,
nir_ssa_def **vertex_index,
- int (*type_size)(const struct glsl_type *))
+ int (*type_size)(const struct glsl_type *,
+ unsigned num_packed_components),
+ unsigned num_packed_components)
{
nir_deref *tail = &deref->deref;
@@ -140,7 +144,7 @@ get_io_offset(nir_builder *b, nir_deref_var *deref,
if (tail->deref_type == nir_deref_type_array) {
nir_deref_array *deref_array = nir_deref_as_array(tail);
- unsigned size = type_size(tail->type);
+ unsigned size = type_size(tail->type, num_packed_components);
offset = nir_iadd(b, offset,
nir_imm_int(b, size * deref_array->base_offset));
@@ -157,7 +161,8 @@ get_io_offset(nir_builder *b, nir_deref_var *deref,
unsigned field_offset = 0;
for (unsigned i = 0; i < deref_struct->index; i++) {
-field_offset += type_size(glsl_get_struct_field(parent_type, i));
+field_offset +=
+ type_size(glsl_get_struct_field(parent_type, i), 0);
}
offset = nir_iadd(b, offset, nir_imm_int(b, field_offset));
}
@@ -288,7 +293,9 @@ nir_lower_io_block(nir_block *block,
offset = get_io_offset(b, intrin->variables[0],
per_vertex ? &vertex_index : NULL,
-state->type_size);
+state->type_size,
+intrin->variables[0]->var->
+ data.num_packed_components);
nir_intrinsic_instr *load =
nir_intrinsic_instr_create(state->mem_ctx,
@@ -304,7 +311,7 @@ nir_lower_io_block(nir_block *block,
if (load->intrinsic =
[Mesa-dev] [PATCH 04/12] i965: enable component packing for vs and fs
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 17 +++--
src/mesa/drivers/dri/i965/brw_fs.h | 5 +++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 29 -
3 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 847a6d3..c24813f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1129,7 +1129,8 @@ fs_visitor::emit_general_interpolation(fs_reg *attr,
const char *name,
const glsl_type *type,
glsl_interp_qualifier
interpolation_mode,
int *location, bool mod_centroid,
- bool mod_sample)
+ bool mod_sample,
+ unsigned num_packed_components)
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
@@ -1151,22 +1152,26 @@ fs_visitor::emit_general_interpolation(fs_reg *attr,
const char *name,
for (unsigned i = 0; i < length; i++) {
emit_general_interpolation(attr, name, elem_type, interpolation_mode,
-location, mod_centroid, mod_sample);
+location, mod_centroid, mod_sample,
+num_packed_components);
}
} else if (type->is_record()) {
for (unsigned i = 0; i < type->length; i++) {
const glsl_type *field_type = type->fields.structure[i].type;
emit_general_interpolation(attr, name, field_type, interpolation_mode,
-location, mod_centroid, mod_sample);
+location, mod_centroid, mod_sample,
+num_packed_components);
}
} else {
assert(type->is_scalar() || type->is_vector());
+ unsigned num_components = num_packed_components ?
+ num_packed_components : type->vector_elements;
if (prog_data->urb_setup[*location] == -1) {
/* If there's no incoming setup data for this slot, don't
* emit interpolation for it.
*/
- *attr = offset(*attr, bld, type->vector_elements);
+ *attr = offset(*attr, bld, num_components);
(*location)++;
return;
}
@@ -1178,7 +1183,7 @@ fs_visitor::emit_general_interpolation(fs_reg *attr,
const char *name,
* handed us defined values in only the constant offset
* field of the setup reg.
*/
- for (unsigned int i = 0; i < type->vector_elements; i++) {
+ for (unsigned int i = 0; i < num_components; i++) {
struct brw_reg interp = interp_reg(*location, i);
interp = suboffset(interp, 3);
interp.type = attr->type;
@@ -1187,7 +1192,7 @@ fs_visitor::emit_general_interpolation(fs_reg *attr,
const char *name,
}
} else {
/* Smooth/noperspective interpolation case. */
- for (unsigned int i = 0; i < type->vector_elements; i++) {
+ for (unsigned int i = 0; i < num_components; i++) {
struct brw_reg interp = interp_reg(*location, i);
if (devinfo->needs_unlit_centroid_workaround && mod_centroid) {
/* Get the pixel/sample mask into f0 so that we know
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 062fcd5..d5d7a77 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -195,7 +195,7 @@ public:
const glsl_type *type,
glsl_interp_qualifier interpolation_mode,
int *location, bool mod_centroid,
- bool mod_sample);
+ bool mod_sample, unsigned num_components);
fs_reg *emit_vs_system_value(int location);
void emit_interpolation_setup_gen4();
void emit_interpolation_setup_gen6();
@@ -214,7 +214,8 @@ public:
void emit_nir_code();
void nir_setup_inputs();
void nir_setup_single_output_varying(fs_reg *reg, const glsl_type *type,
-unsigned *location);
+unsigned *location,
+unsigned num_components);
void nir_setup_outputs();
void nir_setup_uniforms();
void nir_emit_system_values();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index cc30838..5180e01 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -78,7 +78,8 @@ fs_visitor::nir_setup_inputs()
emit_general_interpolation(&input, var->name, var->type,
[Mesa-dev] [PATCH 03/12] glsl/nir: add new num_packed_components field
This will be used to store the total number of components used at this location
when packing via ARB_enhanced_layouts.
---
src/compiler/glsl/ir.h | 5 +++
src/compiler/glsl/link_varyings.cpp | 74 -
src/compiler/glsl/linker.cpp| 2 +
src/compiler/glsl/linker.h | 4 ++
src/compiler/nir/glsl_to_nir.cpp| 1 +
src/compiler/nir/nir.h | 5 +++
6 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/ir.h b/src/compiler/glsl/ir.h
index d52dbf8..6236245 100644
--- a/src/compiler/glsl/ir.h
+++ b/src/compiler/glsl/ir.h
@@ -759,6 +759,11 @@ public:
unsigned location_frac:2;
/**
+ * The total number of components packed into this location.
+ */
+ unsigned num_packed_components:3;
+
+ /**
* Layout of the matrix. Uses glsl_matrix_layout values.
*/
unsigned matrix_layout:2;
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index dd5c9cc..fcd285d 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -1940,6 +1940,70 @@ reserved_varying_slot(struct gl_shader *stage,
ir_variable_mode io_mode)
return slots;
}
+void
+set_num_packed_components(struct gl_shader *shader, ir_variable_mode io_mode,
+ unsigned base_offset)
+{
+ /* Find the max number of components used at this location */
+ unsigned num_components[MAX_VARYINGS_INCL_PATCH] = { 0 };
+
+ foreach_in_list(ir_instruction, node, shader->ir) {
+ ir_variable *const var = node->as_variable();
+
+ if (var == NULL || var->data.mode != io_mode ||
+ !var->data.explicit_location)
+ continue;
+
+ int idx = var->data.location - base_offset;
+ if (idx < 0 || idx >= MAX_VARYINGS_INCL_PATCH ||
+ var->type->without_array()->is_record() ||
+ var->type->without_array()->is_matrix())
+ continue;
+
+ if (var->type->is_array()) {
+ const glsl_type *type = get_varying_type(var, shader->Stage);
+ unsigned array_components = type->without_array()->vector_elements +
+var->data.location_frac;
+ assert(type->arrays_of_arrays_size() + idx <=
+ARRAY_SIZE(num_components));
+ for (unsigned i = idx; i < type->arrays_of_arrays_size(); i++) {
+num_components[i] = MAX2(array_components, num_components[i]);
+ }
+ } else {
+ unsigned comps = var->type->vector_elements +
+var->data.location_frac;
+ num_components[idx] = MAX2(comps, num_components[idx]);
+ }
+ }
+
+ foreach_in_list(ir_instruction, node, shader->ir) {
+ ir_variable *const var = node->as_variable();
+
+ if (var == NULL || var->data.mode != io_mode ||
+ !var->data.explicit_location)
+ continue;
+
+ int idx = var->data.location - base_offset;
+ if (idx < 0 || idx >= MAX_VARYINGS_INCL_PATCH ||
+ var->type->without_array()->is_record() ||
+ var->type->without_array()->is_matrix())
+ continue;
+
+ /* For arrays we need to check all elements in order to find the max
+ * number of components used.
+ */
+ unsigned c = 0;
+ if (var->type->is_array()) {
+ const glsl_type *type = get_varying_type(var, shader->Stage);
+ for (unsigned i = idx; i < type->arrays_of_arrays_size(); i++) {
+c = MAX2(c, num_components[i]);
+ }
+ } else {
+ c = num_components[idx];
+ }
+ var->data.num_packed_components = c;
+ }
+}
/**
* Assign locations for all variables that are produced in one pipeline stage
@@ -2054,11 +2118,17 @@ assign_varying_locations(struct gl_context *ctx,
* 4. Mark input variables in the consumer that do not have locations as
*not being inputs. This lets the optimizer eliminate them.
*/
- if (consumer)
+ if (consumer) {
canonicalize_shader_io(consumer->ir, ir_var_shader_in);
+ set_num_packed_components(consumer, ir_var_shader_in,
+VARYING_SLOT_VAR0);
+ }
- if (producer)
+ if (producer) {
canonicalize_shader_io(producer->ir, ir_var_shader_out);
+ set_num_packed_components(producer, ir_var_shader_out,
+VARYING_SLOT_VAR0);
+ }
if (consumer)
linker::populate_consumer_input_sets(mem_ctx, consumer->ir,
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 5c0e4b6..e388b26 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -2587,6 +2587,8 @@ assign_attribute_or_color_locations(gl_shader_program
*prog,
(target_index == MESA_SHADER_VERTEX)
? ir_var_shader_in : ir_var_shader_out;
+ set_num_packed_components(sh, direction, generic_base);
+
/* Temporary storage for the set of attributes that need locations assigned.
*/
diff
[Mesa-dev] [PATCH 06/12] i965: add component packing support for tes
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++-
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ce61898..e0d88c6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2376,10 +2376,21 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld,
dst = tmp;
}
+ unsigned first_component = nir_intrinsic_component(instr);
for (unsigned iter = 0; iter < num_iterations; iter++) {
if (indirect_offset.file == BAD_FILE) {
/* Constant indexing - use global offset. */
-inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
+if (first_component != 0) {
+ unsigned read_components = num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
+ for (unsigned i = 0; i < num_components; i++) {
+ bld.MOV(offset(dst, bld, i),
+ offset(tmp, bld, i + first_component));
+ }
+} else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
+}
inst->offset = imm_offset;
inst->mlen = 1;
inst->base_mrf = -1;
@@ -2394,7 +2405,8 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld,
inst->base_mrf = -1;
inst->mlen = 2;
}
- inst->regs_written = num_components * type_sz(dst.type) / 4;
+ inst->regs_written =
+(num_components * type_sz(dst.type) / 4) + first_component;
/* If we are reading 64-bit data using 32-bit read messages we need
* build proper 64-bit data elements by shuffling the low and high
@@ -2798,6 +2810,7 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
case nir_intrinsic_load_per_vertex_input: {
fs_reg indirect_offset = get_indirect_offset(instr);
unsigned imm_offset = instr->const_index[0];
+ unsigned first_component = nir_intrinsic_component(instr);
fs_inst *inst;
if (indirect_offset.file == BAD_FILE) {
@@ -2808,7 +2821,8 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder &bld,
if (imm_offset < max_push_slots) {
fs_reg src = fs_reg(ATTR, imm_offset / 2, dest.type);
for (int i = 0; i < instr->num_components; i++) {
- unsigned comp = 16 / type_sz(dest.type) * (imm_offset % 2) + i;
+ unsigned comp = 16 / type_sz(dest.type) * (imm_offset % 2) +
+ i + first_component;
bld.MOV(offset(dest, bld, i), component(src, comp));
}
tes_prog_data->base.urb_read_length =
@@ -2822,11 +2836,25 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld,
fs_reg patch_handle = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
bld.LOAD_PAYLOAD(patch_handle, srcs, ARRAY_SIZE(srcs), 0);
-inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dest, patch_handle);
+if (first_component != 0) {
+ unsigned read_components =
+ instr->num_components + first_component;
+ fs_reg tmp = bld.vgrf(dest.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp,
+ patch_handle);
+ inst->regs_written = read_components;
+ for (unsigned i = 0; i < instr->num_components; i++) {
+ bld.MOV(offset(dest, bld, i),
+ offset(tmp, bld, i + first_component));
+ }
+} else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dest,
+ patch_handle);
+ inst->regs_written = instr->num_components;
+}
inst->mlen = 1;
inst->offset = imm_offset;
inst->base_mrf = -1;
-inst->regs_written = instr->num_components;
}
} else {
/* Indirect indexing - use per-slot offsets as well. */
--
2.5.5
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[Mesa-dev] [PATCH 05/12] i965: add component packing support for gs
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 21 +
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d5d7a77..b5a4fc8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -280,7 +280,7 @@ public:
void emit_gs_thread_end();
void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
unsigned base_offset, const nir_src &offset_src,
- unsigned num_components);
+ unsigned num_components, unsigned first_component);
void emit_cs_terminate();
fs_reg *emit_cs_local_invocation_id_setup();
fs_reg *emit_cs_work_group_id_setup();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 5180e01..ce61898 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -1988,7 +1988,8 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
const nir_src &vertex_src,
unsigned base_offset,
const nir_src &offset_src,
- unsigned num_components)
+ unsigned num_components,
+ unsigned first_component)
{
struct brw_gs_prog_data *gs_prog_data = (struct brw_gs_prog_data *)
prog_data;
@@ -2106,11 +2107,22 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst,
fs_inst *inst;
if (offset_const) {
/* Constant indexing - use global offset. */
- inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
+ if (first_component != 0) {
+ unsigned read_components = num_components + first_component;
+ fs_reg tmp = bld.vgrf(dst.type, read_components);
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, tmp, icp_handle);
+ inst->regs_written = read_components;
+ for (unsigned i = 0; i < num_components; i++) {
+bld.MOV(offset(dst, bld, i),
+offset(tmp, bld, i + first_component));
+ }
+ } else {
+ inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8, dst, icp_handle);
+ inst->regs_written = num_components;
+ }
inst->offset = base_offset + offset_const->u32[0];
inst->base_mrf = -1;
inst->mlen = 1;
- inst->regs_written = num_components;
} else {
/* Indirect indexing - use per-slot offsets as well. */
const fs_reg srcs[] = { icp_handle, get_nir_src(offset_src) };
@@ -2863,7 +2875,8 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
case nir_intrinsic_load_per_vertex_input:
emit_gs_input_load(dest, instr->src[0], instr->const_index[0],
- instr->src[1], instr->num_components);
+ instr->src[1], instr->num_components,
+ nir_intrinsic_component(instr));
break;
case nir_intrinsic_emit_vertex_with_counter:
--
2.5.5
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[Mesa-dev] [PATCH 02/12] nir: use the same driver location for packed varyings
---
src/compiler/nir/nir.h| 4 ++--
src/compiler/nir/nir_lower_io.c | 25 -
src/mesa/drivers/dri/i965/brw_nir.c | 12 +++-
src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 +++
4 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 7ddad73..4dd38a7 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2309,8 +2309,8 @@ void nir_lower_io_to_temporaries(nir_shader *shader,
nir_function *entrypoint,
void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint);
-void nir_assign_var_locations(struct exec_list *var_list,
- unsigned *size,
+void nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
+ unsigned base_offset,
int (*type_size)(const struct glsl_type *));
void nir_lower_io(nir_shader *shader,
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 0d6d8e4..2079004 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -43,10 +43,18 @@ struct lower_io_state {
void
nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
+ unsigned base_offset,
int (*type_size)(const struct glsl_type *))
{
unsigned location = 0;
+ /* There are 32 regular and 32 patch varyings allowed */
+ int locations[64][2];
+ for (unsigned i = 0; i < 64; i++) {
+ for (unsigned j = 0; j < 2; j++)
+ locations[i][j] = -1;
+ }
+
nir_foreach_variable(var, var_list) {
/*
* UBO's have their own address spaces, so don't count them towards the
@@ -56,7 +64,22 @@ nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
var->interface_type != NULL)
continue;
- var->data.driver_location = location;
+ /* Make sure we give the same location to varyings packed with
+ * ARB_enhanced_layouts.
+ */
+ int idx = var->data.location - base_offset;
+ if (base_offset && idx >= 0) {
+ assert(idx < ARRAY_SIZE(locations));
+
+ if (locations[idx][var->data.index] == -1) {
+var->data.driver_location = location;
+locations[idx][var->data.index] = location;
+ } else {
+var->data.driver_location = locations[idx][var->data.index];
+ }
+ } else {
+ var->data.driver_location = location;
+ }
location += type_size(var->type);
}
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c
b/src/mesa/drivers/dri/i965/brw_nir.c
index 9274f2e..e60d398 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -285,7 +285,8 @@ brw_nir_lower_tes_inputs(nir_shader *nir, const struct
brw_vue_map *vue_map)
void
brw_nir_lower_fs_inputs(nir_shader *nir)
{
- nir_assign_var_locations(&nir->inputs, &nir->num_inputs, type_size_scalar);
+ nir_assign_var_locations(&nir->inputs, &nir->num_inputs, VARYING_SLOT_VAR0,
+type_size_scalar);
nir_lower_io(nir, nir_var_shader_in, type_size_scalar);
}
@@ -295,6 +296,7 @@ brw_nir_lower_vue_outputs(nir_shader *nir,
{
if (is_scalar) {
nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
+ VARYING_SLOT_VAR0,
type_size_vec4_times_4);
nir_lower_io(nir, nir_var_shader_out, type_size_vec4_times_4);
} else {
@@ -333,7 +335,7 @@ void
brw_nir_lower_fs_outputs(nir_shader *nir)
{
nir_assign_var_locations(&nir->outputs, &nir->num_outputs,
-type_size_scalar);
+FRAG_RESULT_DATA0, type_size_scalar);
nir_lower_io(nir, nir_var_shader_out, type_size_scalar);
}
@@ -353,11 +355,11 @@ static void
brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
{
if (is_scalar) {
- nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
+ nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, 0,
type_size_scalar_bytes);
nir_lower_io(nir, nir_var_uniform, type_size_scalar_bytes);
} else {
- nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms,
+ nir_assign_var_locations(&nir->uniforms, &nir->num_uniforms, 0,
type_size_vec4_bytes);
nir_lower_io(nir, nir_var_uniform, type_size_vec4_bytes);
}
@@ -366,7 +368,7 @@ brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
void
brw_nir_lower_cs_shared(nir_shader *nir)
{
- nir_assign_var_locations(&nir->shared, &nir->num_shared,
+ nir_assign_var_locations(&nir->shared, &nir->num_shared, 0,
type_size_scalar_bytes);
nir_lower_io(nir, nir_var_shared, type_size_scalar_bytes);
}
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_
[Mesa-dev] ARB_enhanced_layouts packing support for i965 Gen8+
There are a number of packing tests already in piglit but I have a few more on the way. This series does not add support for doubles as there is currently a doubles bug with explicit locations that I've pointed out to the Igalia guys. Samuel is working on a fix for this after which I will finish up the doubles support. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] tgsi: print TGSI_PROPERTY_NEXT_SHADER value as string, not an integer
Series is
Reviewed-by: Ilia Mirkin
On Tue, May 24, 2016 at 8:43 PM, Brian Paul wrote:
> Print "GEOM" instead of "2", for example.
>
> v2: also update the text parsing code, per Ilia.
> ---
> src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++
> src/gallium/auxiliary/tgsi/tgsi_text.c | 22 ++
> 2 files changed, 25 insertions(+)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c
> b/src/gallium/auxiliary/tgsi/tgsi_dump.c
> index 0d8bd1b..d59b7ff 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
> @@ -470,6 +470,9 @@ iter_property(
>case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
> ENM(prop->u[i].Data, tgsi_fs_coord_pixel_center_names);
> break;
> + case TGSI_PROPERTY_NEXT_SHADER:
> + ENM(prop->u[i].Data, tgsi_processor_type_names);
> + break;
>default:
> SID( prop->u[i].Data );
> break;
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c
> b/src/gallium/auxiliary/tgsi/tgsi_text.c
> index ea1ee53..955d042 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_text.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
> @@ -1663,6 +1663,22 @@ parse_fs_coord_pixel_center( const char **pcur, uint
> *fs_coord_pixel_center )
> return FALSE;
> }
>
> +static boolean
> +parse_property_next_shader( const char **pcur, uint *next_shader )
> +{
> + uint i;
> +
> + for (i = 0; i < ARRAY_SIZE(tgsi_processor_type_names); i++) {
> + const char *cur = *pcur;
> +
> + if (str_match_nocase_whole( &cur, tgsi_processor_type_names[i])) {
> + *next_shader = i;
> + *pcur = cur;
> + return TRUE;
> + }
> + }
> + return FALSE;
> +}
>
> static boolean parse_property( struct translate_ctx *ctx )
> {
> @@ -1716,6 +1732,12 @@ static boolean parse_property( struct translate_ctx
> *ctx )
> return FALSE;
>}
>break;
> + case TGSI_PROPERTY_NEXT_SHADER:
> + if (!parse_property_next_shader(&ctx->cur, &values[0] )) {
> + report_error( ctx, "Unknown next shader property value." );
> + return FALSE;
> + }
> + break;
> case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
> default:
>if (!parse_uint(&ctx->cur, &values[0] )) {
> --
> 1.9.1
>
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Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On Tue, May 24, 2016 at 7:47 PM, Ilia Mirkin wrote: > > On May 24, 2016 10:25 PM, "Kristian Høgsberg" wrote: >> >> On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote: >> > Sorry to be pedantic, but you're enabling the ext for gles1.1, but the >> > new >> > entrypoint appear to only apply to gles2. I think you also want a >> > es1="1.1" >> > or something along those lines. >> >> The extension requires 2.0, so maybe we should instead only enable it for >> 2.0? > > Sure, so long as it's consistent. Cool, that's what I did in v3. Thanks for reviewing. Kristian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/draw: Use the correct buffer index for interleaved VBO sizes
On Tue, May 24, 2016 at 5:01 PM, Jason Ekstrand wrote: > The buffer_range_* arrays are indexed by buffer index not element index. Reviewed-by: Kristian Høgsberg > --- > src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c > b/src/mesa/drivers/dri/i965/brw_draw_upload.c > index 3349161..f4d1b2c 100644 > --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c > +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c > @@ -529,8 +529,10 @@ brw_prepare_vertices(struct brw_context *brw) >input->buffer = brw->vb.enabled[k]->buffer; >input->offset = glarray->Ptr - other->Ptr; > > - buffer_range_start[k] = MIN2(buffer_range_start[k], start); > - buffer_range_end[k] = MAX2(buffer_range_end[k], start + > range); > + buffer_range_start[input->buffer] = > + MIN2(buffer_range_start[input->buffer], start); > + buffer_range_end[input->buffer] = > + MAX2(buffer_range_end[input->buffer], start + range); >break; > } > } > -- > 2.5.0.400.gff86faf > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On May 24, 2016 10:25 PM, "Kristian Høgsberg" wrote: > > On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote: > > Sorry to be pedantic, but you're enabling the ext for gles1.1, but the new > > entrypoint appear to only apply to gles2. I think you also want a es1="1.1" > > or something along those lines. > > The extension requires 2.0, so maybe we should instead only enable it for 2.0? Sure, so long as it's consistent. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3] mesa: Enable GL_KHR_robustness
From: Kristian Høgsberg Kristensen GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry points that we already implement. This patch adds a new dispatch table that returns GL_CONTEXT_LOST from all entry points and implements the GL_LOSE_CONTEXT_ON_RESET by setting that table when we learn that we've lost the context. With the GL_CONTEXT_LOST reporting in place and dispatch for the new entry points we can turn on GL_KHR_robustness. Signed-off-by: Kristian Høgsberg Kristensen Reviewed-by: Ian Romanick --- v3: Only advertise for GLES2.0+, fix typo and dispatch_sanity issue. Reword commit message to say we're enabling GL_KHR_robustness, not just turning on GL_CONTEXT_LOST. docs/GL3.txt | 2 +- docs/relnotes/11.3.0.html | 1 + src/mapi/glapi/gen/KHR_robustness.xml | 66 + src/mapi/glapi/gen/KHR_robustness_es.xml | 63 src/mapi/glapi/gen/Makefile.am| 2 + src/mapi/glapi/gen/es_EXT.xml | 2 + src/mapi/glapi/gen/gl_API.xml | 3 + src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + src/mesa/main/context.c | 1 + src/mesa/main/context.h | 2 + src/mesa/main/extensions_table.h | 1 + src/mesa/main/getstring.c | 82 ++- src/mesa/main/mtypes.h| 7 ++- src/mesa/main/tests/dispatch_sanity.cpp | 15 - 17 files changed, 269 insertions(+), 4 deletions(-) create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml diff --git a/docs/GL3.txt b/docs/GL3.txt index b5f03af..21ab46a 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: GL_ARB_shader_texture_image_samples DONE (i965, nv50, nvc0, r600, radeonsi) GL_ARB_texture_barrierDONE (i965, nv50, nvc0, r600, radeonsi) GL_KHR_context_flush_control DONE (all - but needs GLX/EGL extension to be useful) - GL_KHR_robustness not started (90% done with the ARB variant) + GL_KHR_robustness DONE (i965) GL_EXT_shader_integer_mix DONE (all drivers that support GLSL) These are the extensions cherry-picked to make GLES 3.1 diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html index 5871ec8..d5bb292 100644 --- a/docs/relnotes/11.3.0.html +++ b/docs/relnotes/11.3.0.html @@ -59,6 +59,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe GL_ATI_fragment_shader on all Gallium drivers GL_EXT_base_instance on all drivers that support GL_ARB_base_instance +GL_KHR_robustness on i965 GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers that support GL_ARB_draw_buffers_blend GL_OES_sample_shading on i965, nvc0, r600, radeonsi GL_OES_sample_variables on i965, nvc0, r600, radeonsi diff --git a/src/mapi/glapi/gen/KHR_robustness.xml b/src/mapi/glapi/gen/KHR_robustness.xml new file mode 100644 index 000..56bcfcc --- /dev/null +++ b/src/mapi/glapi/gen/KHR_robustness.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml b/src/mapi/glapi/gen/KHR_robustness_es.xml new file mode 100644 index 000..84f6fd2 --- /dev/null +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am index 0759819..c511de9 100644 --- a/src/mapi/glapi/gen/Makefile.am +++ b/src/mapi/glapi/gen/Makefile.am @@ -192,6 +192,8 @@ API_XML = \ INTEL_performance_query.xml \ KHR_debug.xml \ KHR_context_flush_control.xml \ + KHR_robustness.xml \ + KHR_robustness_es.xml \ KHR_texture_compression_astc.xml \ NV_conditional_render.xml \ NV_primitive_re
Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote: > Sorry to be pedantic, but you're enabling the ext for gles1.1, but the new > entrypoint appear to only apply to gles2. I think you also want a es1="1.1" > or something along those lines. The extension requires 2.0, so maybe we should instead only enable it for 2.0? > > On May 24, 2016 8:02 PM, "Kristian Høgsberg" wrote: >> >> From: Kristian Høgsberg Kristensen >> >> As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all >> entry points when we lose a context. We do this by creating a new >> dispatch table and setting that when we learn that we've lost the >> context. >> >> With the GL_CONTEXT_LOST reporting in place we can turn on >> GL_KHR_robustness. >> >> Signed-off-by: Kristian Høgsberg Kristensen >> --- >> >> v2: Add dispatch for un-suffixed and KHR-suffixed entrypoint added by >> the extension. >> >> docs/GL3.txt | 2 +- >> docs/relnotes/11.3.0.html | 1 + >> src/mapi/glapi/gen/KHR_robustness.xml | 66 + >> src/mapi/glapi/gen/KHR_robustness_es.xml | 63 >> src/mapi/glapi/gen/Makefile.am| 2 + >> src/mapi/glapi/gen/es_EXT.xml | 2 + >> src/mapi/glapi/gen/gl_API.xml | 3 + >> src/mesa/drivers/dri/i965/brw_context.h | 2 + >> src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ >> src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + >> src/mesa/drivers/dri/i965/intel_extensions.c | 1 + >> src/mesa/main/context.c | 1 + >> src/mesa/main/context.h | 2 + >> src/mesa/main/extensions_table.h | 1 + >> src/mesa/main/getstring.c | 82 >> ++- >> src/mesa/main/mtypes.h| 7 ++- >> src/mesa/main/tests/dispatch_sanity.cpp | 12 >> 17 files changed, 267 insertions(+), 3 deletions(-) >> create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml >> create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml >> >> diff --git a/docs/GL3.txt b/docs/GL3.txt >> index b5f03af..21ab46a 100644 >> --- a/docs/GL3.txt >> +++ b/docs/GL3.txt >> @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: >>GL_ARB_shader_texture_image_samples DONE (i965, nv50, >> nvc0, r600, radeonsi) >>GL_ARB_texture_barrierDONE (i965, nv50, >> nvc0, r600, radeonsi) >>GL_KHR_context_flush_control DONE (all - but >> needs GLX/EGL extension to be useful) >> - GL_KHR_robustness not started (90% >> done with the ARB variant) >> + GL_KHR_robustness DONE (i965) >>GL_EXT_shader_integer_mix DONE (all drivers >> that support GLSL) >> >> These are the extensions cherry-picked to make GLES 3.1 >> diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html >> index 5871ec8..d5bb292 100644 >> --- a/docs/relnotes/11.3.0.html >> +++ b/docs/relnotes/11.3.0.html >> @@ -59,6 +59,7 @@ Note: some of the new features are only available with >> certain drivers. >> GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe >> GL_ATI_fragment_shader on all Gallium drivers >> GL_EXT_base_instance on all drivers that support >> GL_ARB_base_instance >> +GL_KHR_robustness on i965 >> GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all >> drivers that support GL_ARB_draw_buffers_blend >> GL_OES_sample_shading on i965, nvc0, r600, radeonsi >> GL_OES_sample_variables on i965, nvc0, r600, radeonsi >> diff --git a/src/mapi/glapi/gen/KHR_robustness.xml >> b/src/mapi/glapi/gen/KHR_robustness.xml >> new file mode 100644 >> index 000..56bcfcc >> --- /dev/null >> +++ b/src/mapi/glapi/gen/KHR_robustness.xml >> @@ -0,0 +1,66 @@ >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> +> value="0x0004"/> >> + >> + >> + >> + >> +> alias="GetGraphicsResetStatusARB"> >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> + >> diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml >> b/src/mapi/glapi/gen/KHR_robustness_es.xml >> new file mode 100644 >> index 000..ba8bdda >> --- /dev/null >> +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml >> @@ -0,0 +1,63 @@ >> + >> + >> + >> + >> + >> + >> + >> +> value="0x8253"/> >> +> value="0x8254"/> >> +> value="0x8255"/> >> + >> +> value="0x8256"> >> + >> + >> +> value="0x8252"/> >> +> value="0x8
Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On Tue, May 24, 2016 at 6:04 PM, Matt Turner wrote: > On Tue, May 24, 2016 at 4:58 PM, Kristian Høgsberg wrote: >> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c >> b/src/mesa/drivers/dri/i965/intel_extensions.c >> index feea6ca..b8d7517 100644 >> --- a/src/mesa/drivers/dri/i965/intel_extensions.c >> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c >> @@ -246,6 +246,7 @@ intelInitExtensions(struct gl_context *ctx) >> ctx->Extensions.EXT_texture_sRGB_decode = true; >> ctx->Extensions.EXT_texture_swizzle = true; >> ctx->Extensions.EXT_vertex_array_bgra = true; >> + ctx->Extensions.KHR_robustness = true; >> ctx->Extensions.AMD_seamless_cubemap_per_texture = true; >> ctx->Extensions.APPLE_object_purgeable = true; >> ctx->Extensions.ATI_separate_stencil = true; > > Same comment as before -- I'd move this between ATI_* and MESA_* I deliberately put it there - ARB and EXT comes before AMD, APPLE and ATI extension, so I concluded that we decided to list official extensions before vendor ones and put KHR_robustness with the official extensions. It'd probably be better to alphabetize this list, but lets do a different patch for that. Kristian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] egl: Additional attribute validation for eglCreatePbufferSurface
On Tue, May 17, 2016 at 06:39:02PM +0100, Plamena Manolova wrote:
> eglCreatePbufferSurface should generate an EGL_BAD_MATCH error if:
> 1: The EGL_TEXTURE_FORMAT attribute is EGL_NO_TEXTURE and EGL_TEXTURE_TARGET
> is something other than EGL_NO_TEXTURE
> 2: EGL_TEXTURE_FORMAT is something other than EGL_NO_TEXTURE and
> EGL_TEXTURE_TARGET is EGL_NO_TEXTURE.
>
> This fixes the dEQP-EGL.functional.negative_api.create_pbuffer_surface test.
>
> Signed-off-by: Plamena Manolova
> ---
> src/egl/main/eglsurface.c | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/src/egl/main/eglsurface.c b/src/egl/main/eglsurface.c
> index 2971bb0..d6b8083 100644
> --- a/src/egl/main/eglsurface.c
> +++ b/src/egl/main/eglsurface.c
> @@ -65,12 +65,14 @@ _eglClampSwapInterval(_EGLSurface *surf, EGLint interval)
> * Parse the list of surface attributes and return the proper error code.
> */
> static EGLint
> -_eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint *attrib_list)
> +_eglParseSurfaceAttribList(_EGLSurface *surf, EGLint s_type, const EGLint
> *attrib_list)
I don't think you need to add s_type, you can simply use surf->Type which is
already defined as type.
> {
> _EGLDisplay *dpy = surf->Resource.Display;
> EGLint type = surf->Type;
> EGLint texture_type = EGL_PBUFFER_BIT;
> EGLint i, err = EGL_SUCCESS;
> + EGLint tex_target = -1;
> + EGLint tex_format = -1;
>
> if (!attrib_list)
>return EGL_SUCCESS;
> @@ -186,6 +188,8 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const
> EGLint *attrib_list)
> err = EGL_BAD_ATTRIBUTE;
> break;
> }
> +
> + tex_format = val;
> switch (val) {
> case EGL_TEXTURE_RGB:
> case EGL_TEXTURE_RGBA:
> @@ -204,6 +208,8 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const
> EGLint *attrib_list)
> err = EGL_BAD_ATTRIBUTE;
> break;
> }
> +
> + tex_target = val;
> switch (val) {
> case EGL_TEXTURE_2D:
> case EGL_NO_TEXTURE:
> @@ -229,6 +235,13 @@ _eglParseSurfaceAttribList(_EGLSurface *surf, const
> EGLint *attrib_list)
> break;
>}
>
> + if (s_type == EGL_PBUFFER_BIT) {
> + if ((tex_target == EGL_NO_TEXTURE && tex_format != EGL_NO_TEXTURE)
> ||
> + (tex_format == EGL_NO_TEXTURE && tex_target != EGL_NO_TEXTURE))
> {
> +err = EGL_BAD_MATCH;
> + }
> + }
> +
lgtm. With the s_type removed:
Reviewed-by: Ben Widawsky
>if (err != EGL_SUCCESS) {
> _eglLog(_EGL_WARNING, "bad surface attribute 0x%04x", attr);
> break;
> @@ -303,7 +316,7 @@ _eglInitSurface(_EGLSurface *surf, _EGLDisplay *dpy,
> EGLint type,
> /* the default swap interval is 1 */
> _eglClampSwapInterval(surf, 1);
>
> - err = _eglParseSurfaceAttribList(surf, attrib_list);
> + err = _eglParseSurfaceAttribList(surf, type, attrib_list);
> if (err != EGL_SUCCESS)
>return _eglError(err, func);
>
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Re: [Mesa-dev] [PATCH 01/11] i965/compute: Fix uniform init issue when SIMD8 is skipped
On Tuesday, May 24, 2016 1:37:46 AM PDT Jordan Justen wrote:
> In d8347f12ead89c5a58f69ce9283a54ac8487159c, we added support for
> skipping SIMD8 generation when the program local size is too large for
> SIMD8 to be usable. This change was missed in that commit.
>
> This bug would impact gen7 platforms when the compute shader local
> size is greater than 512, and gen8 platforms when the local size is
> greater than 448.
>
> Signed-off-by: Jordan Justen
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> index cc30838..f28583c 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
> @@ -181,7 +181,7 @@ fs_visitor::nir_setup_outputs()
> void
> fs_visitor::nir_setup_uniforms()
> {
> - if (dispatch_width != 8)
> + if (dispatch_width != min_dispatch_width)
>return;
>
> uniforms = nir->num_uniforms / 4;
>
This patch is:
Reviewed-by: Kenneth Graunke
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Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On Tue, May 24, 2016 at 4:58 PM, Kristian Høgsberg wrote: > diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c > b/src/mesa/drivers/dri/i965/intel_extensions.c > index feea6ca..b8d7517 100644 > --- a/src/mesa/drivers/dri/i965/intel_extensions.c > +++ b/src/mesa/drivers/dri/i965/intel_extensions.c > @@ -246,6 +246,7 @@ intelInitExtensions(struct gl_context *ctx) > ctx->Extensions.EXT_texture_sRGB_decode = true; > ctx->Extensions.EXT_texture_swizzle = true; > ctx->Extensions.EXT_vertex_array_bgra = true; > + ctx->Extensions.KHR_robustness = true; > ctx->Extensions.AMD_seamless_cubemap_per_texture = true; > ctx->Extensions.APPLE_object_purgeable = true; > ctx->Extensions.ATI_separate_stencil = true; Same comment as before -- I'd move this between ATI_* and MESA_* ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 12/21] i965/fs: Clean up remaining uses of dispatch_width in the generator.
Jason Ekstrand writes:
> Does this mean we can delete the field from brw_fs_generator?
>
Almost, there is still one use left in fire_fb_write() (for the dual
source blend last-rt hack) which we will be able to get rid of
eventually, but it cannot simply be replaced with inst->exec_size
because it's really the shader dispatch width what it needs right now.
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> Most of these are bugs because the intended execution size of an
>> instruction and the dispatch width of the shader aren't necessarily
>> the same (especially in SIMD32 programs).
>> ---
>> src/mesa/drivers/dri/i965/brw_eu.h | 1 -
>> src/mesa/drivers/dri/i965/brw_eu_emit.c| 3 +--
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 13 +++--
>> 3 files changed, 8 insertions(+), 9 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
>> b/src/mesa/drivers/dri/i965/brw_eu.h
>> index 91e3401..b057f17 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu.h
>> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
>> @@ -281,7 +281,6 @@ void brw_svb_write(struct brw_codegen *p,
>> bool send_commit_msg);
>>
>> void brw_fb_WRITE(struct brw_codegen *p,
>> - int dispatch_width,
>>struct brw_reg payload,
>>struct brw_reg implied_header,
>>unsigned msg_control,
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> index 10cbbe8..ff8e207 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> @@ -2342,7 +2342,6 @@ void brw_oword_block_read(struct brw_codegen *p,
>>
>>
>> void brw_fb_WRITE(struct brw_codegen *p,
>> - int dispatch_width,
>>struct brw_reg payload,
>>struct brw_reg implied_header,
>>unsigned msg_control,
>> @@ -2358,7 +2357,7 @@ void brw_fb_WRITE(struct brw_codegen *p,
>> unsigned msg_type;
>> struct brw_reg dest, src0;
>>
>> - if (dispatch_width == 16)
>> + if (brw_inst_exec_size(devinfo, p->current) >= BRW_EXECUTE_16)
>>dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
>> else
>>dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> index 71ac730..9751926 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> @@ -229,7 +229,6 @@ fs_generator::fire_fb_write(fs_inst *inst,
>>
>>
>> brw_fb_WRITE(p,
>> -dispatch_width,
>> payload,
>> implied_header,
>> msg_control,
>> @@ -547,7 +546,7 @@ fs_generator::generate_linterp(fs_inst *inst,
>> * See also: emit_interpolation_setup_gen4().
>> */
>> struct brw_reg delta_x = src[0];
>> - struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
>> + struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
>> struct brw_reg interp = src[1];
>>
>> if (devinfo->has_pln &&
>> @@ -1206,10 +1205,11 @@
>> fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
>> uint32_t surf_index = index.ud;
>>
>> uint32_t simd_mode, rlen, msg_type;
>> - if (dispatch_width == 16) {
>> + if (inst->exec_size == 16) {
>>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
>>rlen = 8;
>> } else {
>> + assert(inst->exec_size == 8);
>>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
>>rlen = 4;
>> }
>> @@ -1267,11 +1267,12 @@
>> fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
>> assert(index.type == BRW_REGISTER_TYPE_UD);
>>
>> uint32_t simd_mode, rlen, mlen;
>> - if (dispatch_width == 16) {
>> + if (inst->exec_size == 16) {
>>mlen = 2;
>>rlen = 8;
>>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
>> } else {
>> + assert(inst->exec_size == 8);
>>mlen = 1;
>>rlen = 4;
>>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
>> @@ -1407,9 +1408,9 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
>>src0.type == BRW_REGISTER_TYPE_UD);
>>
>> struct brw_reg reg = stride(src1, 1, 4, 0);
>> - if (devinfo->gen >= 8 || dispatch_width == 8) {
>> + if (devinfo->gen >= 8 || inst->exec_size == 8) {
>>brw_ADD(p, dst, src0, reg);
>> - } else if (dispatch_width == 16) {
>> + } else if (inst->exec_size == 16) {
>>brw_push_insn_state(p);
>>brw_set_default_exec_size(p, BRW_EXECUTE_8);
>>brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>> --
>> 2.7.3
>>
>> ___
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>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>
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Re: [Mesa-dev] [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHANNEL.
Kenneth Graunke writes:
> On Tuesday, May 24, 2016 5:27:59 PM PDT Francisco Jerez wrote:
>> Jason Ekstrand writes:
>>
>> > On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
>> > wrote:
>> >
>> >> Due to a Gen7-specific hardware bug native 32-wide instructions get
>> >> the lower 16 bits of the execution mask applied incorrectly to both
>> >> halves of the instruction, so the MOV trick we currently use wouldn't
>> >> work. Instead emit multiple 16-wide MOV instructions in 32-wide mode
>> >> in order to cover the whole execution mask.
>> >> ---
>> >> src/mesa/drivers/dri/i965/brw_eu_emit.c | 25 +
>> >> 1 file changed, 17 insertions(+), 8 deletions(-)
>> >>
>> >> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> >> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> >> index af7caed..d36877c 100644
>> >> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> >> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> >> @@ -3330,6 +3330,7 @@ void
>> >> brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst)
>> >> {
>> >> const struct brw_device_info *devinfo = p->devinfo;
>> >> + const unsigned exec_size = 1 << brw_inst_exec_size(devinfo,
>> >> p->current);
>> >> brw_inst *inst;
>> >>
>> >> assert(devinfo->gen >= 7);
>> >> @@ -3359,15 +3360,23 @@ brw_find_live_channel(struct brw_codegen *p,
>> >> struct brw_reg dst)
>> >>
>> >> brw_MOV(p, flag, brw_imm_ud(0));
>> >>
>> >> - /* Run a 16-wide instruction returning zero with execution
>> >> masking
>> >> - * and a conditional modifier enabled in order to get the
>> >> current
>> >> - * execution mask in f1.0.
>> >> + /* Run enough instructions returning zero with execution masking
>> >> and
>> >> + * a conditional modifier enabled in order to get the full
>> >> execution
>> >> + * mask in f1.0. We could use a single 32-wide move here if it
>> >> + * weren't because of the hardware bug that causes channel
>> >> enables to
>> >> + * be applied incorrectly to the second half of 32-wide
>> >> instructions
>> >> + * on Gen7.
>> >>*/
>> >> - inst = brw_MOV(p, brw_null_reg(), brw_imm_ud(0));
>> >> - brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_16);
>> >> - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
>> >> - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
>> >> - brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>> >> + const unsigned lower_size = MIN2(16, exec_size);
>> >> + for (unsigned i = 0; i < exec_size / lower_size; i++) {
>> >> +inst = brw_MOV(p, retype(brw_null_reg(),
>> >> BRW_REGISTER_TYPE_UW),
>> >> + brw_imm_uw(0));
>> >>
>> >
>> > Is there a reason this is changing from D to UW?
>> >
>>
>> It's likely to have lower execution latency than an instruction with
>> 32-bit integer execution type. It shouldn't have any practical
>> implications other than that, the result of the instruction is only used
>> to set bits of the flag register.
>
> I've never heard anything about them having different latencies.
> That doesn't mean that you're wrong, though. :)
>
AFAIUI the FPU pipeline is 4-wide (i.e. it can process four elements per
clock at a given stage of the pipeline) when the execution type is
F/D/UD, 8-wide when it is HF/W/UW, and 2-wide when it is DF/Q/UQ (this
is not accounting for hybrid-issue and such). Other than that if the
execution type is D the instructions would have to be compressed when
the execution size of the FIND_LIVE_CHANNEL instruction is 16 or 32.
> --Ken
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Re: [Mesa-dev] [PATCH] i965/urb: fixes division by zero
On Tue, May 17, 2016 at 11:50:28AM -0700, Matt Turner wrote:
> On Mon, May 16, 2016 at 4:27 PM, Ardinartsev Nikita
> wrote:
> > Fixes regression introduced by af5ca43f2676bff7499f93277f908b681cb821d0
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
>
> Thank you very much for the patch. It is
>
> Reviewed-by: Matt Turner
>
> I'll commit it shortly.
Great patch.
Reviewed-by: Ben Widawsky
>
> > ---
> > src/mesa/drivers/dri/i965/gen7_urb.c | 24 +---
> > 1 file changed, 5 insertions(+), 19 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c
> > b/src/mesa/drivers/dri/i965/gen7_urb.c
> > index a412a42..4194541 100644
> > --- a/src/mesa/drivers/dri/i965/gen7_urb.c
> > +++ b/src/mesa/drivers/dri/i965/gen7_urb.c
> > @@ -292,25 +292,11 @@ gen7_upload_urb(struct brw_context *brw)
> > if (remaining_space > total_wants)
> >remaining_space = total_wants;
> > if (remaining_space > 0) {
> > - unsigned vs_additional = (unsigned)
> > - roundf(vs_wants * (((float) remaining_space) / total_wants));
> > - vs_chunks += vs_additional;
> > - remaining_space -= vs_additional;
> > - total_wants -= vs_wants;
> > -
> > - unsigned hs_additional = (unsigned)
> > - round(hs_wants * (((double) remaining_space) / total_wants));
> > - hs_chunks += hs_additional;
> > - remaining_space -= hs_additional;
> > - total_wants -= hs_wants;
> > -
> > - unsigned ds_additional = (unsigned)
> > - round(ds_wants * (((double) remaining_space) / total_wants));
> > - ds_chunks += ds_additional;
> > - remaining_space -= ds_additional;
> > - total_wants -= ds_wants;
> > -
> > - gs_chunks += remaining_space;
> > + float ratio = ((float) remaining_space) / total_wants;
> > + vs_chunks += roundf(vs_wants * ratio);
> > + hs_chunks += roundf(hs_wants * ratio);
> > + ds_chunks += roundf(ds_wants * ratio);
> > + gs_chunks += roundf(gs_wants * ratio);
>
> I plan to change these roundf() calls to lroundf().
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[Mesa-dev] [PATCH 1/2] tgsi: s/6/PIPE_SHADER_TYPES/ for tgsi_processor_type_names array size
---
src/gallium/auxiliary/tgsi/tgsi_strings.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h
b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index 031d322..9a9362e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
@@ -38,7 +38,7 @@ extern "C" {
#endif
-extern const char *tgsi_processor_type_names[6];
+extern const char *tgsi_processor_type_names[PIPE_SHADER_TYPES];
extern const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT];
--
1.9.1
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[Mesa-dev] [PATCH 2/2] tgsi: print TGSI_PROPERTY_NEXT_SHADER value as string, not an integer
Print "GEOM" instead of "2", for example.
v2: also update the text parsing code, per Ilia.
---
src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++
src/gallium/auxiliary/tgsi/tgsi_text.c | 22 ++
2 files changed, 25 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c
b/src/gallium/auxiliary/tgsi/tgsi_dump.c
index 0d8bd1b..d59b7ff 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_dump.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c
@@ -470,6 +470,9 @@ iter_property(
case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER:
ENM(prop->u[i].Data, tgsi_fs_coord_pixel_center_names);
break;
+ case TGSI_PROPERTY_NEXT_SHADER:
+ ENM(prop->u[i].Data, tgsi_processor_type_names);
+ break;
default:
SID( prop->u[i].Data );
break;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index ea1ee53..955d042 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1663,6 +1663,22 @@ parse_fs_coord_pixel_center( const char **pcur, uint
*fs_coord_pixel_center )
return FALSE;
}
+static boolean
+parse_property_next_shader( const char **pcur, uint *next_shader )
+{
+ uint i;
+
+ for (i = 0; i < ARRAY_SIZE(tgsi_processor_type_names); i++) {
+ const char *cur = *pcur;
+
+ if (str_match_nocase_whole( &cur, tgsi_processor_type_names[i])) {
+ *next_shader = i;
+ *pcur = cur;
+ return TRUE;
+ }
+ }
+ return FALSE;
+}
static boolean parse_property( struct translate_ctx *ctx )
{
@@ -1716,6 +1732,12 @@ static boolean parse_property( struct translate_ctx *ctx
)
return FALSE;
}
break;
+ case TGSI_PROPERTY_NEXT_SHADER:
+ if (!parse_property_next_shader(&ctx->cur, &values[0] )) {
+ report_error( ctx, "Unknown next shader property value." );
+ return FALSE;
+ }
+ break;
case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
default:
if (!parse_uint(&ctx->cur, &values[0] )) {
--
1.9.1
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Re: [Mesa-dev] [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHANNEL.
On Tuesday, May 24, 2016 5:27:59 PM PDT Francisco Jerez wrote:
> Jason Ekstrand writes:
>
> > On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> > wrote:
> >
> >> Due to a Gen7-specific hardware bug native 32-wide instructions get
> >> the lower 16 bits of the execution mask applied incorrectly to both
> >> halves of the instruction, so the MOV trick we currently use wouldn't
> >> work. Instead emit multiple 16-wide MOV instructions in 32-wide mode
> >> in order to cover the whole execution mask.
> >> ---
> >> src/mesa/drivers/dri/i965/brw_eu_emit.c | 25 +
> >> 1 file changed, 17 insertions(+), 8 deletions(-)
> >>
> >> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> index af7caed..d36877c 100644
> >> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> >> @@ -3330,6 +3330,7 @@ void
> >> brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst)
> >> {
> >> const struct brw_device_info *devinfo = p->devinfo;
> >> + const unsigned exec_size = 1 << brw_inst_exec_size(devinfo,
> >> p->current);
> >> brw_inst *inst;
> >>
> >> assert(devinfo->gen >= 7);
> >> @@ -3359,15 +3360,23 @@ brw_find_live_channel(struct brw_codegen *p,
> >> struct brw_reg dst)
> >>
> >> brw_MOV(p, flag, brw_imm_ud(0));
> >>
> >> - /* Run a 16-wide instruction returning zero with execution
> >> masking
> >> - * and a conditional modifier enabled in order to get the current
> >> - * execution mask in f1.0.
> >> + /* Run enough instructions returning zero with execution masking
> >> and
> >> + * a conditional modifier enabled in order to get the full
> >> execution
> >> + * mask in f1.0. We could use a single 32-wide move here if it
> >> + * weren't because of the hardware bug that causes channel
> >> enables to
> >> + * be applied incorrectly to the second half of 32-wide
> >> instructions
> >> + * on Gen7.
> >>*/
> >> - inst = brw_MOV(p, brw_null_reg(), brw_imm_ud(0));
> >> - brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_16);
> >> - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
> >> - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
> >> - brw_inst_set_flag_reg_nr(devinfo, inst, 1);
> >> + const unsigned lower_size = MIN2(16, exec_size);
> >> + for (unsigned i = 0; i < exec_size / lower_size; i++) {
> >> +inst = brw_MOV(p, retype(brw_null_reg(),
> >> BRW_REGISTER_TYPE_UW),
> >> + brw_imm_uw(0));
> >>
> >
> > Is there a reason this is changing from D to UW?
> >
>
> It's likely to have lower execution latency than an instruction with
> 32-bit integer execution type. It shouldn't have any practical
> implications other than that, the result of the instruction is only used
> to set bits of the flag register.
I've never heard anything about them having different latencies.
That doesn't mean that you're wrong, though. :)
--Ken
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Re: [Mesa-dev] [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHANNEL.
Jason Ekstrand writes:
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> Due to a Gen7-specific hardware bug native 32-wide instructions get
>> the lower 16 bits of the execution mask applied incorrectly to both
>> halves of the instruction, so the MOV trick we currently use wouldn't
>> work. Instead emit multiple 16-wide MOV instructions in 32-wide mode
>> in order to cover the whole execution mask.
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_emit.c | 25 +
>> 1 file changed, 17 insertions(+), 8 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> index af7caed..d36877c 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> @@ -3330,6 +3330,7 @@ void
>> brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst)
>> {
>> const struct brw_device_info *devinfo = p->devinfo;
>> + const unsigned exec_size = 1 << brw_inst_exec_size(devinfo,
>> p->current);
>> brw_inst *inst;
>>
>> assert(devinfo->gen >= 7);
>> @@ -3359,15 +3360,23 @@ brw_find_live_channel(struct brw_codegen *p,
>> struct brw_reg dst)
>>
>> brw_MOV(p, flag, brw_imm_ud(0));
>>
>> - /* Run a 16-wide instruction returning zero with execution
>> masking
>> - * and a conditional modifier enabled in order to get the current
>> - * execution mask in f1.0.
>> + /* Run enough instructions returning zero with execution masking
>> and
>> + * a conditional modifier enabled in order to get the full
>> execution
>> + * mask in f1.0. We could use a single 32-wide move here if it
>> + * weren't because of the hardware bug that causes channel
>> enables to
>> + * be applied incorrectly to the second half of 32-wide
>> instructions
>> + * on Gen7.
>>*/
>> - inst = brw_MOV(p, brw_null_reg(), brw_imm_ud(0));
>> - brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_16);
>> - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
>> - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
>> - brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>> + const unsigned lower_size = MIN2(16, exec_size);
>> + for (unsigned i = 0; i < exec_size / lower_size; i++) {
>> +inst = brw_MOV(p, retype(brw_null_reg(),
>> BRW_REGISTER_TYPE_UW),
>> + brw_imm_uw(0));
>>
>
> Is there a reason this is changing from D to UW?
>
It's likely to have lower execution latency than an instruction with
32-bit integer execution type. It shouldn't have any practical
implications other than that, the result of the instruction is only used
to set bits of the flag register.
>
>> +brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
>> +brw_inst_set_group(devinfo, inst, lower_size * i);
>> +brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
>> +brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>> +brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
>> + }
>>
>> brw_FBL(p, vec1(dst), flag);
>>}
>> --
>> 2.7.3
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>>
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Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
On 05/24/2016 04:58 PM, Kristian Høgsberg wrote: > From: Kristian Høgsberg Kristensen > > As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all > entry points when we lose a context. We do this by creating a new > dispatch table and setting that when we learn that we've lost the > context. > > With the GL_CONTEXT_LOST reporting in place we can turn on > GL_KHR_robustness. > > Signed-off-by: Kristian Høgsberg Kristensen > --- > > v2: Add dispatch for un-suffixed and KHR-suffixed entrypoint added by > the extension. > > docs/GL3.txt | 2 +- > docs/relnotes/11.3.0.html | 1 + > src/mapi/glapi/gen/KHR_robustness.xml | 66 + > src/mapi/glapi/gen/KHR_robustness_es.xml | 63 > src/mapi/glapi/gen/Makefile.am| 2 + > src/mapi/glapi/gen/es_EXT.xml | 2 + > src/mapi/glapi/gen/gl_API.xml | 3 + > src/mesa/drivers/dri/i965/brw_context.h | 2 + > src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + > src/mesa/drivers/dri/i965/intel_extensions.c | 1 + > src/mesa/main/context.c | 1 + > src/mesa/main/context.h | 2 + > src/mesa/main/extensions_table.h | 1 + > src/mesa/main/getstring.c | 82 > ++- > src/mesa/main/mtypes.h| 7 ++- > src/mesa/main/tests/dispatch_sanity.cpp | 12 > 17 files changed, 267 insertions(+), 3 deletions(-) > create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml > create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index b5f03af..21ab46a 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: >GL_ARB_shader_texture_image_samples DONE (i965, nv50, > nvc0, r600, radeonsi) >GL_ARB_texture_barrierDONE (i965, nv50, > nvc0, r600, radeonsi) >GL_KHR_context_flush_control DONE (all - but > needs GLX/EGL extension to be useful) > - GL_KHR_robustness not started (90% > done with the ARB variant) > + GL_KHR_robustness DONE (i965) >GL_EXT_shader_integer_mix DONE (all drivers > that support GLSL) > > These are the extensions cherry-picked to make GLES 3.1 > diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html > index 5871ec8..d5bb292 100644 > --- a/docs/relnotes/11.3.0.html > +++ b/docs/relnotes/11.3.0.html > @@ -59,6 +59,7 @@ Note: some of the new features are only available with > certain drivers. > GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe > GL_ATI_fragment_shader on all Gallium drivers > GL_EXT_base_instance on all drivers that support > GL_ARB_base_instance > +GL_KHR_robustness on i965 > GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all > drivers that support GL_ARB_draw_buffers_blend > GL_OES_sample_shading on i965, nvc0, r600, radeonsi > GL_OES_sample_variables on i965, nvc0, r600, radeonsi > diff --git a/src/mapi/glapi/gen/KHR_robustness.xml > b/src/mapi/glapi/gen/KHR_robustness.xml > new file mode 100644 > index 000..56bcfcc > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness.xml > @@ -0,0 +1,66 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + alias="GetGraphicsResetStatusARB"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml > b/src/mapi/glapi/gen/KHR_robustness_es.xml > new file mode 100644 > index 000..ba8bdda > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml > @@ -0,0 +1,63 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + value="0x0004"/> > + > + s/both ES/ES/ > + > + + alias="GetGraphicsResetStatusARB" es2="2.0"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am > index 0759819..c511de9 100644 > ---
Re: [Mesa-dev] [PATCH 20/21] i965/ir: Make BROADCAST emit an unmasked single-channel move.
Jason Ekstrand writes:
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> Alternatively we could have extended the current semantics to 32-wide
>> mode by changing brw_broadcast() to emit multiple indexed MOV
>> instructions in the generator copying the selected value to all
>> destination registers, but it seemed rather silly to waste EU cycles
>> unnecessarily copying the exact same value 32 times in the GRF.
>>
>
> It appears as if emit_uniformize in fs_builder sets stride == 0 on the
> result the version in vec4_visitor does not. It's probably not needed for
> correctness since I think the generator will always take channel 0 anyway,
> but we should fix it none the less.
Unfortunately we can't without substantial churn, because the VEC4 IR
currently has no way to represent scalar regions in the VGRF.
>
>
>> The vstride change in the Align16 path is required to avoid assertions
>> in validate_reg() since the change causes the execution size of the
>> MOV and SEL instructions to be equal to the source region width.
>> ---
>> src/mesa/drivers/dri/i965/brw_defines.h | 6 ++
>> src/mesa/drivers/dri/i965/brw_eu_emit.c | 12 +---
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 1 +
>> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 +
>> 4 files changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
>> b/src/mesa/drivers/dri/i965/brw_defines.h
>> index 702eb5a..8794d44 100644
>> --- a/src/mesa/drivers/dri/i965/brw_defines.h
>> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
>> @@ -1080,6 +1080,12 @@ enum opcode {
>> /**
>> * Pick the channel from its first source register given by the index
>> * specified as second source. Useful for variable indexing of
>> surfaces.
>> +*
>> +* Note that because the result of this instruction is by definition
>> +* uniform and it can always be splatted to multiple channels using a
>> +* scalar regioning mode, only the first channel of the destination
>> region
>> +* is guaranteed to be updated, which implies that BROADCAST
>> instructions
>> +* should usually be marked force_writemask_all.
>> */
>> SHADER_OPCODE_BROADCAST,
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> index b11398c..ee7462f 100644
>> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
>> @@ -3425,6 +3425,10 @@ brw_broadcast(struct brw_codegen *p,
>> const bool align1 = brw_inst_access_mode(devinfo, p->current) ==
>> BRW_ALIGN_1;
>> brw_inst *inst;
>>
>> + brw_push_insn_state(p);
>> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>> + brw_set_default_exec_size(p, align1 ? BRW_EXECUTE_1 : BRW_EXECUTE_4);
>> +
>> assert(src.file == BRW_GENERAL_REGISTER_FILE &&
>>src.address_mode == BRW_ADDRESS_DIRECT);
>>
>> @@ -3475,19 +3479,21 @@ brw_broadcast(struct brw_codegen *p,
>>*/
>> inst = brw_MOV(p,
>> brw_null_reg(),
>> -stride(brw_swizzle(idx, BRW_SWIZZLE_), 0, 4,
>> 1));
>> +stride(brw_swizzle(idx, BRW_SWIZZLE_), 4, 4,
>> 1));
>> brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NONE);
>> brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_NZ);
>> brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>>
>> /* and use predicated SEL to pick the right channel. */
>> inst = brw_SEL(p, dst,
>> -stride(suboffset(src, 4), 0, 4, 1),
>> -stride(src, 0, 4, 1));
>> +stride(suboffset(src, 4), 4, 4, 1),
>> +stride(src, 4, 4, 1));
>> brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NORMAL);
>> brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>>}
>> }
>> +
>> + brw_pop_insn_state(p);
>> }
>>
>> /**
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> index 6421870..804c639 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
>> @@ -2017,6 +2017,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
>> dispatch_width)
>> break;
>>
>>case SHADER_OPCODE_BROADCAST:
>> + assert(inst->force_writemask_all);
>> brw_broadcast(p, dst, src[0], src[1]);
>> break;
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> index baf4422..bb0254e 100644
>> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
>> @@ -1886,6 +1886,7 @@ generate_code(struct brw_codegen *p,
>> break;
>>
>>case SHADER_OPCODE_BROADCAST:
>> + assert(inst->force_writemask_
Re: [Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
Sorry to be pedantic, but you're enabling the ext for gles1.1, but the new entrypoint appear to only apply to gles2. I think you also want a es1="1.1" or something along those lines. On May 24, 2016 8:02 PM, "Kristian Høgsberg" wrote: > From: Kristian Høgsberg Kristensen > > As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all > entry points when we lose a context. We do this by creating a new > dispatch table and setting that when we learn that we've lost the > context. > > With the GL_CONTEXT_LOST reporting in place we can turn on > GL_KHR_robustness. > > Signed-off-by: Kristian Høgsberg Kristensen > --- > > v2: Add dispatch for un-suffixed and KHR-suffixed entrypoint added by > the extension. > > docs/GL3.txt | 2 +- > docs/relnotes/11.3.0.html | 1 + > src/mapi/glapi/gen/KHR_robustness.xml | 66 + > src/mapi/glapi/gen/KHR_robustness_es.xml | 63 > src/mapi/glapi/gen/Makefile.am| 2 + > src/mapi/glapi/gen/es_EXT.xml | 2 + > src/mapi/glapi/gen/gl_API.xml | 3 + > src/mesa/drivers/dri/i965/brw_context.h | 2 + > src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + > src/mesa/drivers/dri/i965/intel_extensions.c | 1 + > src/mesa/main/context.c | 1 + > src/mesa/main/context.h | 2 + > src/mesa/main/extensions_table.h | 1 + > src/mesa/main/getstring.c | 82 > ++- > src/mesa/main/mtypes.h| 7 ++- > src/mesa/main/tests/dispatch_sanity.cpp | 12 > 17 files changed, 267 insertions(+), 3 deletions(-) > create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml > create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml > > diff --git a/docs/GL3.txt b/docs/GL3.txt > index b5f03af..21ab46a 100644 > --- a/docs/GL3.txt > +++ b/docs/GL3.txt > @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: >GL_ARB_shader_texture_image_samples DONE (i965, nv50, > nvc0, r600, radeonsi) >GL_ARB_texture_barrierDONE (i965, nv50, > nvc0, r600, radeonsi) >GL_KHR_context_flush_control DONE (all - but > needs GLX/EGL extension to be useful) > - GL_KHR_robustness not started (90% > done with the ARB variant) > + GL_KHR_robustness DONE (i965) >GL_EXT_shader_integer_mix DONE (all drivers > that support GLSL) > > These are the extensions cherry-picked to make GLES 3.1 > diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html > index 5871ec8..d5bb292 100644 > --- a/docs/relnotes/11.3.0.html > +++ b/docs/relnotes/11.3.0.html > @@ -59,6 +59,7 @@ Note: some of the new features are only available with > certain drivers. > GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe > GL_ATI_fragment_shader on all Gallium drivers > GL_EXT_base_instance on all drivers that support > GL_ARB_base_instance > +GL_KHR_robustness on i965 > GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all > drivers that support GL_ARB_draw_buffers_blend > GL_OES_sample_shading on i965, nvc0, r600, radeonsi > GL_OES_sample_variables on i965, nvc0, r600, radeonsi > diff --git a/src/mapi/glapi/gen/KHR_robustness.xml > b/src/mapi/glapi/gen/KHR_robustness.xml > new file mode 100644 > index 000..56bcfcc > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness.xml > @@ -0,0 +1,66 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + alias="GetGraphicsResetStatusARB"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml > b/src/mapi/glapi/gen/KHR_robustness_es.xml > new file mode 100644 > index 000..ba8bdda > --- /dev/null > +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml > @@ -0,0 +1,63 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + value="0x0004"/> > + > + > + > + + alias="GetGraphicsResetStatusARB" es2="2.0"> > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + es2="2.0"> > + > +
Re: [Mesa-dev] [PATCH 21/21] i965/fs: Expose arbitrary channel execution groups to the IR.
Jason Ekstrand writes:
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> This generalizes the current fs_inst::force_sechalf flag to allow
>> specifying channel enable groups other than 0 or 8. At some point it
>> will likely make sense to fix the vec4 generator to support arbitrary
>> execution groups and then move the definition of fs_inst::group into
>> backend_instruction (e.g. so we can do FP64 in the VEC4 back-end).
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.cpp | 20
>>
>> src/mesa/drivers/dri/i965/brw_fs_builder.h| 14 +++---
>> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 4 ++--
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 7 ---
>> src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 2 +-
>> src/mesa/drivers/dri/i965/brw_ir_fs.h | 20
>> +---
>> 6 files changed, 35 insertions(+), 32 deletions(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> index a59cd3c..92caeaa 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
>> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
>> @@ -3638,7 +3638,7 @@ fs_visitor::lower_integer_multiplication()
>> mul->src[1].stride *= 2;
>>
>> } else if (devinfo->gen == 7 && !devinfo->is_haswell &&
>> -inst->force_sechalf) {
>> +inst->group > 0) {
>> /* Among other things the quarter control bits influence which
>> * accumulator register is used by the hardware for
>> instructions
>> * that access the accumulator implicitly (e.g. MACH). A
>> @@ -3655,7 +3655,7 @@ fs_visitor::lower_integer_multiplication()
>> * to get the result masked correctly according to the current
>> * channel enables.
>> */
>> -mach->force_sechalf = false;
>> +mach->group = 0;
>> mach->force_writemask_all = true;
>> mach->dst = ibld.vgrf(inst->dst.type);
>> ibld.MOV(inst->dst, mach->dst);
>> @@ -3791,8 +3791,8 @@ lower_fb_write_logical_send(const fs_builder &bld,
>> fs_inst *inst,
>>sample_mask.stride *= 2;
>>
>>bld.exec_all().annotate("FB write oMask")
>> - .MOV(half(retype(sources[length], BRW_REGISTER_TYPE_UW),
>> - inst->force_sechalf),
>> + .MOV(horiz_offset(retype(sources[length], BRW_REGISTER_TYPE_UW),
>> + inst->group),
>>sample_mask);
>>length++;
>> }
>> @@ -5017,10 +5017,10 @@ fs_visitor::lower_simd_width()
>>* execution size of the builder to the highest of both for now
>> so
>>* we're sure that both cases can be handled.
>>*/
>> + const unsigned max_width = MAX2(inst->exec_size, lower_width);
>> const fs_builder ibld = bld.at(block, inst)
>> .exec_all(inst->force_writemask_all)
>> -.group(MAX2(inst->exec_size,
>> lower_width),
>> - inst->force_sechalf);
>> +.group(max_width, inst->group /
>> max_width);
>>
>> /* Split the copies in chunks of the execution width of either
>> the
>>* original or the lowered instruction, whichever is lower.
>> @@ -5352,12 +5352,8 @@ fs_visitor::dump_instruction(backend_instruction
>> *be_inst, FILE *file)
>> if (inst->force_writemask_all)
>>fprintf(file, "NoMask ");
>>
>> - if (dispatch_width == 16 && inst->exec_size == 8) {
>> - if (inst->force_sechalf)
>> - fprintf(file, "2ndhalf ");
>> - else
>> - fprintf(file, "1sthalf ");
>> - }
>> + if (inst->exec_size != dispatch_width)
>> + fprintf(file, "group%d ", inst->group);
>>
>> fprintf(file, "\n");
>> }
>> diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
>> b/src/mesa/drivers/dri/i965/brw_fs_builder.h
>> index b50dda4..c1d13a2 100644
>> --- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
>> +++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
>> @@ -72,7 +72,7 @@ namespace brw {
>>fs_builder(backend_shader *shader, bblock_t *block, fs_inst *inst) :
>> shader(shader), block(block), cursor(inst),
>> _dispatch_width(inst->exec_size),
>> - _group(inst->force_sechalf ? 8 : 0),
>> + _group(inst->group),
>> force_writemask_all(inst->force_writemask_all)
>>{
>> annotation.str = inst->annotation;
>> @@ -168,6 +168,15 @@ namespace brw {
>>}
>>
>>/**
>> + * Get the channel group in use.
>> + */
>> + unsigned
>> + group() const
>> + {
>> + return _group;
>> + }
>> +
>> + /**
>> * Allocate a virtual register of natural vector size (one for this
>> IR)
>> * and SIMD width. \p n gives the amount of space to allocate in
>>
Re: [Mesa-dev] [PATCH] gallium/radeon: add the kernel version into the renderer string
Do you need the DRM version number if you'll be displaying the kernel
version anyway?
On Wed, 25 May 2016 at 00:09 Marek Olšák wrote:
> From: Marek Olšák
>
> Example:
> Gallium 0.4 on AMD TONGA (DRM 3.2.0 / 4.5.0, LLVM 3.9.0)
>
> My kernel version is pretty long already (4.5.0-amd-01025-g32791c1)
> and adding "kernel" into the string would make too it long for glxinfo
> to display.
> ---
> src/gallium/drivers/radeon/r600_pipe_common.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index 8d9c5a5..c00e584 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -37,6 +37,7 @@
> #include "vl/vl_video_buffer.h"
> #include "radeon/radeon_video.h"
> #include
> +#include
>
> #ifndef HAVE_LLVM
> #define HAVE_LLVM 0
> @@ -938,10 +939,15 @@ struct pipe_resource
> *r600_resource_create_common(struct pipe_screen *screen,
> bool r600_common_screen_init(struct r600_common_screen *rscreen,
> struct radeon_winsys *ws)
> {
> - char llvm_string[32] = {};
> + char llvm_string[32] = {}, kernel_version[128] = {};
> + struct utsname uname_data;
>
> ws->query_info(ws, &rscreen->info);
>
> + if (uname(&uname_data) == 0)
> + snprintf(kernel_version, sizeof(kernel_version),
> +" / %s", uname_data.release);
> +
> #if HAVE_LLVM
> snprintf(llvm_string, sizeof(llvm_string),
> ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
> @@ -949,10 +955,10 @@ bool r600_common_screen_init(struct
> r600_common_screen *rscreen,
> #endif
>
> snprintf(rscreen->renderer_string,
> sizeof(rscreen->renderer_string),
> -"%s (DRM %i.%i.%i%s)",
> +"%s (DRM %i.%i.%i%s%s)",
> r600_get_chip_name(rscreen), rscreen->info.drm_major,
> rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
> -llvm_string);
> +kernel_version, llvm_string);
>
> rscreen->b.get_name = r600_get_name;
> rscreen->b.get_vendor = r600_get_vendor;
> --
> 2.7.4
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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[Mesa-dev] [PATCH] docs: add missing GL_OES/EXT_gpu_shader5 enablement note
Signed-off-by: Ilia Mirkin --- docs/relnotes/11.3.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html index 8d6caa2..e6ed538 100644 --- a/docs/relnotes/11.3.0.html +++ b/docs/relnotes/11.3.0.html @@ -61,6 +61,7 @@ Note: some of the new features are only available with certain drivers. GL_EXT_base_instance on all drivers that support GL_ARB_base_instance GL_EXT_clip_cull_distance on all drivers that support GL_ARB_cull_distance GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers that support GL_ARB_draw_buffers_blend +GL_OES_gpu_shader5 and GL_EXT_gpu_shader5 on all drivers that support GL_ARB_gpu_shader5 GL_OES_sample_shading on i965, nvc0, r600, radeonsi GL_OES_sample_variables on i965, nvc0, r600, radeonsi GL_OES_shader_image_atomic on all drivers that support GL_ARB_shader_image_load_store -- 2.7.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] mesa: Add support for GL_CONTEXT_LOST
From: Kristian Høgsberg Kristensen As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all entry points when we lose a context. We do this by creating a new dispatch table and setting that when we learn that we've lost the context. With the GL_CONTEXT_LOST reporting in place we can turn on GL_KHR_robustness. Signed-off-by: Kristian Høgsberg Kristensen --- v2: Add dispatch for un-suffixed and KHR-suffixed entrypoint added by the extension. docs/GL3.txt | 2 +- docs/relnotes/11.3.0.html | 1 + src/mapi/glapi/gen/KHR_robustness.xml | 66 + src/mapi/glapi/gen/KHR_robustness_es.xml | 63 src/mapi/glapi/gen/Makefile.am| 2 + src/mapi/glapi/gen/es_EXT.xml | 2 + src/mapi/glapi/gen/gl_API.xml | 3 + src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_reset.c | 20 +++ src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + src/mesa/main/context.c | 1 + src/mesa/main/context.h | 2 + src/mesa/main/extensions_table.h | 1 + src/mesa/main/getstring.c | 82 ++- src/mesa/main/mtypes.h| 7 ++- src/mesa/main/tests/dispatch_sanity.cpp | 12 17 files changed, 267 insertions(+), 3 deletions(-) create mode 100644 src/mapi/glapi/gen/KHR_robustness.xml create mode 100644 src/mapi/glapi/gen/KHR_robustness_es.xml diff --git a/docs/GL3.txt b/docs/GL3.txt index b5f03af..21ab46a 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50: GL_ARB_shader_texture_image_samples DONE (i965, nv50, nvc0, r600, radeonsi) GL_ARB_texture_barrierDONE (i965, nv50, nvc0, r600, radeonsi) GL_KHR_context_flush_control DONE (all - but needs GLX/EGL extension to be useful) - GL_KHR_robustness not started (90% done with the ARB variant) + GL_KHR_robustness DONE (i965) GL_EXT_shader_integer_mix DONE (all drivers that support GLSL) These are the extensions cherry-picked to make GLES 3.1 diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html index 5871ec8..d5bb292 100644 --- a/docs/relnotes/11.3.0.html +++ b/docs/relnotes/11.3.0.html @@ -59,6 +59,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe GL_ATI_fragment_shader on all Gallium drivers GL_EXT_base_instance on all drivers that support GL_ARB_base_instance +GL_KHR_robustness on i965 GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers that support GL_ARB_draw_buffers_blend GL_OES_sample_shading on i965, nvc0, r600, radeonsi GL_OES_sample_variables on i965, nvc0, r600, radeonsi diff --git a/src/mapi/glapi/gen/KHR_robustness.xml b/src/mapi/glapi/gen/KHR_robustness.xml new file mode 100644 index 000..56bcfcc --- /dev/null +++ b/src/mapi/glapi/gen/KHR_robustness.xml @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/mapi/glapi/gen/KHR_robustness_es.xml b/src/mapi/glapi/gen/KHR_robustness_es.xml new file mode 100644 index 000..ba8bdda --- /dev/null +++ b/src/mapi/glapi/gen/KHR_robustness_es.xml @@ -0,0 +1,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/mapi/glapi/gen/Makefile.am b/src/mapi/glapi/gen/Makefile.am index 0759819..c511de9 100644 --- a/src/mapi/glapi/gen/Makefile.am +++ b/src/mapi/glapi/gen/Makefile.am @@ -192,6 +192,8 @@ API_XML = \ INTEL_performance_query.xml \ KHR_debug.xml \ KHR_context_flush_control.xml \ + KHR_robustness.xml \ + KHR_robustness_es.xml \ KHR_texture_compression_astc.xml \ NV_conditional_render.xml \ NV_primitive_restart.xml \ diff --git a/src/mapi/glapi/gen/es_EXT.xml b/src/mapi/glapi/gen/es_EXT.xml index ce4c4c4..6886dab 100644 --- a/src/mapi/glapi/gen/es_EXT.xml +++ b/src/mapi/glapi/gen/es_EXT.xml @@ -924,6 +924,8 @@ +http://www.w3.org/200
[Mesa-dev] [PATCH] glsl: add GL_EXT_clip_cull_distance define, add helpers
Signed-off-by: Ilia Mirkin
---
This addresses the feedback I got after pushing the enablement patch.
docs/relnotes/11.3.0.html | 1 +
src/compiler/glsl/builtin_variables.cpp | 10 --
src/compiler/glsl/glcpp/glcpp-parse.y | 2 ++
src/compiler/glsl/glsl_parser_extras.h | 12
4 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 5871ec8..8d6caa2 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe
GL_ATI_fragment_shader on all Gallium drivers
GL_EXT_base_instance on all drivers that support GL_ARB_base_instance
+GL_EXT_clip_cull_distance on all drivers that support
GL_ARB_cull_distance
GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers
that support GL_ARB_draw_buffers_blend
GL_OES_sample_shading on i965, nvc0, r600, radeonsi
GL_OES_sample_variables on i965, nvc0, r600, radeonsi
diff --git a/src/compiler/glsl/builtin_variables.cpp
b/src/compiler/glsl/builtin_variables.cpp
index 3d34028..15d791c 100644
--- a/src/compiler/glsl/builtin_variables.cpp
+++ b/src/compiler/glsl/builtin_variables.cpp
@@ -674,14 +674,13 @@ builtin_variable_generator::generate_constants()
state->Const.MaxProgramTexelOffset);
}
- if (state->is_version(130, 0) || state->EXT_clip_cull_distance_enable) {
+ if (state->has_clip_distance()) {
add_const("gl_MaxClipDistances", state->Const.MaxClipPlanes);
}
if (state->is_version(130, 0)) {
add_const("gl_MaxVaryingComponents", state->ctx->Const.MaxVarying * 4);
}
- if (state->is_version(450, 0) || state->ARB_cull_distance_enable ||
- state->EXT_clip_cull_distance_enable) {
+ if (state->has_cull_distance()) {
add_const("gl_MaxCullDistances", state->Const.MaxClipPlanes);
add_const("gl_MaxCombinedClipAndCullDistances",
state->Const.MaxClipPlanes);
@@ -1259,12 +1258,11 @@ builtin_variable_generator::generate_varyings()
}
}
- if (state->is_version(130, 0) || state->EXT_clip_cull_distance_enable) {
+ if (state->has_clip_distance()) {
add_varying(VARYING_SLOT_CLIP_DIST0, array(float_t, 0),
"gl_ClipDistance");
}
- if (state->is_version(450, 0) || state->ARB_cull_distance_enable ||
- state->EXT_clip_cull_distance_enable) {
+ if (state->has_cull_distance()) {
add_varying(VARYING_SLOT_CULL_DIST0, array(float_t, 0),
"gl_CullDistance");
}
diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y
b/src/compiler/glsl/glcpp/glcpp-parse.y
index 820458a..8048f8d 100644
--- a/src/compiler/glsl/glcpp/glcpp-parse.y
+++ b/src/compiler/glsl/glcpp/glcpp-parse.y
@@ -2310,6 +2310,8 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t
*parser, intmax_t versio
add_builtin_define(parser,
"GL_OES_texture_storage_multisample_2d_array", 1);
if (extensions->ARB_blend_func_extended)
add_builtin_define(parser, "GL_EXT_blend_func_extended", 1);
+ if (extensions->ARB_cull_distance)
+add_builtin_define(parser, "GL_EXT_clip_cull_distance", 1);
if (version >= 310) {
if (extensions->ARB_shader_image_load_store)
diff --git a/src/compiler/glsl/glsl_parser_extras.h
b/src/compiler/glsl/glsl_parser_extras.h
index 3afc9cb..2e77b24 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -272,6 +272,18 @@ struct _mesa_glsl_parse_state {
is_version(150, 320);
}
+ bool has_clip_distance() const
+ {
+ return EXT_clip_cull_distance_enable || is_version(130, 0);
+ }
+
+ bool has_cull_distance() const
+ {
+ return EXT_clip_cull_distance_enable ||
+ ARB_cull_distance_enable ||
+ is_version(450, 0);
+ }
+
void process_version_directive(YYLTYPE *locp, int version,
const char *ident);
--
2.7.3
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[Mesa-dev] [PATCH] i965/draw: Use the correct buffer index for interleaved VBO sizes
The buffer_range_* arrays are indexed by buffer index not element index. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 3349161..f4d1b2c 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -529,8 +529,10 @@ brw_prepare_vertices(struct brw_context *brw) input->buffer = brw->vb.enabled[k]->buffer; input->offset = glarray->Ptr - other->Ptr; - buffer_range_start[k] = MIN2(buffer_range_start[k], start); - buffer_range_end[k] = MAX2(buffer_range_end[k], start + range); + buffer_range_start[input->buffer] = + MIN2(buffer_range_start[input->buffer], start); + buffer_range_end[input->buffer] = + MAX2(buffer_range_end[input->buffer], start + range); break; } } -- 2.5.0.400.gff86faf ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] tgsi: print TGSI_PROPERTY_NEXT_SHADER value as string, not an integer
Print "GEOM" instead of "2", for example. --- src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c b/src/gallium/auxiliary/tgsi/tgsi_dump.c index 0d8bd1b..d59b7ff 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_dump.c +++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c @@ -470,6 +470,9 @@ iter_property( case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER: ENM(prop->u[i].Data, tgsi_fs_coord_pixel_center_names); break; + case TGSI_PROPERTY_NEXT_SHADER: + ENM(prop->u[i].Data, tgsi_processor_type_names); + break; default: SID( prop->u[i].Data ); break; -- 1.9.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/2] tgsi: s/6/PIPE_SHADER_TYPES/ for tgsi_processor_type_names array size
---
src/gallium/auxiliary/tgsi/tgsi_strings.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h
b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index 031d322..9a9362e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.h
@@ -38,7 +38,7 @@ extern "C" {
#endif
-extern const char *tgsi_processor_type_names[6];
+extern const char *tgsi_processor_type_names[PIPE_SHADER_TYPES];
extern const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT];
--
1.9.1
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Re: [Mesa-dev] [PATCH 2/2] tgsi: print TGSI_PROPERTY_NEXT_SHADER value as string, not an integer
Please adjust the parser to read this in as well. On Tue, May 24, 2016 at 7:45 PM, Brian Paul wrote: > Print "GEOM" instead of "2", for example. > --- > src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c > b/src/gallium/auxiliary/tgsi/tgsi_dump.c > index 0d8bd1b..d59b7ff 100644 > --- a/src/gallium/auxiliary/tgsi/tgsi_dump.c > +++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c > @@ -470,6 +470,9 @@ iter_property( >case TGSI_PROPERTY_FS_COORD_PIXEL_CENTER: > ENM(prop->u[i].Data, tgsi_fs_coord_pixel_center_names); > break; > + case TGSI_PROPERTY_NEXT_SHADER: > + ENM(prop->u[i].Data, tgsi_processor_type_names); > + break; >default: > SID( prop->u[i].Data ); > break; > -- > 1.9.1 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: split out libstandalone
From: Rob Clark
Split standalone glsl_compiler into a libstandalone.la and a thin
main.cpp. This way drivers can re-use the glsl standalone frontend in
their own standalone compilers.
Signed-off-by: Rob Clark
---
v2: fix scons build and fix automake hack
src/compiler/Makefile.glsl.am| 16 +-
src/compiler/Makefile.sources| 3 +-
src/compiler/SConscript.glsl | 2 +
src/compiler/glsl/main.cpp | 380 ++
src/compiler/glsl/standalone.cpp | 433 +++
src/compiler/glsl/standalone.h | 51 +
6 files changed, 514 insertions(+), 371 deletions(-)
create mode 100644 src/compiler/glsl/standalone.cpp
create mode 100644 src/compiler/glsl/standalone.h
diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am
index daf98f6..23c2a6b 100644
--- a/src/compiler/Makefile.glsl.am
+++ b/src/compiler/Makefile.glsl.am
@@ -57,7 +57,6 @@ glsl_tests_blob_test_LDADD = \
glsl/libglsl.la
glsl_tests_general_ir_test_SOURCES = \
- glsl/standalone_scaffolding.cpp \
glsl/tests/builtin_variable_test.cpp\
glsl/tests/invalidate_locations_test.cpp\
glsl/tests/general_ir_test.cpp \
@@ -67,6 +66,7 @@ glsl_tests_general_ir_test_CFLAGS = \
glsl_tests_general_ir_test_LDADD = \
$(top_builddir)/src/gtest/libgtest.la \
glsl/libglsl.la \
+ glsl/libstandalone.la \
$(top_builddir)/src/libglsl_util.la \
$(PTHREAD_LIBS)
@@ -93,7 +93,7 @@ glsl_tests_sampler_types_test_LDADD = \
$(top_builddir)/src/libglsl_util.la \
$(PTHREAD_LIBS)
-noinst_LTLIBRARIES += glsl/libglsl.la glsl/libglcpp.la
+noinst_LTLIBRARIES += glsl/libglsl.la glsl/libglcpp.la glsl/libstandalone.la
glsl_libglcpp_la_LIBADD = \
$(top_builddir)/src/util/libmesautil.la
@@ -121,23 +121,29 @@ glsl_libglsl_la_SOURCES = \
$(LIBGLSL_FILES)
-glsl_compiler_SOURCES = \
+glsl_libstandalone_la_SOURCES = \
$(GLSL_COMPILER_CXX_FILES)
-glsl_compiler_LDADD = \
+glsl_libstandalone_la_LIBADD = \
glsl/libglsl.la \
$(top_builddir)/src/libglsl_util.la \
$(top_builddir)/src/util/libmesautil.la \
$(PTHREAD_LIBS)
+glsl_compiler_SOURCES = \
+ glsl/main.cpp
+
+glsl_compiler_LDADD = \
+ glsl/libstandalone.la
+
glsl_glsl_test_SOURCES = \
- glsl/standalone_scaffolding.cpp \
glsl/test.cpp \
glsl/test_optpass.cpp \
glsl/test_optpass.h
glsl_glsl_test_LDADD = \
glsl/libglsl.la \
+ glsl/libstandalone.la \
$(top_builddir)/src/libglsl_util.la \
$(PTHREAD_LIBS)
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index b8f2b49..ebc5953 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -138,7 +138,8 @@ LIBGLSL_FILES = \
GLSL_COMPILER_CXX_FILES = \
glsl/standalone_scaffolding.cpp \
glsl/standalone_scaffolding.h \
- glsl/main.cpp
+ glsl/standalone.cpp \
+ glsl/standalone.h
# libglsl generated sources
LIBGLSL_GENERATED_CXX_FILES = \
diff --git a/src/compiler/SConscript.glsl b/src/compiler/SConscript.glsl
index 43a11d1..0590508 100644
--- a/src/compiler/SConscript.glsl
+++ b/src/compiler/SConscript.glsl
@@ -109,6 +109,8 @@ if env['platform'] == 'windows':
env.Prepend(LIBS = [compiler, glsl])
+compiler_objs += env.StaticObject("glsl/main.cpp")
+
glsl_compiler = env.Program(
target = 'glsl_compiler',
source = compiler_objs,
diff --git a/src/compiler/glsl/main.cpp b/src/compiler/glsl/main.cpp
index d253575..f65b185 100644
--- a/src/compiler/glsl/main.cpp
+++ b/src/compiler/glsl/main.cpp
@@ -20,6 +20,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+
+#include
#include
/** @file main.cpp
@@ -31,255 +33,16 @@
* offline compile GLSL code and examine the resulting GLSL IR.
*/
-#include "ast.h"
-#include "glsl_parser_extras.h"
-#include "ir_optimization.h"
-#include "program.h"
-#include "program/hash_table.h"
-#include "loop_analysis.h"
-#include "standalone_scaffolding.h"
-
-static int glsl_version = 330;
-
-static void
-initialize_context(struct gl_context *ctx, gl_api api)
-{
- initialize_context_to_defaults(ctx, api);
-
- /* The standalone compiler needs to claim support for almost
-* everything in order to compile the built-in functions.
-*/
- ctx->Const.GLSLVersion = glsl_version;
- ctx->Extensions.ARB_ES3_compa
Re: [Mesa-dev] [PATCH 20/21] i965/ir: Make BROADCAST emit an unmasked single-channel move.
On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
wrote:
> Alternatively we could have extended the current semantics to 32-wide
> mode by changing brw_broadcast() to emit multiple indexed MOV
> instructions in the generator copying the selected value to all
> destination registers, but it seemed rather silly to waste EU cycles
> unnecessarily copying the exact same value 32 times in the GRF.
>
It appears as if emit_uniformize in fs_builder sets stride == 0 on the
result the version in vec4_visitor does not. It's probably not needed for
correctness since I think the generator will always take channel 0 anyway,
but we should fix it none the less.
> The vstride change in the Align16 path is required to avoid assertions
> in validate_reg() since the change causes the execution size of the
> MOV and SEL instructions to be equal to the source region width.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 6 ++
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 12 +---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 1 +
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 +
> 4 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 702eb5a..8794d44 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -1080,6 +1080,12 @@ enum opcode {
> /**
> * Pick the channel from its first source register given by the index
> * specified as second source. Useful for variable indexing of
> surfaces.
> +*
> +* Note that because the result of this instruction is by definition
> +* uniform and it can always be splatted to multiple channels using a
> +* scalar regioning mode, only the first channel of the destination
> region
> +* is guaranteed to be updated, which implies that BROADCAST
> instructions
> +* should usually be marked force_writemask_all.
> */
> SHADER_OPCODE_BROADCAST,
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index b11398c..ee7462f 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -3425,6 +3425,10 @@ brw_broadcast(struct brw_codegen *p,
> const bool align1 = brw_inst_access_mode(devinfo, p->current) ==
> BRW_ALIGN_1;
> brw_inst *inst;
>
> + brw_push_insn_state(p);
> + brw_set_default_mask_control(p, BRW_MASK_DISABLE);
> + brw_set_default_exec_size(p, align1 ? BRW_EXECUTE_1 : BRW_EXECUTE_4);
> +
> assert(src.file == BRW_GENERAL_REGISTER_FILE &&
>src.address_mode == BRW_ADDRESS_DIRECT);
>
> @@ -3475,19 +3479,21 @@ brw_broadcast(struct brw_codegen *p,
>*/
> inst = brw_MOV(p,
> brw_null_reg(),
> -stride(brw_swizzle(idx, BRW_SWIZZLE_), 0, 4,
> 1));
> +stride(brw_swizzle(idx, BRW_SWIZZLE_), 4, 4,
> 1));
> brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NONE);
> brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_NZ);
> brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>
> /* and use predicated SEL to pick the right channel. */
> inst = brw_SEL(p, dst,
> -stride(suboffset(src, 4), 0, 4, 1),
> -stride(src, 0, 4, 1));
> +stride(suboffset(src, 4), 4, 4, 1),
> +stride(src, 4, 4, 1));
> brw_inst_set_pred_control(devinfo, inst, BRW_PREDICATE_NORMAL);
> brw_inst_set_flag_reg_nr(devinfo, inst, 1);
>}
> }
> +
> + brw_pop_insn_state(p);
> }
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 6421870..804c639 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -2017,6 +2017,7 @@ fs_generator::generate_code(const cfg_t *cfg, int
> dispatch_width)
> break;
>
>case SHADER_OPCODE_BROADCAST:
> + assert(inst->force_writemask_all);
> brw_broadcast(p, dst, src[0], src[1]);
> break;
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index baf4422..bb0254e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -1886,6 +1886,7 @@ generate_code(struct brw_codegen *p,
> break;
>
>case SHADER_OPCODE_BROADCAST:
> + assert(inst->force_writemask_all);
> brw_broadcast(p, dst, src[0], src[1]);
> break;
>
> --
> 2.7.3
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
Re: [Mesa-dev] [PATCH] i965: Add missing types to type_sz().
Reviewed-by: Jordan Justen
On 2016-05-24 15:12:25, Matt Turner wrote:
> Coverity warns in multiple places about the potential for division by
> zero, caused by this function's default case.
>
> Cc: Francisco Jerez
> ---
> src/mesa/drivers/dri/i965/brw_reg.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
> b/src/mesa/drivers/dri/i965/brw_reg.h
> index b0ef94e..be23678 100644
> --- a/src/mesa/drivers/dri/i965/brw_reg.h
> +++ b/src/mesa/drivers/dri/i965/brw_reg.h
> @@ -292,15 +292,19 @@ type_sz(unsigned type)
> case BRW_REGISTER_TYPE_UD:
> case BRW_REGISTER_TYPE_D:
> case BRW_REGISTER_TYPE_F:
> + case BRW_REGISTER_TYPE_VF:
>return 4;
> case BRW_REGISTER_TYPE_UW:
> case BRW_REGISTER_TYPE_W:
> + case BRW_REGISTER_TYPE_UV:
> + case BRW_REGISTER_TYPE_V:
> + case BRW_REGISTER_TYPE_HF:
>return 2;
> case BRW_REGISTER_TYPE_UB:
> case BRW_REGISTER_TYPE_B:
>return 1;
> default:
> - return 0;
> + unreachable("not reached");
> }
> }
>
> --
> 2.7.3
>
> ___
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Re: [Mesa-dev] [PATCH 00/21] i965: Scalar back-end support for SIMD32, part 2.
I sent a few fairly minor comments that I'd like to see addressed. Other than those, Reviewed-by: Jason Ekstrand On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez wrote: > This should be enough to get the FS generator emitting 32-wide code > for at least compute shaders. Most of the work in this series is > about fixing the current codegen infrastructure to support arbitrary > channel group controls and execution sizes (other than dispatch_width > that is), and extending several virtual opcodes to handle SIMD32 (only > the changes for opcodes that can potentially be used in compute > shaders are included here). > > Enjoy. > > [PATCH 01/21] i965/eu: Define alternative interface for setting > compression and group controls. > [PATCH 02/21] i965/eu: Fix a bunch of compression control bugs in the > generator. > [PATCH 03/21] i965/fs: No need to set compression control at the top of > generate_code(). > [PATCH 04/21] i965/fs: Simplify per-instruction compression control setup > in generator. > [PATCH 05/21] i965/fs: Pass the compression mode to brw_reg_from_fs_reg(). > [PATCH 06/21] i965/fs: Extend region width calculation to allow arbitrary > execution sizes. > [PATCH 07/21] i965/eu: Stop using p->compressed to specify the exec size > of control flow instructions. > [PATCH 08/21] i965/fs: Pass current execution size to brw_IF() and > brw_DO(). > [PATCH 09/21] i965/fs: No need to reset predicate control after emitting > some instructions. > [PATCH 10/21] i965/eu: Use current exec size instead of p->compressed in > surface message generation. > [PATCH 11/21] i965/eu: Remove brw_codegen::compressed and > ::compressed_stack. > [PATCH 12/21] i965/fs: Clean up remaining uses of dispatch_width in the > generator. > [PATCH 13/21] i965/eu: Consider QtrCtrl 3Q-4Q in typed surface message > descriptor setup. > [PATCH 14/21] i965/eu: Set execution size explicitly for memory fence send > message. > [PATCH 15/21] i965/eu: Fix Gen7+ DP scratch message size calculation on > Gen7. > [PATCH 16/21] i965/fs: Implement scratch reads and writes of 4 GRFs at a > time. > [PATCH 17/21] i965/fs: Lower 32-wide scratch writes in the generator. > [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 > to FIND_LIVE_CHANNEL. > [PATCH 19/21] i965/fs: Allow specifying arbitrary quarter control to > FIND_LIVE_CHANNEL. > [PATCH 20/21] i965/ir: Make BROADCAST emit an unmasked single-channel move. > [PATCH 21/21] i965/fs: Expose arbitrary channel execution groups to the IR. > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 21/21] i965/fs: Expose arbitrary channel execution groups to the IR.
On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
wrote:
> This generalizes the current fs_inst::force_sechalf flag to allow
> specifying channel enable groups other than 0 or 8. At some point it
> will likely make sense to fix the vec4 generator to support arbitrary
> execution groups and then move the definition of fs_inst::group into
> backend_instruction (e.g. so we can do FP64 in the VEC4 back-end).
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 20
>
> src/mesa/drivers/dri/i965/brw_fs_builder.h| 14 +++---
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 4 ++--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 7 ---
> src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_ir_fs.h | 20
> +---
> 6 files changed, 35 insertions(+), 32 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index a59cd3c..92caeaa 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -3638,7 +3638,7 @@ fs_visitor::lower_integer_multiplication()
> mul->src[1].stride *= 2;
>
> } else if (devinfo->gen == 7 && !devinfo->is_haswell &&
> -inst->force_sechalf) {
> +inst->group > 0) {
> /* Among other things the quarter control bits influence which
> * accumulator register is used by the hardware for
> instructions
> * that access the accumulator implicitly (e.g. MACH). A
> @@ -3655,7 +3655,7 @@ fs_visitor::lower_integer_multiplication()
> * to get the result masked correctly according to the current
> * channel enables.
> */
> -mach->force_sechalf = false;
> +mach->group = 0;
> mach->force_writemask_all = true;
> mach->dst = ibld.vgrf(inst->dst.type);
> ibld.MOV(inst->dst, mach->dst);
> @@ -3791,8 +3791,8 @@ lower_fb_write_logical_send(const fs_builder &bld,
> fs_inst *inst,
>sample_mask.stride *= 2;
>
>bld.exec_all().annotate("FB write oMask")
> - .MOV(half(retype(sources[length], BRW_REGISTER_TYPE_UW),
> - inst->force_sechalf),
> + .MOV(horiz_offset(retype(sources[length], BRW_REGISTER_TYPE_UW),
> + inst->group),
>sample_mask);
>length++;
> }
> @@ -5017,10 +5017,10 @@ fs_visitor::lower_simd_width()
>* execution size of the builder to the highest of both for now
> so
>* we're sure that both cases can be handled.
>*/
> + const unsigned max_width = MAX2(inst->exec_size, lower_width);
> const fs_builder ibld = bld.at(block, inst)
> .exec_all(inst->force_writemask_all)
> -.group(MAX2(inst->exec_size,
> lower_width),
> - inst->force_sechalf);
> +.group(max_width, inst->group /
> max_width);
>
> /* Split the copies in chunks of the execution width of either
> the
>* original or the lowered instruction, whichever is lower.
> @@ -5352,12 +5352,8 @@ fs_visitor::dump_instruction(backend_instruction
> *be_inst, FILE *file)
> if (inst->force_writemask_all)
>fprintf(file, "NoMask ");
>
> - if (dispatch_width == 16 && inst->exec_size == 8) {
> - if (inst->force_sechalf)
> - fprintf(file, "2ndhalf ");
> - else
> - fprintf(file, "1sthalf ");
> - }
> + if (inst->exec_size != dispatch_width)
> + fprintf(file, "group%d ", inst->group);
>
> fprintf(file, "\n");
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
> b/src/mesa/drivers/dri/i965/brw_fs_builder.h
> index b50dda4..c1d13a2 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
> @@ -72,7 +72,7 @@ namespace brw {
>fs_builder(backend_shader *shader, bblock_t *block, fs_inst *inst) :
> shader(shader), block(block), cursor(inst),
> _dispatch_width(inst->exec_size),
> - _group(inst->force_sechalf ? 8 : 0),
> + _group(inst->group),
> force_writemask_all(inst->force_writemask_all)
>{
> annotation.str = inst->annotation;
> @@ -168,6 +168,15 @@ namespace brw {
>}
>
>/**
> + * Get the channel group in use.
> + */
> + unsigned
> + group() const
> + {
> + return _group;
> + }
> +
> + /**
> * Allocate a virtual register of natural vector size (one for this
> IR)
> * and SIMD width. \p n gives the amount of space to allocate in
> * dispatch_width units (which is just enough space for one logical
> @@ -353,9 +362,8 @@ namespace brw {
> assert(inst->exec_size
[Mesa-dev] [PATCH] mesa/program_interface_query: fix transform feedback varyings.
From: Dave Airlie
The spec says gl_NextBuffer and gl_SkipComponents need to be
returned to userspace in the program interface queries.
We currently throw those away, this requires a complete piglit
run to make sure no drivers fallover due to the extra varyings.
This fixes:
GL45-CTS.program_interface_query.transform-feedback-built-in
Signed-off-by: Dave Airlie
---
src/compiler/glsl/link_varyings.cpp | 81 +
src/mesa/main/shader_query.cpp | 2 +-
2 files changed, 48 insertions(+), 35 deletions(-)
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index a7667a4..aa9b08b 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -812,15 +812,20 @@ tfeedback_decl::store(struct gl_context *ctx, struct
gl_shader_program *prog,
const unsigned max_outputs, bool *explicit_stride,
bool has_xfb_qualifiers) const
{
- assert(!this->next_buffer_separator);
-
+ unsigned xfb_offset = 0;
+ unsigned size = this->size;
/* Handle gl_SkipComponents. */
if (this->skip_components) {
info->Buffers[buffer].Stride += this->skip_components;
- return true;
+ size = this->skip_components;
+ goto store_varying;
+ }
+
+ if (this->next_buffer_separator) {
+ size = 0;
+ goto store_varying;
}
- unsigned xfb_offset = 0;
if (has_xfb_qualifiers) {
xfb_offset = this->offset / 4;
} else {
@@ -828,37 +833,39 @@ tfeedback_decl::store(struct gl_context *ctx, struct
gl_shader_program *prog,
}
info->Varyings[info->NumVarying].Offset = xfb_offset * 4;
- unsigned location = this->location;
- unsigned location_frac = this->location_frac;
- unsigned num_components = this->num_components();
- while (num_components > 0) {
- unsigned output_size = MIN2(num_components, 4 - location_frac);
- assert((info->NumOutputs == 0 && max_outputs == 0) ||
- info->NumOutputs < max_outputs);
+ {
+ unsigned location = this->location;
+ unsigned location_frac = this->location_frac;
+ unsigned num_components = this->num_components();
+ while (num_components > 0) {
+ unsigned output_size = MIN2(num_components, 4 - location_frac);
+ assert((info->NumOutputs == 0 && max_outputs == 0) ||
+info->NumOutputs < max_outputs);
+
+ /* From the ARB_enhanced_layouts spec:
+ *
+ *"If such a block member or variable is not written during a
shader
+ *invocation, the buffer contents at the assigned offset will be
+ *undefined. Even if there are no static writes to a variable or
+ *member that is assigned a transform feedback offset, the space
is
+ *still allocated in the buffer and still affects the stride."
+ */
+ if (this->is_varying_written()) {
+info->Outputs[info->NumOutputs].ComponentOffset = location_frac;
+info->Outputs[info->NumOutputs].OutputRegister = location;
+info->Outputs[info->NumOutputs].NumComponents = output_size;
+info->Outputs[info->NumOutputs].StreamId = stream_id;
+info->Outputs[info->NumOutputs].OutputBuffer = buffer;
+info->Outputs[info->NumOutputs].DstOffset = xfb_offset;
+++info->NumOutputs;
+ }
+ info->Buffers[buffer].Stream = this->stream_id;
+ xfb_offset += output_size;
- /* From the ARB_enhanced_layouts spec:
- *
- *"If such a block member or variable is not written during a shader
- *invocation, the buffer contents at the assigned offset will be
- *undefined. Even if there are no static writes to a variable or
- *member that is assigned a transform feedback offset, the space is
- *still allocated in the buffer and still affects the stride."
- */
- if (this->is_varying_written()) {
- info->Outputs[info->NumOutputs].ComponentOffset = location_frac;
- info->Outputs[info->NumOutputs].OutputRegister = location;
- info->Outputs[info->NumOutputs].NumComponents = output_size;
- info->Outputs[info->NumOutputs].StreamId = stream_id;
- info->Outputs[info->NumOutputs].OutputBuffer = buffer;
- info->Outputs[info->NumOutputs].DstOffset = xfb_offset;
- ++info->NumOutputs;
+ num_components -= output_size;
+ location++;
+ location_frac = 0;
}
- info->Buffers[buffer].Stream = this->stream_id;
- xfb_offset += output_size;
-
- num_components -= output_size;
- location++;
- location_frac = 0;
}
if (explicit_stride && explicit_stride[buffer]) {
@@ -903,10 +910,11 @@ tfeedback_decl::store(struct gl_context *ctx, struct
gl_shader_program *prog,
return false;
}
+store_varying:
info->Varyings[info->NumVarying].Name = ralloc_strdup(prog,
[Mesa-dev] [PATCH] gallium/radeon: add the kernel version into the renderer string
From: Marek Olšák
Example:
Gallium 0.4 on AMD TONGA (DRM 3.2.0 / 4.5.0, LLVM 3.9.0)
My kernel version is pretty long already (4.5.0-amd-01025-g32791c1)
and adding "kernel" into the string would make too it long for glxinfo
to display.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 8d9c5a5..c00e584 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -37,6 +37,7 @@
#include "vl/vl_video_buffer.h"
#include "radeon/radeon_video.h"
#include
+#include
#ifndef HAVE_LLVM
#define HAVE_LLVM 0
@@ -938,10 +939,15 @@ struct pipe_resource *r600_resource_create_common(struct
pipe_screen *screen,
bool r600_common_screen_init(struct r600_common_screen *rscreen,
struct radeon_winsys *ws)
{
- char llvm_string[32] = {};
+ char llvm_string[32] = {}, kernel_version[128] = {};
+ struct utsname uname_data;
ws->query_info(ws, &rscreen->info);
+ if (uname(&uname_data) == 0)
+ snprintf(kernel_version, sizeof(kernel_version),
+" / %s", uname_data.release);
+
#if HAVE_LLVM
snprintf(llvm_string, sizeof(llvm_string),
", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
@@ -949,10 +955,10 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
#endif
snprintf(rscreen->renderer_string, sizeof(rscreen->renderer_string),
-"%s (DRM %i.%i.%i%s)",
+"%s (DRM %i.%i.%i%s%s)",
r600_get_chip_name(rscreen), rscreen->info.drm_major,
rscreen->info.drm_minor, rscreen->info.drm_patchlevel,
-llvm_string);
+kernel_version, llvm_string);
rscreen->b.get_name = r600_get_name;
rscreen->b.get_vendor = r600_get_vendor;
--
2.7.4
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Re: [Mesa-dev] [PATCH 18/21] i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHANNEL.
On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
wrote:
> Due to a Gen7-specific hardware bug native 32-wide instructions get
> the lower 16 bits of the execution mask applied incorrectly to both
> halves of the instruction, so the MOV trick we currently use wouldn't
> work. Instead emit multiple 16-wide MOV instructions in 32-wide mode
> in order to cover the whole execution mask.
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c | 25 +
> 1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index af7caed..d36877c 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -3330,6 +3330,7 @@ void
> brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst)
> {
> const struct brw_device_info *devinfo = p->devinfo;
> + const unsigned exec_size = 1 << brw_inst_exec_size(devinfo,
> p->current);
> brw_inst *inst;
>
> assert(devinfo->gen >= 7);
> @@ -3359,15 +3360,23 @@ brw_find_live_channel(struct brw_codegen *p,
> struct brw_reg dst)
>
> brw_MOV(p, flag, brw_imm_ud(0));
>
> - /* Run a 16-wide instruction returning zero with execution
> masking
> - * and a conditional modifier enabled in order to get the current
> - * execution mask in f1.0.
> + /* Run enough instructions returning zero with execution masking
> and
> + * a conditional modifier enabled in order to get the full
> execution
> + * mask in f1.0. We could use a single 32-wide move here if it
> + * weren't because of the hardware bug that causes channel
> enables to
> + * be applied incorrectly to the second half of 32-wide
> instructions
> + * on Gen7.
>*/
> - inst = brw_MOV(p, brw_null_reg(), brw_imm_ud(0));
> - brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_16);
> - brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
> - brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
> - brw_inst_set_flag_reg_nr(devinfo, inst, 1);
> + const unsigned lower_size = MIN2(16, exec_size);
> + for (unsigned i = 0; i < exec_size / lower_size; i++) {
> +inst = brw_MOV(p, retype(brw_null_reg(),
> BRW_REGISTER_TYPE_UW),
> + brw_imm_uw(0));
>
Is there a reason this is changing from D to UW?
> +brw_inst_set_mask_control(devinfo, inst, BRW_MASK_ENABLE);
> +brw_inst_set_group(devinfo, inst, lower_size * i);
> +brw_inst_set_cond_modifier(devinfo, inst, BRW_CONDITIONAL_Z);
> +brw_inst_set_flag_reg_nr(devinfo, inst, 1);
> +brw_inst_set_exec_size(devinfo, inst, cvt(lower_size) - 1);
> + }
>
> brw_FBL(p, vec1(dst), flag);
>}
> --
> 2.7.3
>
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Re: [Mesa-dev] [PATCH] mesa/extensions: Fix ES1 extension reporting
Reviewed-by: Ian Romanick On 05/24/2016 03:39 PM, Nanley Chery wrote: > From: Nanley Chery > > Commit eda15abd84af575d3bde432e2163e30d743a7c87 , unintentionally > advertised these extensions in ES1 contexts. Undo this error. > > Signed-off-by: Nanley Chery > --- > src/mesa/main/extensions_table.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/main/extensions_table.h > b/src/mesa/main/extensions_table.h > index a809023..9ae8915 100644 > --- a/src/mesa/main/extensions_table.h > +++ b/src/mesa/main/extensions_table.h > @@ -190,7 +190,7 @@ EXT(EXT_blend_minmax, > EXT_blend_minmax > EXT(EXT_blend_subtract , dummy_true > , GLL, x , x , x , 1995) > EXT(EXT_buffer_storage , ARB_buffer_storage > , x , x , x , 31, 2015) > EXT(EXT_clip_cull_distance , ARB_cull_distance > , x , x , x , 30, 2016) > -EXT(EXT_color_buffer_float , dummy_true > , x , x , ES1, 30, 2013) > +EXT(EXT_color_buffer_float , dummy_true > , x , x , x , 30, 2013) > EXT(EXT_compiled_vertex_array , dummy_true > , GLL, x , x , x , 1996) > EXT(EXT_copy_image , OES_copy_image > , x , x , x , 30, 2014) > EXT(EXT_copy_texture, dummy_true > , GLL, x , x , x , 1995) > @@ -365,7 +365,7 @@ EXT(OES_texture_half_float_linear , > OES_texture_half_float_linear > EXT(OES_texture_mirrored_repeat , dummy_true > , x , x , ES1, x , 2005) > EXT(OES_texture_npot, ARB_texture_non_power_of_two > , x , x , ES1, ES2, 2005) > EXT(OES_texture_stencil8, ARB_texture_stencil8 > , x , x , x , 30, 2014) > -EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample > , x , x , ES1, 31, 2014) > +EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample > , x , x , x , 31, 2014) > EXT(OES_vertex_array_object , dummy_true > , x , x , ES1, ES2, 2010) > > EXT(S3_s3tc , ANGLE_texture_compression_dxt > , GLL, GLC, x , x , 1999) > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] egl: Check if API is supported when using eglBindAPI.
According to the EGL specifications before binding an API
we must check whether it's supported first. If not eglBindAPI
should return EGL_FALSE and generate a EGL_BAD_PARAMETER error.
Signed-off-by: Plamena Manolova
---
src/egl/main/eglapi.c | 65 +++
src/egl/main/eglcurrent.h | 11 +---
src/egl/main/egldisplay.c | 5
src/egl/main/egldisplay.h | 1 +
4 files changed, 72 insertions(+), 10 deletions(-)
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index be2c90f..2d03ab4 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -1196,6 +1196,61 @@ eglGetError(void)
}
+static bool
+_eglDisplaySupportsApi(_EGLDisplay *dpy, EGLenum api)
+{
+ if (!dpy->Initialized) {
+ return false;
+ }
+
+ switch (api) {
+ case EGL_OPENGL_API:
+ return !!(dpy->ClientAPIs & EGL_OPENGL_BIT);
+ case EGL_OPENGL_ES_API:
+ return !!(dpy->ClientAPIs & EGL_OPENGL_ES_BIT) ||
+ !!(dpy->ClientAPIs & EGL_OPENGL_ES2_BIT) ||
+ !!(dpy->ClientAPIs & EGL_OPENGL_ES3_BIT_KHR);
+ case EGL_OPENVG_API:
+ return !!(dpy->ClientAPIs & EGL_OPENVG_BIT);
+ }
+
+ return false;
+}
+
+
+/**
+ * Return true if a client API enum is recognized.
+ */
+static bool
+_eglIsApiValid(EGLenum api)
+{
+ _EGLDisplay *dpy = _eglGlobal.DisplayList;
+ _EGLThreadInfo *current_thread = _eglGetCurrentThread();
+
+ if (api != EGL_OPENGL_API && api != EGL_OPENGL_ES_API &&
+ api != EGL_OPENVG_API) {
+ return false;
+ }
+
+ while (dpy) {
+ _EGLThreadInfo *thread = dpy->ThreadList;
+
+ while (thread) {
+ if (thread == current_thread) {
+if (_eglDisplaySupportsApi(dpy, api))
+ return true;
+ }
+
+ thread = thread->Next;
+ }
+
+ dpy = dpy->Next;
+ }
+
+ return false;
+}
+
+
/**
** EGL 1.2
**/
@@ -1211,6 +1266,16 @@ eglGetError(void)
* eglWaitNative()
* See section 3.7 "Rendering Context" in the EGL specification for details.
*/
+
+ /**
+ * Section 3.7 (Rendering Contexts) of the EGL 1.5 spec says:
+ *
+ * "api must specify one of the supported client APIs, either
+ * EGL_OPENGL_API, EGL_OPENGL_ES_API, or EGL_OPENVG_API... If api
+ * is not one of the values specified above, or if the client API
+ * specified by api is not supported by the implementation, an
+ * EGL_BAD_PARAMETER error is generated."
+ */
EGLBoolean EGLAPIENTRY
eglBindAPI(EGLenum api)
{
diff --git a/src/egl/main/eglcurrent.h b/src/egl/main/eglcurrent.h
index 1e386ac..6c203be 100644
--- a/src/egl/main/eglcurrent.h
+++ b/src/egl/main/eglcurrent.h
@@ -56,6 +56,7 @@ extern "C" {
*/
struct _egl_thread_info
{
+ _EGLThreadInfo *Next; /* used to link threads */
EGLint LastError;
_EGLContext *CurrentContexts[_EGL_API_NUM_APIS];
/* use index for fast access to current context */
@@ -64,16 +65,6 @@ struct _egl_thread_info
/**
- * Return true if a client API enum is recognized.
- */
-static inline EGLBoolean
-_eglIsApiValid(EGLenum api)
-{
- return (api >= _EGL_API_FIRST_API && api <= _EGL_API_LAST_API);
-}
-
-
-/**
* Convert a client API enum to an index, for use by thread info.
* The client API enum is assumed to be valid.
*/
diff --git a/src/egl/main/egldisplay.c b/src/egl/main/egldisplay.c
index f6db03a..907a607 100644
--- a/src/egl/main/egldisplay.c
+++ b/src/egl/main/egldisplay.c
@@ -240,6 +240,7 @@ _EGLDisplay *
_eglFindDisplay(_EGLPlatformType plat, void *plat_dpy)
{
_EGLDisplay *dpy;
+ _EGLThreadInfo *thread = _eglGetCurrentThread();
if (plat == _EGL_INVALID_PLATFORM)
return NULL;
@@ -265,9 +266,13 @@ _eglFindDisplay(_EGLPlatformType plat, void *plat_dpy)
/* add to the display list */
dpy->Next = _eglGlobal.DisplayList;
_eglGlobal.DisplayList = dpy;
+ dpy->ThreadList = NULL;
}
}
+ thread->Next = dpy->ThreadList;
+ dpy->ThreadList = thread;
+
mtx_unlock(_eglGlobal.Mutex);
return dpy;
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 6bfc858..8a730ed 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -140,6 +140,7 @@ struct _egl_display
_EGLPlatformType Platform; /**< The type of the platform display */
void *PlatformDisplay; /**< A pointer to the platform display */
+ _EGLThreadInfo *ThreadList;/**< A pointer to the thread the display was
created form */
_EGLDriver *Driver;/**< Matched driver of the display */
EGLBoolean Initialized;/**< True if the display is initialized */
--
2.8.3.windows.1
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Re: [Mesa-dev] [PATCH] mesa/extensions: Fix ES1 extension reporting
Reviewed-by: Ilia Mirkin On Tue, May 24, 2016 at 6:39 PM, Nanley Chery wrote: > From: Nanley Chery > > Commit eda15abd84af575d3bde432e2163e30d743a7c87 , unintentionally > advertised these extensions in ES1 contexts. Undo this error. > > Signed-off-by: Nanley Chery > --- > src/mesa/main/extensions_table.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/main/extensions_table.h > b/src/mesa/main/extensions_table.h > index a809023..9ae8915 100644 > --- a/src/mesa/main/extensions_table.h > +++ b/src/mesa/main/extensions_table.h > @@ -190,7 +190,7 @@ EXT(EXT_blend_minmax, > EXT_blend_minmax > EXT(EXT_blend_subtract , dummy_true > , GLL, x , x , x , 1995) > EXT(EXT_buffer_storage , ARB_buffer_storage > , x , x , x , 31, 2015) > EXT(EXT_clip_cull_distance , ARB_cull_distance > , x , x , x , 30, 2016) > -EXT(EXT_color_buffer_float , dummy_true > , x , x , ES1, 30, 2013) > +EXT(EXT_color_buffer_float , dummy_true > , x , x , x , 30, 2013) > EXT(EXT_compiled_vertex_array , dummy_true > , GLL, x , x , x , 1996) > EXT(EXT_copy_image , OES_copy_image > , x , x , x , 30, 2014) > EXT(EXT_copy_texture, dummy_true > , GLL, x , x , x , 1995) > @@ -365,7 +365,7 @@ EXT(OES_texture_half_float_linear , > OES_texture_half_float_linear > EXT(OES_texture_mirrored_repeat , dummy_true > , x , x , ES1, x , 2005) > EXT(OES_texture_npot, ARB_texture_non_power_of_two > , x , x , ES1, ES2, 2005) > EXT(OES_texture_stencil8, ARB_texture_stencil8 > , x , x , x , 30, 2014) > -EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample > , x , x , ES1, 31, 2014) > +EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample > , x , x , x , 31, 2014) > EXT(OES_vertex_array_object , dummy_true > , x , x , ES1, ES2, 2010) > > EXT(S3_s3tc , ANGLE_texture_compression_dxt > , GLL, GLC, x , x , 1999) > -- > 2.8.2 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa/extensions: Fix ES1 extension reporting
From: Nanley Chery Commit eda15abd84af575d3bde432e2163e30d743a7c87 , unintentionally advertised these extensions in ES1 contexts. Undo this error. Signed-off-by: Nanley Chery --- src/mesa/main/extensions_table.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h index a809023..9ae8915 100644 --- a/src/mesa/main/extensions_table.h +++ b/src/mesa/main/extensions_table.h @@ -190,7 +190,7 @@ EXT(EXT_blend_minmax, EXT_blend_minmax EXT(EXT_blend_subtract , dummy_true , GLL, x , x , x , 1995) EXT(EXT_buffer_storage , ARB_buffer_storage , x , x , x , 31, 2015) EXT(EXT_clip_cull_distance , ARB_cull_distance , x , x , x , 30, 2016) -EXT(EXT_color_buffer_float , dummy_true , x , x , ES1, 30, 2013) +EXT(EXT_color_buffer_float , dummy_true , x , x , x , 30, 2013) EXT(EXT_compiled_vertex_array , dummy_true , GLL, x , x , x , 1996) EXT(EXT_copy_image , OES_copy_image , x , x , x , 30, 2014) EXT(EXT_copy_texture, dummy_true , GLL, x , x , x , 1995) @@ -365,7 +365,7 @@ EXT(OES_texture_half_float_linear , OES_texture_half_float_linear EXT(OES_texture_mirrored_repeat , dummy_true , x , x , ES1, x , 2005) EXT(OES_texture_npot, ARB_texture_non_power_of_two , x , x , ES1, ES2, 2005) EXT(OES_texture_stencil8, ARB_texture_stencil8 , x , x , x , 30, 2014) -EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample , x , x , ES1, 31, 2014) +EXT(OES_texture_storage_multisample_2d_array, ARB_texture_multisample , x , x , x , 31, 2014) EXT(OES_vertex_array_object , dummy_true , x , x , ES1, ES2, 2010) EXT(S3_s3tc , ANGLE_texture_compression_dxt , GLL, GLC, x , x , 1999) -- 2.8.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 12/21] i965/fs: Clean up remaining uses of dispatch_width in the generator.
Does this mean we can delete the field from brw_fs_generator?
On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
wrote:
> Most of these are bugs because the intended execution size of an
> instruction and the dispatch width of the shader aren't necessarily
> the same (especially in SIMD32 programs).
> ---
> src/mesa/drivers/dri/i965/brw_eu.h | 1 -
> src/mesa/drivers/dri/i965/brw_eu_emit.c| 3 +--
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 13 +++--
> 3 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
> b/src/mesa/drivers/dri/i965/brw_eu.h
> index 91e3401..b057f17 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu.h
> +++ b/src/mesa/drivers/dri/i965/brw_eu.h
> @@ -281,7 +281,6 @@ void brw_svb_write(struct brw_codegen *p,
> bool send_commit_msg);
>
> void brw_fb_WRITE(struct brw_codegen *p,
> - int dispatch_width,
>struct brw_reg payload,
>struct brw_reg implied_header,
>unsigned msg_control,
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 10cbbe8..ff8e207 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -2342,7 +2342,6 @@ void brw_oword_block_read(struct brw_codegen *p,
>
>
> void brw_fb_WRITE(struct brw_codegen *p,
> - int dispatch_width,
>struct brw_reg payload,
>struct brw_reg implied_header,
>unsigned msg_control,
> @@ -2358,7 +2357,7 @@ void brw_fb_WRITE(struct brw_codegen *p,
> unsigned msg_type;
> struct brw_reg dest, src0;
>
> - if (dispatch_width == 16)
> + if (brw_inst_exec_size(devinfo, p->current) >= BRW_EXECUTE_16)
>dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
> else
>dest = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index 71ac730..9751926 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -229,7 +229,6 @@ fs_generator::fire_fb_write(fs_inst *inst,
>
>
> brw_fb_WRITE(p,
> -dispatch_width,
> payload,
> implied_header,
> msg_control,
> @@ -547,7 +546,7 @@ fs_generator::generate_linterp(fs_inst *inst,
> * See also: emit_interpolation_setup_gen4().
> */
> struct brw_reg delta_x = src[0];
> - struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
> + struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
> struct brw_reg interp = src[1];
>
> if (devinfo->has_pln &&
> @@ -1206,10 +1205,11 @@
> fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
> uint32_t surf_index = index.ud;
>
> uint32_t simd_mode, rlen, msg_type;
> - if (dispatch_width == 16) {
> + if (inst->exec_size == 16) {
>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
>rlen = 8;
> } else {
> + assert(inst->exec_size == 8);
>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
>rlen = 4;
> }
> @@ -1267,11 +1267,12 @@
> fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
> assert(index.type == BRW_REGISTER_TYPE_UD);
>
> uint32_t simd_mode, rlen, mlen;
> - if (dispatch_width == 16) {
> + if (inst->exec_size == 16) {
>mlen = 2;
>rlen = 8;
>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
> } else {
> + assert(inst->exec_size == 8);
>mlen = 1;
>rlen = 4;
>simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
> @@ -1407,9 +1408,9 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
>src0.type == BRW_REGISTER_TYPE_UD);
>
> struct brw_reg reg = stride(src1, 1, 4, 0);
> - if (devinfo->gen >= 8 || dispatch_width == 8) {
> + if (devinfo->gen >= 8 || inst->exec_size == 8) {
>brw_ADD(p, dst, src0, reg);
> - } else if (dispatch_width == 16) {
> + } else if (inst->exec_size == 16) {
>brw_push_insn_state(p);
>brw_set_default_exec_size(p, BRW_EXECUTE_8);
>brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
> --
> 2.7.3
>
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Re: [Mesa-dev] [PATCH 01/21] i965/eu: Define alternative interface for setting compression and group controls.
On Tue, May 24, 2016 at 2:05 AM, Michael Schellenberger <
mschellenbergerco...@googlemail.com> wrote:
> Hi curro,
>
> Am 24.05.2016 um 09:18 schrieb Francisco Jerez:
> > This implements some simple helper functions that can be used to
> > specify the group of channel enable signals and compression enable
> > that apply to a brw_inst instruction.
> >
> > It's intended to replace brw_set_default_compression_control
> > eventually because the current interface has a number of shortcomings
> > inherited from the Gen-4-5-centric representation of compression and
> > group controls as a single non-orthogonal enum: On the one hand it
> > doesn't work for specifying arbitrary group controls other than 1Q and
> > 2Q, which are frequently useful in SIMD32 and FP64 programs. On the
> > other hand the current interface forces you to update the compression
> > *and* group controls simultaneously, which has been the source of a
> > number of generator bugs (a bunch of them fixed in this series),
> > because in many cases we would end up resetting the group controls to
> > zero inadvertently even though everything we wanted to do was disable
> > instruction compression -- The latter seems especially unfortunate on
> > Gen6+ hardware which have no explicit compression control, so we would
> > end up bashing the quarter control field of the instruction for no
> > benefit.
> >
> > Instead of a single function that updates both at the same time
> > introduce separate interfaces to update one or the other independently
> > preserving the current value of the other (which typically comes from
> > the back-end IR so it has to be respected).
> > ---
> > src/mesa/drivers/dri/i965/brw_eu.c | 69
> ++
> > src/mesa/drivers/dri/i965/brw_eu.h | 6
> > 2 files changed, 75 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
> b/src/mesa/drivers/dri/i965/brw_eu.c
> > index 48c8439..f1161d2 100644
> > --- a/src/mesa/drivers/dri/i965/brw_eu.c
> > +++ b/src/mesa/drivers/dri/i965/brw_eu.c
> > @@ -218,6 +218,75 @@ brw_set_default_compression_control(struct
> brw_codegen *p,
> > }
> > }
> >
> > +/**
> > + * Enable or disable instruction compression on the given instruction
> leaving
> > + * the currently selected channel enable group untouched.
> > + */
> > +void
> > +brw_inst_set_compression(const struct brw_device_info *devinfo,
> > + brw_inst *inst, bool on)
> > +{
> > + if (devinfo->gen >= 6) {
> > + /* No-op, the EU will figure out for us whether the instruction
> needs to
> > + * be compressed.
> > + */
> > + } else {
> > + /* The channel group and compression controls are non-orthogonal,
> there
> > + * are two possible representations for uncompressed instructions
> and we
> > + * may need to preserve the current one to avoid changing the
> selected
> > + * channel group inadvertently.
> > + */
> > + if (on)
> > + brw_inst_set_qtr_control(devinfo, inst,
> BRW_COMPRESSION_COMPRESSED);
> > + else if (brw_inst_qtr_control(devinfo, inst)
> > + == BRW_COMPRESSION_COMPRESSED)
> > + brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
> > + }
> > +}
> > +
> > +void
> > +brw_set_default_compression(struct brw_codegen *p, bool on)
> > +{
> > + brw_inst_set_compression(p->devinfo, p->current, on);
> > +}
> > +
> > +/**
> > + * Apply the range of channel enable signals given by
> > + * [group, group + exec_size[ to the instruction passed as argument.
> > + */
> > +void
> > +brw_inst_set_group(const struct brw_device_info *devinfo,
> > + brw_inst *inst, unsigned group)
> > +{
> > + if (devinfo->gen >= 7) {
> > + assert(group % 4 == 0 && group < 32);
> > + brw_inst_set_qtr_control(devinfo, inst, group / 8);
> > + brw_inst_set_nib_control(devinfo, inst, group / 4 % 2);
>
Mind adding parentheses around "group / 4" so the reader doesn't have to
think about operator precedence between / and %.
> > +
> > + } else if (devinfo->gen >= 6) {
> Could you make that ==6, so the two conditions do not overlap?
>
That's not a bad idea.
> --Michael
> > + assert(group % 8 == 0 && group < 32);
> > + brw_inst_set_qtr_control(devinfo, inst, group / 8);
> > +
> > + } else {
> > + assert(group % 8 == 0 && group < 16);
> > + /* The channel group and compression controls are non-orthogonal,
> there
> > + * are two possible representations for group zero and we may
> need to
> > + * preserve the current one to avoid changing the selected
> compression
> > + * enable inadvertently.
> > + */
> > + if (group == 8)
> > + brw_inst_set_qtr_control(devinfo, inst,
> BRW_COMPRESSION_2NDHALF);
> > + else if (brw_inst_qtr_control(devinfo, inst) ==
> BRW_COMPRESSION_2NDHALF)
> > + brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
> > + }
> > +}
> > +
> > +void
> >
Re: [Mesa-dev] [PATCH 01/21] i965/eu: Define alternative interface for setting compression and group controls.
On Tue, May 24, 2016 at 2:05 AM, Michael Schellenberger <
mschellenbergerco...@googlemail.com> wrote:
> Hi curro,
>
> Am 24.05.2016 um 09:18 schrieb Francisco Jerez:
> > This implements some simple helper functions that can be used to
> > specify the group of channel enable signals and compression enable
> > that apply to a brw_inst instruction.
> >
> > It's intended to replace brw_set_default_compression_control
> > eventually because the current interface has a number of shortcomings
> > inherited from the Gen-4-5-centric representation of compression and
> > group controls as a single non-orthogonal enum: On the one hand it
> > doesn't work for specifying arbitrary group controls other than 1Q and
> > 2Q, which are frequently useful in SIMD32 and FP64 programs. On the
> > other hand the current interface forces you to update the compression
> > *and* group controls simultaneously, which has been the source of a
> > number of generator bugs (a bunch of them fixed in this series),
> > because in many cases we would end up resetting the group controls to
> > zero inadvertently even though everything we wanted to do was disable
> > instruction compression -- The latter seems especially unfortunate on
> > Gen6+ hardware which have no explicit compression control, so we would
> > end up bashing the quarter control field of the instruction for no
> > benefit.
> >
> > Instead of a single function that updates both at the same time
> > introduce separate interfaces to update one or the other independently
> > preserving the current value of the other (which typically comes from
> > the back-end IR so it has to be respected).
> > ---
> > src/mesa/drivers/dri/i965/brw_eu.c | 69
> ++
> > src/mesa/drivers/dri/i965/brw_eu.h | 6
> > 2 files changed, 75 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
> b/src/mesa/drivers/dri/i965/brw_eu.c
> > index 48c8439..f1161d2 100644
> > --- a/src/mesa/drivers/dri/i965/brw_eu.c
> > +++ b/src/mesa/drivers/dri/i965/brw_eu.c
> > @@ -218,6 +218,75 @@ brw_set_default_compression_control(struct
> brw_codegen *p,
> > }
> > }
> >
> > +/**
> > + * Enable or disable instruction compression on the given instruction
> leaving
> > + * the currently selected channel enable group untouched.
> > + */
> > +void
> > +brw_inst_set_compression(const struct brw_device_info *devinfo,
> > + brw_inst *inst, bool on)
> > +{
> > + if (devinfo->gen >= 6) {
> > + /* No-op, the EU will figure out for us whether the instruction
> needs to
> > + * be compressed.
> > + */
> > + } else {
> > + /* The channel group and compression controls are non-orthogonal,
> there
> > + * are two possible representations for uncompressed instructions
> and we
> > + * may need to preserve the current one to avoid changing the
> selected
> > + * channel group inadvertently.
> > + */
> > + if (on)
> > + brw_inst_set_qtr_control(devinfo, inst,
> BRW_COMPRESSION_COMPRESSED);
> > + else if (brw_inst_qtr_control(devinfo, inst)
> > + == BRW_COMPRESSION_COMPRESSED)
> > + brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
> > + }
> > +}
> > +
> > +void
> > +brw_set_default_compression(struct brw_codegen *p, bool on)
> > +{
> > + brw_inst_set_compression(p->devinfo, p->current, on);
> > +}
> > +
> > +/**
> > + * Apply the range of channel enable signals given by
> > + * [group, group + exec_size[ to the instruction passed as argument.
> > + */
> > +void
> > +brw_inst_set_group(const struct brw_device_info *devinfo,
> > + brw_inst *inst, unsigned group)
> > +{
> > + if (devinfo->gen >= 7) {
> > + assert(group % 4 == 0 && group < 32);
> > + brw_inst_set_qtr_control(devinfo, inst, group / 8);
> > + brw_inst_set_nib_control(devinfo, inst, group / 4 % 2);
>
Mind adding parentheses around "group / 4" so the reader doesn't have to
think about operator precedence between / and %.
> > +
> > + } else if (devinfo->gen >= 6) {
> Could you make that ==6, so the two conditions do not overlap?
>
That's not a bad idea.
> --Michael
> > + assert(group % 8 == 0 && group < 32);
> > + brw_inst_set_qtr_control(devinfo, inst, group / 8);
> > +
> > + } else {
> > + assert(group % 8 == 0 && group < 16);
> > + /* The channel group and compression controls are non-orthogonal,
> there
> > + * are two possible representations for group zero and we may
> need to
> > + * preserve the current one to avoid changing the selected
> compression
> > + * enable inadvertently.
> > + */
> > + if (group == 8)
> > + brw_inst_set_qtr_control(devinfo, inst,
> BRW_COMPRESSION_2NDHALF);
> > + else if (brw_inst_qtr_control(devinfo, inst) ==
> BRW_COMPRESSION_2NDHALF)
> > + brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
> > + }
> > +}
> > +
> > +void
> >
[Mesa-dev] [PATCH] i965: Add missing types to type_sz().
Coverity warns in multiple places about the potential for division by
zero, caused by this function's default case.
Cc: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_reg.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index b0ef94e..be23678 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -292,15 +292,19 @@ type_sz(unsigned type)
case BRW_REGISTER_TYPE_UD:
case BRW_REGISTER_TYPE_D:
case BRW_REGISTER_TYPE_F:
+ case BRW_REGISTER_TYPE_VF:
return 4;
case BRW_REGISTER_TYPE_UW:
case BRW_REGISTER_TYPE_W:
+ case BRW_REGISTER_TYPE_UV:
+ case BRW_REGISTER_TYPE_V:
+ case BRW_REGISTER_TYPE_HF:
return 2;
case BRW_REGISTER_TYPE_UB:
case BRW_REGISTER_TYPE_B:
return 1;
default:
- return 0;
+ unreachable("not reached");
}
}
--
2.7.3
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Add support for GL_CONTEXT_LOST
On Tue, May 24, 2016 at 2:30 PM, Kristian Høgsberg wrote: > diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c > b/src/mesa/drivers/dri/i965/intel_extensions.c > index feea6ca..b8d7517 100644 > --- a/src/mesa/drivers/dri/i965/intel_extensions.c > +++ b/src/mesa/drivers/dri/i965/intel_extensions.c > @@ -246,6 +246,7 @@ intelInitExtensions(struct gl_context *ctx) > ctx->Extensions.EXT_texture_sRGB_decode = true; > ctx->Extensions.EXT_texture_swizzle = true; > ctx->Extensions.EXT_vertex_array_bgra = true; > + ctx->Extensions.KHR_robustness = true; This is kind of a strangely sorted list, but I think this should go between ATI_* and MESA_* > ctx->Extensions.AMD_seamless_cubemap_per_texture = true; > ctx->Extensions.APPLE_object_purgeable = true; > ctx->Extensions.ATI_separate_stencil = true; ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir/algebraic: support for power-of-two optimizations
From: Rob Clark
Some optimizations, like converting integer multiply/divide into left/
right shifts, have additional constraints on the search expression.
Like requiring that a variable is a constant power of two. Support
these cases by allowing a fxn name to be appended to the search var
expression (ie. "a#32(is_power_of_two)").
Signed-off-by: Rob Clark
[for an earlier version:]
Reviewed-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
---
R-b's were on earlier version, before splitting out positive and
negative PoT condition functions and handling idiv in addition to
udiv.
The idiv rules do seem to work properly for case where 'a' is MIN_INT.
(Tested on both i965 and freedreno).
src/compiler/nir/nir.h| 3 ++
src/compiler/nir/nir_algebraic.py | 8 ++-
src/compiler/nir/nir_opt_algebraic.py | 15 --
src/compiler/nir/nir_search.c | 3 ++
src/compiler/nir/nir_search.h | 10
src/compiler/nir/nir_search_helpers.h | 94 +++
6 files changed, 128 insertions(+), 5 deletions(-)
create mode 100644 src/compiler/nir/nir_search_helpers.h
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index dab0404..9b5d088 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1652,6 +1652,9 @@ typedef struct nir_shader_compiler_options {
/* lower {slt,sge,seq,sne} to {flt,fge,feq,fne} + b2f: */
bool lower_scmp;
+ /** enables rules to lower idiv by power-of-two: */
+ bool lower_idiv;
+
/* Does the native fdot instruction replicate its result for four
* components? If so, then opt_algebraic_late will turn all fdotN
* instructions into fdot_replicatedN instructions.
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebraic.py
index 285f853..19ac6ee 100644
--- a/src/compiler/nir/nir_algebraic.py
+++ b/src/compiler/nir/nir_algebraic.py
@@ -76,6 +76,7 @@ class Value(object):
return Constant(val, name_base)
__template = mako.template.Template("""
+#include "compiler/nir/nir_search_helpers.h"
static const ${val.c_type} ${val.name} = {
{ ${val.type_enum}, ${val.bit_size} },
% if isinstance(val, Constant):
@@ -84,6 +85,7 @@ static const ${val.c_type} ${val.name} = {
${val.index}, /* ${val.var_name} */
${'true' if val.is_constant else 'false'},
${val.type() or 'nir_type_invalid' },
+ ${val.cond if val.cond else 'NULL'},
% elif isinstance(val, Expression):
${'true' if val.inexact else 'false'},
nir_op_${val.opcode},
@@ -113,7 +115,7 @@ static const ${val.c_type} ${val.name} = {
Variable=Variable,
Expression=Expression)
-_constant_re = re.compile(r"(?P[^@]+)(?:@(?P\d+))?")
+_constant_re = re.compile(r"(?P[^@\(]+)(?:@(?P\d+))?")
class Constant(Value):
def __init__(self, val, name):
@@ -150,7 +152,8 @@ class Constant(Value):
return "nir_type_float"
_var_name_re = re.compile(r"(?P#)?(?P\w+)"
-
r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?")
+ r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?"
+ r"(?P\([^\)]+\))?")
class Variable(Value):
def __init__(self, val, name, varset):
@@ -161,6 +164,7 @@ class Variable(Value):
self.var_name = m.group('name')
self.is_constant = m.group('const') is not None
+ self.cond = m.group('cond')
self.required_type = m.group('type')
self.bit_size = int(m.group('bits')) if m.group('bits') else 0
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index f8db2b6..011263a 100644
--- a/src/compiler/nir/nir_opt_algebraic.py
+++ b/src/compiler/nir/nir_opt_algebraic.py
@@ -45,10 +45,11 @@ d = 'd'
# however, be used for backend-requested lowering operations as those need to
# happen regardless of precision.
#
-# Variable names are specified as "[#]name[@type]" where "#" inicates that
-# the given variable will only match constants and the type indicates that
+# Variable names are specified as "[#]name[@type][(cond)]" where "#" inicates
+# that the given variable will only match constants and the type indicates that
# the given variable will only match values from ALU instructions with the
-# given output type.
+# given output type, and (cond) specifies an additional condition function
+# (see nir_search_helpers.h).
#
# For constants, you have to be careful to make sure that it is the right
# type because python is unaware of the source and destination types of the
@@ -62,6 +63,14 @@ d = 'd'
# constructed value should have that bit-size.
optimizations = [
+
+ (('imul', a, '#b@32(is_pos_power_of_two)'), ('ishl', a, ('find_lsb', b))),
+ (('imul', a, '#b@32(is_neg_power_of_two)'), ('ineg', ('ishl', a,
('find_lsb', ('iabs', b),
+ (('udiv', a, '#b@32(is_pos_power_of_two)'), ('ushr', a, ('find_lsb', b))),
+ (('idiv', a, '#b@32(is_pos_power_of_two)'), ('imul', ('isig
[Mesa-dev] [PATCH] mesa: Add support for GL_CONTEXT_LOST
From: Kristian Høgsberg Kristensen
As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all
entry points when we lose a context. We do this by creating a new
dispatch table and setting that when we learn that we've lost the
context.
With the GL_CONTEXT_LOST reporting in place we can turn on
GL_KHR_robustness.
Signed-off-by: Kristian Høgsberg Kristensen
---
docs/GL3.txt | 2 +-
docs/relnotes/11.3.0.html | 1 +
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/brw_reset.c | 20 +++
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 3 +
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
src/mesa/main/context.c | 1 +
src/mesa/main/context.h | 2 +
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/getstring.c | 82 ++-
src/mesa/main/mtypes.h| 7 ++-
11 files changed, 119 insertions(+), 3 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index b5f03af..21ab46a 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -218,7 +218,7 @@ GL 4.5, GLSL 4.50:
GL_ARB_shader_texture_image_samples DONE (i965, nv50,
nvc0, r600, radeonsi)
GL_ARB_texture_barrierDONE (i965, nv50,
nvc0, r600, radeonsi)
GL_KHR_context_flush_control DONE (all - but needs
GLX/EGL extension to be useful)
- GL_KHR_robustness not started (90% done
with the ARB variant)
+ GL_KHR_robustness DONE (i965)
GL_EXT_shader_integer_mix DONE (all drivers that
support GLSL)
These are the extensions cherry-picked to make GLES 3.1
diff --git a/docs/relnotes/11.3.0.html b/docs/relnotes/11.3.0.html
index 5871ec8..d5bb292 100644
--- a/docs/relnotes/11.3.0.html
+++ b/docs/relnotes/11.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new features are only available with
certain drivers.
GL_ARB_shader_storage_buffer_objects on radeonsi, softpipe
GL_ATI_fragment_shader on all Gallium drivers
GL_EXT_base_instance on all drivers that support GL_ARB_base_instance
+GL_KHR_robustness on i965
GL_OES_draw_buffers_indexed and GL_EXT_draw_buffers_indexed on all drivers
that support GL_ARB_draw_buffers_blend
GL_OES_sample_shading on i965, nvc0, r600, radeonsi
GL_OES_sample_variables on i965, nvc0, r600, radeonsi
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 5155475..4b22201 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1704,6 +1704,8 @@ gen7_emit_urb_state(struct brw_context *brw,
/* brw_reset.c */
extern GLenum
brw_get_graphics_reset_status(struct gl_context *ctx);
+void
+brw_check_for_reset(struct brw_context *brw);
/* brw_compute.c */
extern void
diff --git a/src/mesa/drivers/dri/i965/brw_reset.c
b/src/mesa/drivers/dri/i965/brw_reset.c
index e3182b1..df734e5 100644
--- a/src/mesa/drivers/dri/i965/brw_reset.c
+++ b/src/mesa/drivers/dri/i965/brw_reset.c
@@ -20,6 +20,9 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+
+#include "main/context.h"
+
#include "brw_context.h"
/**
@@ -73,3 +76,20 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
return GL_NO_ERROR;
}
+
+void
+brw_check_for_reset(struct brw_context *brw)
+{
+ uint32_t reset_count;
+ uint32_t active;
+ uint32_t pending;
+ int err;
+
+ err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
+ &pending);
+ if (err)
+ return;
+
+ if (active > 0 || pending > 0)
+ _mesa_set_context_lost_dispatch(&brw->ctx);
+}
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index f220311..5a0db9f 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -368,6 +368,9 @@ do_flush_locked(struct brw_context *brw)
if (unlikely(INTEL_DEBUG & DEBUG_BATCH))
do_batch_dump(brw);
+ if (brw->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
+ brw_check_for_reset(brw);
+
if (ret != 0) {
fprintf(stderr, "intel_do_flush_locked failed: %s\n", strerror(-ret));
exit(1);
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index feea6ca..b8d7517 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -246,6 +246,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_texture_sRGB_decode = true;
ctx->Extensions.EXT_texture_swizzle = true;
ctx->Extensions.EXT_vertex_array_bgra = true;
+ ctx->Extensions.KHR_robustness = true;
ctx->Extensions.AMD_seamless_cubemap_pe
Re: [Mesa-dev] [PATCH 2/3] nir/algebraic: support for power-of-two optimizations
On Tue, May 24, 2016 at 3:41 PM, Rob Clark wrote:
> On Mon, May 16, 2016 at 3:16 PM, Jason Ekstrand wrote:
>> On Mon, May 16, 2016 at 9:09 AM, Rob Clark wrote:
>>>
>>> On Mon, May 16, 2016 at 10:45 AM, Jason Ekstrand
>>> wrote:
>>> >
>>> > On May 16, 2016 7:29 AM, "Rob Clark" wrote:
>>> >>
>>> >> On Sat, May 14, 2016 at 4:03 PM, Jason Ekstrand
>>> >> wrote:
>>> >> >
>>> >> >
>>> >> > On Sat, May 14, 2016 at 12:20 PM, Rob Clark
>>> >> > wrote:
>>> >> >>
>>> >> >> On Thu, May 12, 2016 at 10:55 PM, Jason Ekstrand
>>> >> >>
>>> >> >> wrote:
>>> >> >> >
>>> >> >> >
>>> >> >> > On Tue, May 10, 2016 at 11:57 AM, Rob Clark
>>> >> >> > wrote:
>>> >> >> >>
>>> >> >> >> From: Rob Clark
>>> >> >> >>
>>> >> >> >> Some optimizations, like converting integer multiply/divide into
>>> >> >> >> left/
>>> >> >> >> right shifts, have additional constraints on the search
>>> >> >> >> expression.
>>> >> >> >> Like requiring that a variable is a constant power of two.
>>> >> >> >> Support
>>> >> >> >> these cases by allowing a fxn name to be appended to the search
>>> >> >> >> var
>>> >> >> >> expression (ie. "a#32(is_power_of_two)").
>>> >> >> >>
>>> >> >> >> TODO update doc/comment explaining search var syntax
>>> >> >> >> TODO the eagle-eyed viewer might have noticed that this could
>>> >> >> >> also
>>> >> >> >> replace the existing const syntax (ie. "#a"). Not sure if we
>>> >> >> >> should
>>> >> >> >> keep that.. we could make it syntactic sugar (ie '#'
>>> >> >> >> automatically
>>> >> >> >> sets
>>> >> >> >> the cond fxn ptr to 'is_const') or just get rid of it entirely?
>>> >> >> >> Maybe
>>> >> >> >> that is a follow-on clean-up patch?
>>> >> >> >>
>>> >> >> >> Signed-off-by: Rob Clark
>>> >> >> >> ---
>>> >> >> >> src/compiler/nir/nir_algebraic.py | 8 +++--
>>> >> >> >> src/compiler/nir/nir_opt_algebraic.py | 5 +++
>>> >> >> >> src/compiler/nir/nir_search.c | 3 ++
>>> >> >> >> src/compiler/nir/nir_search.h | 10 ++
>>> >> >> >> src/compiler/nir/nir_search_helpers.h | 66
>>> >> >> >> +++
>>> >> >> >> 5 files changed, 90 insertions(+), 2 deletions(-)
>>> >> >> >> create mode 100644 src/compiler/nir/nir_search_helpers.h
>>> >> >> >>
>>> >> >> >> diff --git a/src/compiler/nir/nir_algebraic.py
>>> >> >> >> b/src/compiler/nir/nir_algebraic.py
>>> >> >> >> index 285f853..19ac6ee 100644
>>> >> >> >> --- a/src/compiler/nir/nir_algebraic.py
>>> >> >> >> +++ b/src/compiler/nir/nir_algebraic.py
>>> >> >> >> @@ -76,6 +76,7 @@ class Value(object):
>>> >> >> >> return Constant(val, name_base)
>>> >> >> >>
>>> >> >> >> __template = mako.template.Template("""
>>> >> >> >> +#include "compiler/nir/nir_search_helpers.h"
>>> >> >> >> static const ${val.c_type} ${val.name} = {
>>> >> >> >> { ${val.type_enum}, ${val.bit_size} },
>>> >> >> >> % if isinstance(val, Constant):
>>> >> >> >> @@ -84,6 +85,7 @@ static const ${val.c_type} ${val.name} = {
>>> >> >> >> ${val.index}, /* ${val.var_name} */
>>> >> >> >> ${'true' if val.is_constant else 'false'},
>>> >> >> >> ${val.type() or 'nir_type_invalid' },
>>> >> >> >> + ${val.cond if val.cond else 'NULL'},
>>> >> >> >> % elif isinstance(val, Expression):
>>> >> >> >> ${'true' if val.inexact else 'false'},
>>> >> >> >> nir_op_${val.opcode},
>>> >> >> >> @@ -113,7 +115,7 @@ static const ${val.c_type} ${val.name} = {
>>> >> >> >> Variable=Variable,
>>> >> >> >> Expression=Expression)
>>> >> >> >>
>>> >> >> >> -_constant_re =
>>> >> >> >> re.compile(r"(?P[^@]+)(?:@(?P\d+))?")
>>> >> >> >> +_constant_re =
>>> >> >> >> re.compile(r"(?P[^@\(]+)(?:@(?P\d+))?")
>>> >> >> >
>>> >> >> >
>>> >> >> > Spurious change?
>>> >> >> >
>>> >> >>
>>> >> >> I thought it needed to avoid matching something like
>>> >> >> a(is_power_of_two).. but it seems to work with that hunk reverted so
>>> >> >> I
>>> >> >> guess I can drop it..
>>> >> >>
>>> >> >> >>
>>> >> >> >>
>>> >> >> >> class Constant(Value):
>>> >> >> >> def __init__(self, val, name):
>>> >> >> >> @@ -150,7 +152,8 @@ class Constant(Value):
>>> >> >> >> return "nir_type_float"
>>> >> >> >>
>>> >> >> >> _var_name_re = re.compile(r"(?P#)?(?P\w+)"
>>> >> >> >> -
>>> >> >> >> r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?")
>>> >> >> >> +
>>> >> >> >> r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?"
>>> >> >> >> + r"(?P\([^\)]+\))?")
>>> >> >> >>
>>> >> >> >> class Variable(Value):
>>> >> >> >> def __init__(self, val, name, varset):
>>> >> >> >> @@ -161,6 +164,7 @@ class Variable(Value):
>>> >> >> >>
>>> >> >> >>self.var_name = m.group('name')
>>> >> >> >>self.is_constant = m.group('const') is not None
>>> >> >> >> + self.cond = m.group('cond')
>>> >> >> >>self.required_type = m.group('type')
>>> >> >> >>self.bit_size = int(m.group('bits')) if m.group('bits')
>>> >> >> >> else
>>> >> >> >> 0
>>> >> >> >>
Re: [Mesa-dev] [PATCH 1/6] isl: Remove useless qualifier from return type.
On Tue, May 24, 2016 at 1:23 PM, Matt Turner wrote:
> ---
> src/intel/isl/isl_surface_state.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/isl/isl_surface_state.c
> b/src/intel/isl/isl_surface_state.c
> index dd88531..cc9c94a 100644
> --- a/src/intel/isl/isl_surface_state.c
> +++ b/src/intel/isl/isl_surface_state.c
> @@ -90,7 +90,7 @@ static const uint32_t isl_to_gen_multisample_layout[] = {
> };
> #endif
>
> -static const uint8_t
> +static uint8_t
> get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
> {
> switch (dim) {
> --
> 2.7.3
>
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Series is:
Reviewed-by: Anuj Phogat
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Re: [Mesa-dev] [PATCH 09/14] mesa_glinterop: fix GL interop *_VERSION comments
On Tue, May 24, 2016 at 10:16 PM, Emil Velikov wrote:
> On 24 May 2016 at 17:38, Marek Olšák wrote:
>> On Tue, May 24, 2016 at 4:32 PM, Emil Velikov
>> wrote:
>>> From: Emil Velikov
>>>
>>> Using the macro to set the version is wrong and ill-advised. Please don't
>>> do it.
>>>
>>> Cc: Marek Olšák
>>> Signed-off-by: Emil Velikov
>>> ---
>>> Marek, now things start to unravel as to why you were not too excited on
>>> the idea. Hopefully this comment makes things clearer/more descriptive.
>>> If not please let me know how we can improve it.
>>> ---
>>> include/GL/mesa_glinterop.h | 9 ++---
>>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/include/GL/mesa_glinterop.h b/include/GL/mesa_glinterop.h
>>> index 5c172c6..f637409 100644
>>> --- a/include/GL/mesa_glinterop.h
>>> +++ b/include/GL/mesa_glinterop.h
>>> @@ -93,7 +93,8 @@ enum {
>>> * Device information returned by Mesa.
>>> */
>>> typedef struct _mesa_glinterop_device_info {
>>> - /* The caller should set this to: MESA_GLINTEROP_DEVICE_INFO_VERSION */
>>> + /* The caller should set this to the version of the struct they support
>>> */
>>> + /* NOTE: Do not use the MESA_GLINTEROP_DEVICE_INFO_VERSION macro */
>>> uint32_t struct_version;
>>>
>>> /* PCI location */
>>> @@ -124,7 +125,8 @@ typedef struct _mesa_glinterop_device_info {
>>> * Input parameters to Mesa interop export functions.
>>> */
>>> typedef struct _mesa_glinterop_export_in {
>>> - /* The caller should set this to: MESA_GLINTEROP_EXPORT_IN_VERSION */
>>> + /* The caller should set this to the version of the struct they support
>>> */
>>> + /* NOTE: Do not use the MESA_GLINTEROP_EXPORT_IN_VERSION macro */
>>> uint32_t struct_version;
>>>
>>> /* One of the following:
>>> @@ -183,7 +185,8 @@ typedef struct _mesa_glinterop_export_in {
>>> * Outputs of Mesa interop export functions.
>>> */
>>> typedef struct _mesa_glinterop_export_out {
>>> - /* The caller should set this to: MESA_GLINTEROP_EXPORT_OUT_VERSION */
>>> + /* The caller should set this to the version of the struct they support
>>> */
>>> + /* NOTE: Do not use the MESA_GLINTEROP_EXPORT_OUT_VERSION macro */
>>> uint32_t struct_version;
>>
>> Obviously, the comments don't apply to closed-source projects or any
>> open source projects that just import the header and use the interface
>> correctly and completely. If that's the case, using the VERSION macros
>> makes sense. It had never been my intention for other projects to get
>> this header from /usr/include/GL. Maybe we shouldn't install it.
>>
>> This patch would be OK if the header was used from /usr/include/GL
>> only. Since that's not the expected usage, this patch is NAK.
>>
> I wasn't thinking/implying that the header should be installed...
> maybe it should, maybe it shouldn't. The more important part is that
> things are fragile as-is.
>
> For example:
> User I needs v2 of export_in. Header is updated and implementation is done.
> User A needs v2 of export_out. Header is updated and one will
> - need to implement both v2 export_out _and_ v2 export_in (even if v2
> _in cannot be done for time/other reasons), or
> - have to hack the header locally (a not good idea in itself), or
> - don't implement v2 _in, in which case we'll crash.
>
> With ^^ in mind, I think it makes sense to advice against using the
> macro, correct ?
OK, that sounds good. This patch is:
Reviewed-by: Marek Olšák
Marek
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Re: [Mesa-dev] [PATCH 0/2] scons 2.5.0 support
On 05/24/2016 02:05 PM, Giuseppe Bilotta wrote: On Tue, May 24, 2016 at 6:13 PM, Brian Paul wrote: For both, Reviewed-by: Brian Paul Do you need me to push these for you? Well, AFAIK I don't have write access to the mesa git tree so yes please ;-) (Possibly with the extra commit lines with the full Bugzilla link that Emil posted for patch#2). Sure. Unfortunately, the series does not apply cleanly on ToT master: % git am p[12].txt Applying: scons: whitespace cleanup Using index info to reconstruct a base tree... error: patch failed: src/gallium/state_trackers/wgl/SConscript:12 error: src/gallium/state_trackers/wgl/SConscript: patch does not apply Did you hand edit your patch? It does not apply to blobs recorded in its index. Cannot fall back to three-way merge. Patch failed at 0001 scons: whitespace cleanup The copy of the patch that failed is found in: /home/brianp/mesa/.git/rebase-apply/patch When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Can you update the patches and send them to me? Thanks. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/6] i965: Mark fallthrough in switch statement.
--- src/mesa/drivers/dri/i965/brw_eu_emit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index d31943d..20fdfc1 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -2695,6 +2695,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset) */ if (!while_jumps_before_offset(devinfo, insn, offset, start_offset)) continue; + /* fallthrough */ case BRW_OPCODE_ELSE: case BRW_OPCODE_HALT: if (depth == 0) -- 2.7.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/6] isl: Mark default cases unreachable.
---
src/intel/isl/isl_surface_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index cc9c94a..e96d3b0 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -166,7 +166,7 @@ get_qpitch(const struct isl_surf *surf)
{
switch (surf->dim) {
default:
- assert(!"Bad isl_surf_dim");
+ unreachable("Bad isl_surf_dim");
case ISL_SURF_DIM_1D:
if (GEN_GEN >= 9) {
/* QPitch is usually expressed as rows of surface elements (where
@@ -363,7 +363,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev,
void *state,
info->view->base_level) - 1;
break;
default:
- unreachable(!"bad SurfaceType");
+ unreachable("bad SurfaceType");
}
if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
--
2.7.3
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[Mesa-dev] [PATCH 5/6] i965: Assert that a depth_mt exists when using HiZ.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 1 +
src/mesa/drivers/dri/i965/gen6_depth_state.c | 1 +
src/mesa/drivers/dri/i965/gen7_misc_state.c | 1 +
src/mesa/drivers/dri/i965/gen8_depth_state.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 5510d2c..690c2f6 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -646,6 +646,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit hiz buffer. */
if (hiz) {
+ assert(depth_mt);
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index febd478..1a29860 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -160,6 +160,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
/* Emit hiz buffer. */
if (hiz) {
+ assert(depth_mt);
struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_buf->mt;
uint32_t offset = 0;
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 321c425..ffdf6f2 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -145,6 +145,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ assert(depth_mt);
struct intel_miptree_aux_buffer *hiz_buf = depth_mt->hiz_buf;
BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 0eb993f..a780da6 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -90,6 +90,7 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
+ assert(depth_mt);
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2));
OUT_BATCH((depth_mt->hiz_buf->pitch - 1) | mocs_wb << 25);
--
2.7.3
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[Mesa-dev] [PATCH 4/6] nir: Strengthen assertion that 'out' is nonnull.
--- src/compiler/nir/nir_lower_clamp_color_outputs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_clamp_color_outputs.c b/src/compiler/nir/nir_lower_clamp_color_outputs.c index 68bfbed..ab211a4 100644 --- a/src/compiler/nir/nir_lower_clamp_color_outputs.c +++ b/src/compiler/nir/nir_lower_clamp_color_outputs.c @@ -79,7 +79,7 @@ lower_intrinsic(lower_state *state, nir_intrinsic_instr *intr) break; } } - assert(out); + assume(out); break; default: return; -- 2.7.3 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/6] isl: Remove useless qualifier from return type.
---
src/intel/isl/isl_surface_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index dd88531..cc9c94a 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -90,7 +90,7 @@ static const uint32_t isl_to_gen_multisample_layout[] = {
};
#endif
-static const uint8_t
+static uint8_t
get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
{
switch (dim) {
--
2.7.3
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[Mesa-dev] [PATCH 3/6] spriv: Mark default cases unreachable().
---
src/compiler/spirv/vtn_alu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 8b9a63c..5730ca4 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -356,6 +356,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
case 2: op = nir_op_bany_inequal2; break;
case 3: op = nir_op_bany_inequal3; break;
case 4: op = nir_op_bany_inequal4; break;
+ default: unreachable("not reached");
}
val->ssa->def = nir_build_alu(&b->nb, op, src[0],
nir_imm_int(&b->nb, NIR_FALSE),
@@ -372,6 +373,7 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode,
case 2: op = nir_op_ball_iequal2; break;
case 3: op = nir_op_ball_iequal3; break;
case 4: op = nir_op_ball_iequal4; break;
+ default: unreachable("not reached");
}
val->ssa->def = nir_build_alu(&b->nb, op, src[0],
nir_imm_int(&b->nb, NIR_TRUE),
--
2.7.3
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Re: [Mesa-dev] [PATCH 09/14] mesa_glinterop: fix GL interop *_VERSION comments
On 24 May 2016 at 17:38, Marek Olšák wrote:
> On Tue, May 24, 2016 at 4:32 PM, Emil Velikov
> wrote:
>> From: Emil Velikov
>>
>> Using the macro to set the version is wrong and ill-advised. Please don't
>> do it.
>>
>> Cc: Marek Olšák
>> Signed-off-by: Emil Velikov
>> ---
>> Marek, now things start to unravel as to why you were not too excited on
>> the idea. Hopefully this comment makes things clearer/more descriptive.
>> If not please let me know how we can improve it.
>> ---
>> include/GL/mesa_glinterop.h | 9 ++---
>> 1 file changed, 6 insertions(+), 3 deletions(-)
>>
>> diff --git a/include/GL/mesa_glinterop.h b/include/GL/mesa_glinterop.h
>> index 5c172c6..f637409 100644
>> --- a/include/GL/mesa_glinterop.h
>> +++ b/include/GL/mesa_glinterop.h
>> @@ -93,7 +93,8 @@ enum {
>> * Device information returned by Mesa.
>> */
>> typedef struct _mesa_glinterop_device_info {
>> - /* The caller should set this to: MESA_GLINTEROP_DEVICE_INFO_VERSION */
>> + /* The caller should set this to the version of the struct they support
>> */
>> + /* NOTE: Do not use the MESA_GLINTEROP_DEVICE_INFO_VERSION macro */
>> uint32_t struct_version;
>>
>> /* PCI location */
>> @@ -124,7 +125,8 @@ typedef struct _mesa_glinterop_device_info {
>> * Input parameters to Mesa interop export functions.
>> */
>> typedef struct _mesa_glinterop_export_in {
>> - /* The caller should set this to: MESA_GLINTEROP_EXPORT_IN_VERSION */
>> + /* The caller should set this to the version of the struct they support
>> */
>> + /* NOTE: Do not use the MESA_GLINTEROP_EXPORT_IN_VERSION macro */
>> uint32_t struct_version;
>>
>> /* One of the following:
>> @@ -183,7 +185,8 @@ typedef struct _mesa_glinterop_export_in {
>> * Outputs of Mesa interop export functions.
>> */
>> typedef struct _mesa_glinterop_export_out {
>> - /* The caller should set this to: MESA_GLINTEROP_EXPORT_OUT_VERSION */
>> + /* The caller should set this to the version of the struct they support
>> */
>> + /* NOTE: Do not use the MESA_GLINTEROP_EXPORT_OUT_VERSION macro */
>> uint32_t struct_version;
>
> Obviously, the comments don't apply to closed-source projects or any
> open source projects that just import the header and use the interface
> correctly and completely. If that's the case, using the VERSION macros
> makes sense. It had never been my intention for other projects to get
> this header from /usr/include/GL. Maybe we shouldn't install it.
>
> This patch would be OK if the header was used from /usr/include/GL
> only. Since that's not the expected usage, this patch is NAK.
>
I wasn't thinking/implying that the header should be installed...
maybe it should, maybe it shouldn't. The more important part is that
things are fragile as-is.
For example:
User I needs v2 of export_in. Header is updated and implementation is done.
User A needs v2 of export_out. Header is updated and one will
- need to implement both v2 export_out _and_ v2 export_in (even if v2
_in cannot be done for time/other reasons), or
- have to hack the header locally (a not good idea in itself), or
- don't implement v2 _in, in which case we'll crash.
With ^^ in mind, I think it makes sense to advice against using the
macro, correct ?
-Emil
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Re: [Mesa-dev] [PATCH 0/2] scons 2.5.0 support
On Tue, May 24, 2016 at 6:13 PM, Brian Paul wrote: > For both, > Reviewed-by: Brian Paul > > Do you need me to push these for you? Well, AFAIK I don't have write access to the mesa git tree so yes please ;-) (Possibly with the extra commit lines with the full Bugzilla link that Emil posted for patch#2). -- Giuseppe "Oblomov" Bilotta ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] glsl/distance: make sure we use clip dist varying slot for lowered var.
Reviewed-by: Ilia Mirkin
On Tue, May 24, 2016 at 4:03 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> When lowering, we always want to use the clip dist varying.
>
> Signed-off-by: Dave Airlie
> ---
> src/compiler/glsl/lower_distance.cpp | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/compiler/glsl/lower_distance.cpp
> b/src/compiler/glsl/lower_distance.cpp
> index 49a71c2..c2158f2 100644
> --- a/src/compiler/glsl/lower_distance.cpp
> +++ b/src/compiler/glsl/lower_distance.cpp
> @@ -168,6 +168,7 @@ lower_distance_visitor::visit(ir_variable *ir)
>*new_var = ir->clone(ralloc_parent(ir), NULL);
>(*new_var)->name = ralloc_strdup(*new_var, GLSL_CLIP_VAR_NAME);
>(*new_var)->data.max_array_access = new_size - 1;
> + (*new_var)->data.location = VARYING_SLOT_CLIP_DIST0;
>
>if (!ir->type->fields.array->is_array()) {
> /* gl_ClipDistance (used for vertex, tessellation evaluation and
> --
> 2.5.5
>
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[Mesa-dev] [PATCH] glsl/distance: make sure we use clip dist varying slot for lowered var.
From: Dave Airlie
When lowering, we always want to use the clip dist varying.
Signed-off-by: Dave Airlie
---
src/compiler/glsl/lower_distance.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/glsl/lower_distance.cpp
b/src/compiler/glsl/lower_distance.cpp
index 49a71c2..c2158f2 100644
--- a/src/compiler/glsl/lower_distance.cpp
+++ b/src/compiler/glsl/lower_distance.cpp
@@ -168,6 +168,7 @@ lower_distance_visitor::visit(ir_variable *ir)
*new_var = ir->clone(ralloc_parent(ir), NULL);
(*new_var)->name = ralloc_strdup(*new_var, GLSL_CLIP_VAR_NAME);
(*new_var)->data.max_array_access = new_size - 1;
+ (*new_var)->data.location = VARYING_SLOT_CLIP_DIST0;
if (!ir->type->fields.array->is_array()) {
/* gl_ClipDistance (used for vertex, tessellation evaluation and
--
2.5.5
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[Mesa-dev] [PATCH] swr: [rasterizer] Correctly select optimized primitive assembly.
Indexed primitives were always using cut-aware primitive assembly,
whether primitive_restart was enabled or not. Correctly pass down
primitive_restart and select optimized PA when possible.
---
src/gallium/drivers/swr/rasterizer/core/api.cpp|2 ++
.../drivers/swr/rasterizer/core/frontend.cpp |6 --
src/gallium/drivers/swr/rasterizer/core/frontend.h |1 +
src/gallium/drivers/swr/rasterizer/core/pa.h |4 ++--
src/gallium/drivers/swr/rasterizer/core/state.h|3 ++-
src/gallium/drivers/swr/swr_draw.cpp |6 ++
src/gallium/drivers/swr/swr_state.cpp |4
7 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 8e0c1e1..2e6f8b3 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -1069,6 +1069,7 @@ void DrawInstanced(
pDC->FeWork.type = DRAW;
pDC->FeWork.pfnWork = GetProcessDrawFunc(
false, // IsIndexed
+false, // bEnableCutIndex
pState->tsState.tsEnable,
pState->gsState.gsEnable,
pState->soState.soEnable,
@@ -1202,6 +1203,7 @@ void DrawIndexedInstance(
pDC->FeWork.type = DRAW;
pDC->FeWork.pfnWork = GetProcessDrawFunc(
true, // IsIndexed
+pState->frontendState.bEnableCutIndex,
pState->tsState.tsEnable,
pState->gsState.gsEnable,
pState->soState.soEnable,
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index d6643c6..ef90a24 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -1159,6 +1159,7 @@ static void TessellationStages(
/// @param pUserData - Pointer to DRAW_WORK
template <
typename IsIndexedT,
+typename IsCutIndexEnabledT,
typename HasTessellationT,
typename HasGeometryShaderT,
typename HasStreamOutT,
@@ -1283,7 +1284,7 @@ void ProcessDraw(
}
// choose primitive assembler
-PA_FACTORY paFactory(pDC, state.topology, work.numVerts);
+PA_FACTORY paFactory(pDC, state.topology,
work.numVerts);
PA_STATE& pa = paFactory.GetPA();
/// @todo: temporarily move instance loop in the FE to ensure SO ordering
@@ -1434,12 +1435,13 @@ struct FEDrawChooser
// Selector for correct templated Draw front-end function
PFN_FE_WORK_FUNC GetProcessDrawFunc(
bool IsIndexed,
+bool IsCutIndexEnabled,
bool HasTessellation,
bool HasGeometryShader,
bool HasStreamOut,
bool HasRasterization)
{
-return TemplateArgUnroller::GetFunc(IsIndexed,
HasTessellation, HasGeometryShader, HasStreamOut, HasRasterization);
+return TemplateArgUnroller::GetFunc(IsIndexed,
IsCutIndexEnabled, HasTessellation, HasGeometryShader, HasStreamOut,
HasRasterization);
}
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.h
b/src/gallium/drivers/swr/rasterizer/core/frontend.h
index e1b0400..dfd3987 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.h
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.h
@@ -322,6 +322,7 @@ uint32_t NumVertsPerPrim(PRIMITIVE_TOPOLOGY topology, bool
includeAdjVerts);
// ProcessDraw front-end function. All combinations of parameter values are
available
PFN_FE_WORK_FUNC GetProcessDrawFunc(
bool IsIndexed,
+bool IsCutIndexEnabled,
bool HasTessellation,
bool HasGeometryShader,
bool HasStreamOut,
diff --git a/src/gallium/drivers/swr/rasterizer/core/pa.h
b/src/gallium/drivers/swr/rasterizer/core/pa.h
index c98ea14..6aa73c1 100644
--- a/src/gallium/drivers/swr/rasterizer/core/pa.h
+++ b/src/gallium/drivers/swr/rasterizer/core/pa.h
@@ -1149,14 +1149,14 @@ private:
// Primitive Assembler factory class, responsible for creating and
initializing the correct assembler
// based on state.
-template
+template
struct PA_FACTORY
{
PA_FACTORY(DRAW_CONTEXT* pDC, PRIMITIVE_TOPOLOGY in_topo, uint32_t
numVerts) : topo(in_topo)
{
#if KNOB_ENABLE_CUT_AWARE_PA == TRUE
const API_STATE& state = GetApiState(pDC);
-if ((IsIndexedT::value && (
+if ((IsIndexedT::value && IsCutIndexEnabledT::value && (
topo == TOP_TRIANGLE_STRIP || topo == TOP_POINT_LIST ||
topo == TOP_LINE_LIST || topo == TOP_LINE_STRIP ||
topo == TOP_TRIANGLE_LIST || topo == TOP_LINE_LIST_ADJ ||
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h
b/src/gallium/drivers/swr/rasterizer/core/state.h
index f4813e4..5156c6b 100644
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -799,6 +799,7 @@ struct SWR_FRONTEND_STATE
// skip clip test, perspective divide, and viewport transform
// intended for verts in screen s
[Mesa-dev] [PATCH] glapi/glx: Add overflow checks to the client-side indirect code
Coverity complains that the computed sizes can lead to negative lengths
passed to memcpy. If that happens we've been handed invalid arguments
anyway, so just bomb out.
The funky "0%s" is because the size string for the variable-length part
of the request is of the form "+ safe_pad() ...", and a unary + would
coerce the result to always be positive, defeating the overflow check.
Signed-off-by: Adam Jackson
---
src/mapi/glapi/gen/glX_proto_send.py | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mapi/glapi/gen/glX_proto_send.py
b/src/mapi/glapi/gen/glX_proto_send.py
index 10abcff..26e7ab6 100644
--- a/src/mapi/glapi/gen/glX_proto_send.py
+++ b/src/mapi/glapi/gen/glX_proto_send.py
@@ -635,6 +635,15 @@ generic_%u_byte( GLint rop, const void * ptr )
if name != None and name not in f.glx_vendorpriv_names:
print '#endif'
+if f.command_variable_length() != "":
+print "if (0%s < 0) {" % f.command_variable_length()
+print "__glXSetError(gc, GL_INVALID_VALUE);"
+if f.return_type != 'void':
+print "return 0;"
+else:
+print "return;"
+print "}"
+
condition_list = []
for p in f.parameterIterateCounters():
condition_list.append( "%s >= 0" % (p.name) )
--
2.7.4
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Re: [Mesa-dev] [PATCH 2/3] nir/algebraic: support for power-of-two optimizations
On Mon, May 16, 2016 at 3:16 PM, Jason Ekstrand wrote:
> On Mon, May 16, 2016 at 9:09 AM, Rob Clark wrote:
>>
>> On Mon, May 16, 2016 at 10:45 AM, Jason Ekstrand
>> wrote:
>> >
>> > On May 16, 2016 7:29 AM, "Rob Clark" wrote:
>> >>
>> >> On Sat, May 14, 2016 at 4:03 PM, Jason Ekstrand
>> >> wrote:
>> >> >
>> >> >
>> >> > On Sat, May 14, 2016 at 12:20 PM, Rob Clark
>> >> > wrote:
>> >> >>
>> >> >> On Thu, May 12, 2016 at 10:55 PM, Jason Ekstrand
>> >> >>
>> >> >> wrote:
>> >> >> >
>> >> >> >
>> >> >> > On Tue, May 10, 2016 at 11:57 AM, Rob Clark
>> >> >> > wrote:
>> >> >> >>
>> >> >> >> From: Rob Clark
>> >> >> >>
>> >> >> >> Some optimizations, like converting integer multiply/divide into
>> >> >> >> left/
>> >> >> >> right shifts, have additional constraints on the search
>> >> >> >> expression.
>> >> >> >> Like requiring that a variable is a constant power of two.
>> >> >> >> Support
>> >> >> >> these cases by allowing a fxn name to be appended to the search
>> >> >> >> var
>> >> >> >> expression (ie. "a#32(is_power_of_two)").
>> >> >> >>
>> >> >> >> TODO update doc/comment explaining search var syntax
>> >> >> >> TODO the eagle-eyed viewer might have noticed that this could
>> >> >> >> also
>> >> >> >> replace the existing const syntax (ie. "#a"). Not sure if we
>> >> >> >> should
>> >> >> >> keep that.. we could make it syntactic sugar (ie '#'
>> >> >> >> automatically
>> >> >> >> sets
>> >> >> >> the cond fxn ptr to 'is_const') or just get rid of it entirely?
>> >> >> >> Maybe
>> >> >> >> that is a follow-on clean-up patch?
>> >> >> >>
>> >> >> >> Signed-off-by: Rob Clark
>> >> >> >> ---
>> >> >> >> src/compiler/nir/nir_algebraic.py | 8 +++--
>> >> >> >> src/compiler/nir/nir_opt_algebraic.py | 5 +++
>> >> >> >> src/compiler/nir/nir_search.c | 3 ++
>> >> >> >> src/compiler/nir/nir_search.h | 10 ++
>> >> >> >> src/compiler/nir/nir_search_helpers.h | 66
>> >> >> >> +++
>> >> >> >> 5 files changed, 90 insertions(+), 2 deletions(-)
>> >> >> >> create mode 100644 src/compiler/nir/nir_search_helpers.h
>> >> >> >>
>> >> >> >> diff --git a/src/compiler/nir/nir_algebraic.py
>> >> >> >> b/src/compiler/nir/nir_algebraic.py
>> >> >> >> index 285f853..19ac6ee 100644
>> >> >> >> --- a/src/compiler/nir/nir_algebraic.py
>> >> >> >> +++ b/src/compiler/nir/nir_algebraic.py
>> >> >> >> @@ -76,6 +76,7 @@ class Value(object):
>> >> >> >> return Constant(val, name_base)
>> >> >> >>
>> >> >> >> __template = mako.template.Template("""
>> >> >> >> +#include "compiler/nir/nir_search_helpers.h"
>> >> >> >> static const ${val.c_type} ${val.name} = {
>> >> >> >> { ${val.type_enum}, ${val.bit_size} },
>> >> >> >> % if isinstance(val, Constant):
>> >> >> >> @@ -84,6 +85,7 @@ static const ${val.c_type} ${val.name} = {
>> >> >> >> ${val.index}, /* ${val.var_name} */
>> >> >> >> ${'true' if val.is_constant else 'false'},
>> >> >> >> ${val.type() or 'nir_type_invalid' },
>> >> >> >> + ${val.cond if val.cond else 'NULL'},
>> >> >> >> % elif isinstance(val, Expression):
>> >> >> >> ${'true' if val.inexact else 'false'},
>> >> >> >> nir_op_${val.opcode},
>> >> >> >> @@ -113,7 +115,7 @@ static const ${val.c_type} ${val.name} = {
>> >> >> >> Variable=Variable,
>> >> >> >> Expression=Expression)
>> >> >> >>
>> >> >> >> -_constant_re =
>> >> >> >> re.compile(r"(?P[^@]+)(?:@(?P\d+))?")
>> >> >> >> +_constant_re =
>> >> >> >> re.compile(r"(?P[^@\(]+)(?:@(?P\d+))?")
>> >> >> >
>> >> >> >
>> >> >> > Spurious change?
>> >> >> >
>> >> >>
>> >> >> I thought it needed to avoid matching something like
>> >> >> a(is_power_of_two).. but it seems to work with that hunk reverted so
>> >> >> I
>> >> >> guess I can drop it..
>> >> >>
>> >> >> >>
>> >> >> >>
>> >> >> >> class Constant(Value):
>> >> >> >> def __init__(self, val, name):
>> >> >> >> @@ -150,7 +152,8 @@ class Constant(Value):
>> >> >> >> return "nir_type_float"
>> >> >> >>
>> >> >> >> _var_name_re = re.compile(r"(?P#)?(?P\w+)"
>> >> >> >> -
>> >> >> >> r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?")
>> >> >> >> +
>> >> >> >> r"(?:@(?Pint|uint|bool|float)?(?P\d+)?)?"
>> >> >> >> + r"(?P\([^\)]+\))?")
>> >> >> >>
>> >> >> >> class Variable(Value):
>> >> >> >> def __init__(self, val, name, varset):
>> >> >> >> @@ -161,6 +164,7 @@ class Variable(Value):
>> >> >> >>
>> >> >> >>self.var_name = m.group('name')
>> >> >> >>self.is_constant = m.group('const') is not None
>> >> >> >> + self.cond = m.group('cond')
>> >> >> >>self.required_type = m.group('type')
>> >> >> >>self.bit_size = int(m.group('bits')) if m.group('bits')
>> >> >> >> else
>> >> >> >> 0
>> >> >> >>
>> >> >> >> diff --git a/src/compiler/nir/nir_opt_algebraic.py
>> >> >> >> b/src/compiler/nir/nir_opt_algebraic.py
>> >> >> >> index 0a95725..952a91a 100644
>> >> >> >> --- a/
Re: [Mesa-dev] [PATCH 7/7] i965: Enable OES_copy_image (and EXT) on Gen8+ and Baytrail.
On Fri, May 20, 2016 at 6:35 PM, Kenneth Graunke wrote:
> For now, only enable it on platforms that actually support ETC2.
>
> At this point, Broadwell is only failing 5 (out of 8358) dEQP tests:
> dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.
>srgb8_alpha8_r11f_g11f_b10f.renderbuffer_to_texture3d
>srgb8_alpha8_rgb10_a2ui.renderbuffer_to_cubemap
>srgb8_alpha8_rgb10_a2ui.renderbuffer_to_renderbuffer
>srgb8_alpha8_rgb10_a2.renderbuffer_to_texture2d
>srgb8_alpha8_rgb9_e5.renderbuffer_to_texture3d
>
> These fail with all methods (meta, blorp, blitter, memcpy).
>
> All are blacklisted from the Android mustpass list, which makes me
> wonder whether there's an issue with the tests. The formats in
> question work with other targets, and the targets in question work
> with other formats...
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 878bd84..624bc26 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -374,6 +374,14 @@ intelInitExtensions(struct gl_context *ctx)
>ctx->Extensions.ARB_query_buffer_object = true;
> }
>
> + if (brw->gen >= 8 || brw->is_baytrail) {
> + /* For now, we only enable OES_copy_image on platforms that support
> + * ETC2 natively in hardware. We would need more hacks to support it
> + * elsewhere.
> + */
> + ctx->Extensions.OES_copy_image = true;
> + }
> +
> if (brw->gen >= 8) {
>ctx->Extensions.ARB_shader_precision = true;
>ctx->Extensions.ARB_stencil_texturing = true;
> --
> 2.8.2
>
> ___
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Patches 2-7 are:
Reviewed-by: Anuj Phogat
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Re: [Mesa-dev] [PATCH] i965/gen7: Fix gl_HelperInvocation
Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/10] mesa: Additional SSO validation using program_interface_query data
On 05/20/2016 06:03 PM, Timothy Arceri wrote:
> On Fri, 2016-05-20 at 00:26 -0700, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> Fixes the following dEQP tests on SKL:
>>
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_qualifi
>> er_vertex_smooth_fragment_flat
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_implici
>> t_explicit_location_1
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_array_e
>> lement_type
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_qualifi
>> er_vertex_flat_fragment_none
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_struct_
>> member_order
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_struct_
>> member_type
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_qualifi
>> er_vertex_centroid_fragment_flat
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_array_l
>> ength
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_type
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_struct_
>> member_precision
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_explici
>> t_location_type
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_qualifi
>> er_vertex_flat_fragment_centroid
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_explici
>> t_location
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_qualifi
>> er_vertex_flat_fragment_smooth
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.mismatch_struct_
>> member_name
>>
>> It regresses one test:
>>
>> dEQP-
>> GLES31.functional.separate_shader.validation.varying.match_different_
>> struct_names
>>
>> Hoever, this test is based on language in the OpenGL ES 3.1 spec that
>> I
>> believe is incorrect. I have already submitted a spec bug:
>>
>> https://www.khronos.org/bugzilla/show_bug.cgi?id=1500
>>
>> Signed-off-by: Ian Romanick
>> ---
>>
>> I'm experimenting with different formatting of spec quotations. This
>> is
>> something new-ish based on the list discussion with Ken and Matt
>> earlier
>> this week.
>>
>> src/mesa/main/shader_query.cpp | 172
>> +
>> 1 file changed, 172 insertions(+)
>>
>> diff --git a/src/mesa/main/shader_query.cpp
>> b/src/mesa/main/shader_query.cpp
>> index a120cb4..5fa611f 100644
>> --- a/src/mesa/main/shader_query.cpp
>> +++ b/src/mesa/main/shader_query.cpp
>> @@ -1470,6 +1470,175 @@ validate_io(const struct gl_shader *producer,
>> return inputs == outputs;
>> }
>>
>> +static bool
>> +validate_io(struct gl_shader_program *producer,
>> +struct gl_shader_program *consumer)
>> +{
>> + if (producer == consumer)
>> + return true;
>> +
>> + bool valid = true;
>> +
>> + gl_shader_variable const **outputs =
>> + (gl_shader_variable const **) calloc(producer-
>>> NumProgramResourceList,
>> + sizeof(gl_shader_variable
>> *));
>> + if (outputs == NULL)
>> + return false;
>> +
>> + /* Section 7.4.1 (Shader Interface Matching) of the OpenGL ES 3.1
>> spec
>> +* says:
>> +*
>> +*At an interface between program objects, the set of inputs
>> and
>> +*outputs are considered to match exactly if and only if:
>> +*
>> +*- Every declared input variable has a matching output, as
>> described
>> +* above.
>> +*- There are no user-defined output variables declared
>> without a
>> +* matching input variable declaration.
>> +*
>> +* Every input has an output, and every output has an
>> input. Scan the list
>> +* of producer resources once, and generate the list of
>> outputs. As inputs
>> +* and outputs are matched, remove the matched outputs from the
>> set. At
>> +* the end, the set must be empty. If the set is not empty, then
>> there is
>> +* some output that did not have an input.
>> +*/
>> + unsigned num_outputs = 0;
>> + for (unsigned i = 0; i < producer->NumProgramResourceList; i++) {
>> + struct gl_program_resource *res = &producer-
>>> ProgramResourceList[i];
>> +
>> + if (res->Type != GL_PROGRAM_OUTPUT)
>> + continue;
>> +
>> + gl_shader_variable const *const var = RESOURCE_VAR(res);
>> +
>> + if (is_gl_identifier(var->name))
>> + continue;
>> +
>> + outputs[num_outputs++] = var;
>> + }
>> +
>> + unsigned match_index = 0;
>> + for (unsigned i = 0; i < consumer->NumProgramResourceList; i++) {
>> + struct gl_program_resource *res = &consumer-
>>> ProgramResourceList[i];
>> +
>> + if (res->Type != GL_PROGRAM_INPUT)
>> + continue;
>> +
>> + gl_shader_variable const *const consumer_var =
>> RESOURCE_VAR(res);
>> + gl_shader_variable const *producer_var = NULL;
>> +
>> + /*
Re: [Mesa-dev] [PATCH 2/2] Add LLVM version to Mesa version strings
On 05/23/2016 07:45 AM, Marek Olšák wrote:
> I think it would be better to put stuff like this only into the
> renderer string of drivers which use LLVM. The majority of drivers
> don't care about the LLVM version.
Yes. In fact, I *really* don't want the LLVM version to show up in the
glxinfo from the i965 or i915 (classic) drivers. Drivers can already
tack extra stuff on to the renderer string (like the AGP speed!), so
maybe it's best to use that mechanism.
> Marek
>
> On Mon, May 23, 2016 at 9:21 AM, Giuseppe Bilotta
> wrote:
>> Code generation (kernel compilation) may sometimes hit LLVM-specific
>> bugs. Adding the used LLVM version to the version string may make bug
>> triaging easier. (This was inspired by a similar patch recently
>> proposed for pocl.)
>>
>> Signed-off-by: Giuseppe Bilotta
>> ---
>> configure.ac | 3 ++-
>> src/gallium/state_trackers/clover/Makefile.am | 1 +
>> src/mesa/main/version_string.h| 2 +-
>> 3 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/configure.ac b/configure.ac
>> index 6eee2bc..400dd9e 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -2122,7 +2122,7 @@ if test "x$enable_gallium_llvm" = xyes; then
>> LLVM_COMPONENTS="${LLVM_COMPONENTS} all-targets ipo linker
>> instrumentation"
>> LLVM_COMPONENTS="${LLVM_COMPONENTS} irreader option objcarcopts
>> profiledata"
>> fi
>> -DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
>> -DMESA_LLVM_VERSION_PATCH=$LLVM_VERSION_PATCH"
>> +DEFINES="${DEFINES} -DHAVE_LLVM=0x0$LLVM_VERSION_INT
>> -DMESA_LLVM_VERSION_PATCH=$LLVM_VERSION_PATCH
>> '-DMESA_LLVM_VERSION_STRING=\"$LLVM_VERSION_MAJOR.$LLVM_VERSION_MINOR.$LLVM_VERSION_PATCH\"'"
>> MESA_LLVM=1
>>
>> dnl Check for Clang internal headers
>> @@ -2137,6 +2137,7 @@ if test "x$enable_gallium_llvm" = xyes; then
>> else
>> MESA_LLVM=0
>> LLVM_VERSION_INT=0
>> +DEFINES="${DEFINES} '-DMESA_LLVM_VERSION_STRING=\"\"'"
>> fi
>> else
>> MESA_LLVM=0
>> diff --git a/src/gallium/state_trackers/clover/Makefile.am
>> b/src/gallium/state_trackers/clover/Makefile.am
>> index 4c9d7d9..f6f3d7f 100644
>> --- a/src/gallium/state_trackers/clover/Makefile.am
>> +++ b/src/gallium/state_trackers/clover/Makefile.am
>> @@ -50,6 +50,7 @@ libclllvm_la_SOURCES = $(LLVM_SOURCES)
>>
>> libclover_la_CXXFLAGS = \
>> -std=c++11 \
>> + $(DEFINES) \
>> $(VISIBILITY_CXXFLAGS)
>>
>> libclover_la_LIBADD = \
>> diff --git a/src/mesa/main/version_string.h b/src/mesa/main/version_string.h
>> index 970cc8b..b175293 100644
>> --- a/src/mesa/main/version_string.h
>> +++ b/src/mesa/main/version_string.h
>> @@ -30,5 +30,5 @@
>> #define MESA_GIT_SHA1_SUFFIX ""
>> #endif
>>
>> -#define MESA_VERSION_SUFFIX " Mesa " PACKAGE_VERSION MESA_GIT_SHA1_SUFFIX
>> +#define MESA_VERSION_SUFFIX " Mesa " PACKAGE_VERSION MESA_GIT_SHA1_SUFFIX
>> MESA_LLVM_VERSION_STRING
>>
>> --
>> 2.8.1.372.g9612035
>>
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Re: [Mesa-dev] [PATCH 04/10] mesa: Check isES before calling validate_io
On 05/20/2016 05:46 PM, Timothy Arceri wrote:
> On Fri, 2016-05-20 at 00:25 -0700, Ian Romanick wrote:
>> From: Ian Romanick
>>
>> There's going to be a second validate_io function, and checking the
>> same
>> thing twice is silly.
>
> I think we should just do this check
> in _mesa_validate_program_pipeline() before we
> call _mesa_validate_pipeline_io() otherwise we end up looping over the
> shaders at draw time for desktop when there is no need to.
>
> The comment above that call quotes
>
> "From OpenGL 4.5 Core spec:
> * "Separable program objects may have validation failures that
> cannot be
> * detected without the complete program pipeline. Mismatched
> interfaces,
> * improper usage of program objects together, and the same
> * state-dependent failures can result in validation errors for
> such
> * program objects."
>
> However I think this is a spec bug I filed https://cvs.khronos.org/bugz
> illa/show_bug.cgi?id=15331 for it.
I think the spec is correct. The key phrase is "can result." This
leaves the possibility for hardware that would crash with certain types
of mismatches to reject them with a GL error at draw time. I don't
think any desktop hardware operates like this, but I think some mobile
hardware might. The ES group opted for uniformity among implementations
by requiring everyone to reject the same stuff... even if it could "just
work."
The thing that's a little bit weird about this code, and makes me
nervous about changing it too much, is that the checks depend on the ES
/ non-ES state of the shaders, not the API. I'd like to understand why
that was done in the first place before mucking with it... the change
you suggest may still be the right thing to do, I'm just not 100% sure.
>> Signed-off-by: Ian Romanick
>> ---
>> src/mesa/main/shader_query.cpp | 16 +++-
>> 1 file changed, 7 insertions(+), 9 deletions(-)
>>
>> diff --git a/src/mesa/main/shader_query.cpp
>> b/src/mesa/main/shader_query.cpp
>> index 9e18a1c..a120cb4 100644
>> --- a/src/mesa/main/shader_query.cpp
>> +++ b/src/mesa/main/shader_query.cpp
>> @@ -1372,7 +1372,7 @@ _mesa_get_program_resourceiv(struct
>> gl_shader_program *shProg,
>>
>> static bool
>> validate_io(const struct gl_shader *producer,
>> -const struct gl_shader *consumer, bool isES)
>> +const struct gl_shader *consumer)
>> {
>> assert(producer && consumer);
>> unsigned inputs = 0, outputs = 0;
>> @@ -1416,10 +1416,6 @@ validate_io(const struct gl_shader *producer,
>> * packing makes this challenging.
>> */
>>
>> - /* Currently no matching done for desktop. */
>> - if (!isES)
>> - return true;
>> -
>> /* For each output in a, find input in b and do any required
>> checks. */
>> foreach_in_list(ir_instruction, out, producer->ir) {
>>ir_variable *out_var = out->as_variable();
>> @@ -1501,10 +1497,12 @@ _mesa_validate_pipeline_io(struct
>> gl_pipeline_object *pipeline)
>> if (shProg[idx]->_LinkedShaders[idx]->Stage ==
>> MESA_SHADER_COMPUTE)
>> break;
>>
>> - if (!validate_io(shProg[prev]->_LinkedShaders[prev],
>> - shProg[idx]->_LinkedShaders[idx],
>> - shProg[prev]->IsES || shProg[idx]->IsES))
>> -return false;
>> + if (shProg[prev]->IsES || shProg[idx]->IsES) {
>> +if (!validate_io(shProg[prev]->_LinkedShaders[prev],
>> + shProg[idx]->_LinkedShaders[idx]))
>> + return false;
>> + }
>> +
>> prev = idx;
>>}
>> }
>
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Re: [Mesa-dev] [PATCH 0/7] i965, anv: Use ISL for querying surface format capabilities
On Tue, May 24, 2016 at 1:47 PM, Nanley Chery wrote: > On Mon, May 23, 2016 at 02:07:41PM -0700, Jason Ekstrand wrote: >> On Mon, May 23, 2016 at 10:41 AM, Nanley Chery >> wrote: >> >> > On Fri, May 20, 2016 at 06:12:34PM -0700, Jason Ekstrand wrote: >> > > This little series effectively moves the surface format table from >> > > brw_surface_formats.c into ISL. Previously, it got built into >> > > libi965_compiler.la because we needed to share it between drivers and >> > > didn't have a better place to put it. Now it can live in ISL where it >> > > belongs. >> > > >> > > When we pull it into ISL, we also clean up the API for querying a bit. >> > > Instead of simply having a table with gen numbers in it, everything uses >> > > isl_format_supports_* queries. This allows us to special-case things in >> > > cases where the table just doesn't quite work. For instance, there are a >> > > number of formats that become avilable for vertex fetch on Haswell and >> > Bay >> > > Trail but don't exist on Ivy Bridge. This isn't something the current >> > > table-based approach can handle properly. >> > > >> > >> > Pulling the table into ISL seems like a great idea and helpers shouldn't >> > hurt. It seems like the problem helpers would solve is the case when a >> > format loses its support in a future generation - has this happened with a >> > Gen introduction? For the example you stated, I think we could fix it by >> > giving Baytrail a gen number between 70 and 75. This would require scaling >> > up all brw_device_info::gen fields by 10 of course. >> > >> >> Yes, we could call Bay Trail 7.1 or something like that but we can't really >> guarantee that it will be monotonic. > > 7.1 sounds good. What can't we guarantee will be monotonic? You might have a situation where a feature exists in 70 and 75 but not 71, and another feature which exists in 70 and 71 but not 75. So there's no total order that will account for it. (No clue if such a set of features exists.) -ilia ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/7] i965, anv: Use ISL for querying surface format capabilities
On Mon, May 23, 2016 at 02:07:41PM -0700, Jason Ekstrand wrote: > On Mon, May 23, 2016 at 10:41 AM, Nanley Chery > wrote: > > > On Fri, May 20, 2016 at 06:12:34PM -0700, Jason Ekstrand wrote: > > > This little series effectively moves the surface format table from > > > brw_surface_formats.c into ISL. Previously, it got built into > > > libi965_compiler.la because we needed to share it between drivers and > > > didn't have a better place to put it. Now it can live in ISL where it > > > belongs. > > > > > > When we pull it into ISL, we also clean up the API for querying a bit. > > > Instead of simply having a table with gen numbers in it, everything uses > > > isl_format_supports_* queries. This allows us to special-case things in > > > cases where the table just doesn't quite work. For instance, there are a > > > number of formats that become avilable for vertex fetch on Haswell and > > Bay > > > Trail but don't exist on Ivy Bridge. This isn't something the current > > > table-based approach can handle properly. > > > > > > > Pulling the table into ISL seems like a great idea and helpers shouldn't > > hurt. It seems like the problem helpers would solve is the case when a > > format loses its support in a future generation - has this happened with a > > Gen introduction? For the example you stated, I think we could fix it by > > giving Baytrail a gen number between 70 and 75. This would require scaling > > up all brw_device_info::gen fields by 10 of course. > > > > Yes, we could call Bay Trail 7.1 or something like that but we can't really > guarantee that it will be monotonic. 7.1 sounds good. What can't we guarantee will be monotonic? - Nanley > --Jason > > > > - Nanley > > > > > Jason Ekstrand (6): > > > i965/surface_formats: Update the VB column for new formats added on > > > BYT > > > isl: Add support for quering the string name of a format > > > isl: Add the ISL_FORMAT_R32G32_FLOAT_LD format > > > isl: Add per-gen format introspection > > > anv/formats: Use isl_format_supports* for format introspection > > > i965: Use ISL for surface format introspection > > > > > > Nanley Chery (1): > > > i965: Unset alpha blend for R10G10B10_SNORM_A2_UNORM > > > > > > src/intel/isl/isl.h | 21 ++ > > > src/intel/isl/isl_format.c | 386 > > > > > src/intel/isl/isl_format_layout.csv | 1 + > > > src/intel/isl/isl_format_layout_gen.bash| 3 +- > > > src/intel/vulkan/anv_formats.c | 41 ++- > > > src/mesa/drivers/dri/i965/Makefile.sources | 3 +- > > > src/mesa/drivers/dri/i965/brw_context.h | 2 - > > > src/mesa/drivers/dri/i965/brw_state.h | 1 - > > > src/mesa/drivers/dri/i965/brw_state_dump.c | 8 +- > > > src/mesa/drivers/dri/i965/brw_surface_formats.c | 344 > > + > > > src/mesa/drivers/dri/i965/brw_surface_formats.h | 43 --- > > > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +- > > > 12 files changed, 448 insertions(+), 410 deletions(-) > > > delete mode 100644 src/mesa/drivers/dri/i965/brw_surface_formats.h > > > > > > -- > > > 2.5.0.400.gff86faf > > > > > > ___ > > > mesa-dev mailing list > > > mesa-dev@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/29] Make more use of bitmasks
On 05/24/2016 12:41 AM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich Hi all, following a series with performance improvements for cpu/draw bound applications. This part makes more use of the bitmask/ffs technique for iterating a set of enabled items. The gains are not huge but they are noticable for some of my favourite workloads. Please review! Overall looks good to me (though, see Roland's comment). I like the clean-ups. Reviewed-by: Brian Paul However, in gallium we have a u_bit_scan() helper function for looping over bitmasks. I wonder if we should use something like that in Mesa too. What do you think? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/6] update swr rasterizer
Reviewed-by: Bruce Cherniak minus the knob.h change to disable cut-aware primitive assembler. New change for that coming today. > On May 20, 2016, at 2:08 PM, Rowley, Timothy O > wrote: > > Bruce, is cut-aware needed for primitive restart? > >> On May 20, 2016, at 11:58 AM, Rowley, Timothy O >> wrote: >> >> Highlights this round are a frontend performance boost and >> removal of dead code. >> >> Unfortunately the instanceID/vertexID patch combines some style >> changes along with the code updates. I've tried separating it >> but haven't come up with something clean. >> >> Tim Rowley (6): >> swr: [rasterizer jitter] implement InstanceID/VertexID in fetch jit >> swr: [rasterizer core] move centroid setup out of >> CalcCentroidBarycentrics >> swr: [rasterizer core] buckets fixes >> swr: [rasterizer core] disable cut-aware primitive assembler >> swr: [rasterizer core] remove utility dead code >> swr: [rasterizer] remove containers.hpp >> >> src/gallium/drivers/swr/Makefile.sources | 2 - >> .../drivers/swr/rasterizer/common/containers.hpp | 208 - >> .../swr/rasterizer/common/rdtsc_buckets.cpp| 1 + >> .../drivers/swr/rasterizer/common/rdtsc_buckets.h | 13 +- >> .../drivers/swr/rasterizer/core/backend.cpp| 22 +- >> src/gallium/drivers/swr/rasterizer/core/backend.h | 13 - >> src/gallium/drivers/swr/rasterizer/core/knobs.h| 3 +- >> .../drivers/swr/rasterizer/core/rdtsc_core.cpp | 1 + >> .../drivers/swr/rasterizer/core/rdtsc_core.h | 5 +- >> src/gallium/drivers/swr/rasterizer/core/utils.cpp | 164 --- >> src/gallium/drivers/swr/rasterizer/core/utils.h| 92 >> .../drivers/swr/rasterizer/jitter/JitManager.cpp | 1 - >> .../drivers/swr/rasterizer/jitter/blend_jit.cpp| 1 - >> .../drivers/swr/rasterizer/jitter/builder_misc.cpp | 54 ++- >> .../drivers/swr/rasterizer/jitter/fetch_jit.cpp| 489 >> + >> .../drivers/swr/rasterizer/jitter/fetch_jit.h | 24 +- >> .../swr/rasterizer/jitter/streamout_jit.cpp| 1 - >> 17 files changed, 408 insertions(+), 686 deletions(-) >> delete mode 100644 src/gallium/drivers/swr/rasterizer/common/containers.hpp >> delete mode 100644 src/gallium/drivers/swr/rasterizer/core/utils.cpp >> >> -- >> 1.9.1 >> > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/14] Revert "mesa: Build EGL without X11 headers after interop patchset"
On Tue, May 24, 2016 at 03:32:44PM +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> This reverts commit 4e2c9a04354b6b133845b8b93c0c5d34261a91d0.
>
> The solution was incomplete and fragile. An alternative one is coming
> shortly.
Tested-by: Tom Stellard
> ---
> include/GL/mesa_glinterop.h | 15 +--
> 1 file changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/include/GL/mesa_glinterop.h b/include/GL/mesa_glinterop.h
> index 39822f2..814064d 100644
> --- a/include/GL/mesa_glinterop.h
> +++ b/include/GL/mesa_glinterop.h
> @@ -50,11 +50,7 @@
> #ifndef MESA_GLINTEROP_H
> #define MESA_GLINTEROP_H
>
> -#if defined(MESA_EGL_NO_X11_HEADERS)
> -#include
> -#else
> #include
> -#endif
> #include
>
> #ifdef __cplusplus
> @@ -223,7 +219,6 @@ typedef struct _mesa_glinterop_export_out {
> } mesa_glinterop_export_out;
>
>
> -#if !defined(MESA_EGL_NO_X11_HEADERS)
> /**
> * Query device information.
> *
> @@ -233,11 +228,9 @@ typedef struct _mesa_glinterop_export_out {
> *
> * \return MESA_GLINTEROP_SUCCESS or MESA_GLINTEROP_* != 0 on error
> */
> -
> GLAPI int GLAPIENTRY
> MesaGLInteropGLXQueryDeviceInfo(Display *dpy, GLXContext context,
> mesa_glinterop_device_info *out);
> -#endif
>
>
> /**
> @@ -249,7 +242,6 @@ MesaGLInteropEGLQueryDeviceInfo(EGLDisplay dpy,
> EGLContext context,
> mesa_glinterop_device_info *out);
>
>
> -#if !defined(MESA_EGL_NO_X11_HEADERS)
> /**
> * Create and return a DMABUF handle corresponding to the given OpenGL
> * object, and return other parameters about the OpenGL object.
> @@ -261,12 +253,10 @@ MesaGLInteropEGLQueryDeviceInfo(EGLDisplay dpy,
> EGLContext context,
> *
> * \return MESA_GLINTEROP_SUCCESS or MESA_GLINTEROP_* != 0 on error
> */
> -
> GLAPI int GLAPIENTRY
> MesaGLInteropGLXExportObject(Display *dpy, GLXContext context,
> const mesa_glinterop_export_in *in,
> mesa_glinterop_export_out *out);
> -#endif
>
>
> /**
> @@ -278,17 +268,14 @@ MesaGLInteropEGLExportObject(EGLDisplay dpy, EGLContext
> context,
> const mesa_glinterop_export_in *in,
> mesa_glinterop_export_out *out);
>
> -#if !defined(MESA_EGL_NO_X11_HEADERS)
> +
> typedef int (APIENTRYP PFNMESAGLINTEROPGLXQUERYDEVICEINFOPROC)(Display *dpy,
> GLXContext context,
>
> mesa_glinterop_device_info *out);
> -#endif
> typedef int (APIENTRYP PFNMESAGLINTEROPEGLQUERYDEVICEINFOPROC)(EGLDisplay
> dpy, EGLContext context,
>
> mesa_glinterop_device_info *out);
> -#if !defined(MESA_EGL_NO_X11_HEADERS)
> typedef int (APIENTRYP PFNMESAGLINTEROPGLXEXPORTOBJECTPROC)(Display *dpy,
> GLXContext context,
> const
> mesa_glinterop_export_in *in,
>
> mesa_glinterop_export_out *out);
> -#endif
> typedef int (APIENTRYP PFNMESAGLINTEROPEGLEXPORTOBJECTPROC)(EGLDisplay dpy,
> EGLContext context,
> const
> mesa_glinterop_export_in *in,
>
> mesa_glinterop_export_out *out);
> --
> 2.8.2
>
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