Re: [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine
On Wed, 10 Jan 2018 18:22:02 -0800 Michael Clark wrote: > This provides a RISC-V Board compatible with the the SiFive E300 SDK. > The following machine is implemented: > > - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM > > Signed-off-by: Michael Clark > --- > hw/riscv/sifive_e300.c | 232 > + > include/hw/riscv/sifive_e300.h | 79 ++ > 2 files changed, 311 insertions(+) > create mode 100644 hw/riscv/sifive_e300.c > create mode 100644 include/hw/riscv/sifive_e300.h > > diff --git a/hw/riscv/sifive_e300.c b/hw/riscv/sifive_e300.c > new file mode 100644 > index 000..bbea55a > --- /dev/null > +++ b/hw/riscv/sifive_e300.c > @@ -0,0 +1,232 @@ > +/* > + * QEMU RISC-V Board Compatible with SiFive E300 SDK > + * > + * Copyright (c) 2017 SiFive, Inc. > + * > + * Provides a board compatible with the bsp in the SiFive E300 SDK: > + * > + * 0) UART > + * 1) CLINT (Core Level Interruptor) > + * 2) PLIC (Platform Level Interrupt Controller) > + * 3) PRCI (Power, Reset, Clock, Interrupt) > + * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM > + * 5) Flash memory emulated as RAM > + * > + * The Mask ROM reset vector jumps to the flash payload at 0x2040_. > + * The OTP ROM and Flash boot code will be emulated in a future version. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a > copy > + * of this software and associated documentation files (the "Software"), to > deal > + * in the Software without restriction, including without limitation the > rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/log.h" > +#include "qemu/error-report.h" > +#include "hw/hw.h" > +#include "hw/boards.h" > +#include "hw/loader.h" > +#include "hw/sysbus.h" > +#include "hw/char/serial.h" > +#include "target/riscv/cpu.h" > +#include "hw/riscv/riscv_hart.h" > +#include "hw/riscv/sifive_plic.h" > +#include "hw/riscv/sifive_clint.h" > +#include "hw/riscv/sifive_prci.h" > +#include "hw/riscv/sifive_uart.h" > +#include "hw/riscv/sifive_e300.h" > +#include "chardev/char.h" > +#include "sysemu/arch_init.h" > +#include "exec/address-spaces.h" > +#include "elf.h" > + > +static const struct MemmapEntry { > +hwaddr base; > +hwaddr size; > +} sifive_e300_memmap[] = { > +[SIFIVE_E300_DEBUG] ={0x0, 0x100 }, > +[SIFIVE_E300_MROM] = { 0x1000, 0x2000 }, > +[SIFIVE_E300_OTP] = {0x2, 0x2000 }, > +[SIFIVE_E300_CLINT] ={ 0x200,0x1 }, > +[SIFIVE_E300_PLIC] = { 0xc00, 0x400 }, > +[SIFIVE_E300_AON] = { 0x1000, 0x8000 }, > +[SIFIVE_E300_PRCI] = { 0x10008000, 0x8000 }, > +[SIFIVE_E300_OTP_CTRL] = { 0x1001, 0x1000 }, > +[SIFIVE_E300_GPIO0] ={ 0x10012000, 0x1000 }, > +[SIFIVE_E300_UART0] ={ 0x10013000, 0x1000 }, > +[SIFIVE_E300_QSPI0] ={ 0x10014000, 0x1000 }, > +[SIFIVE_E300_PWM0] = { 0x10015000, 0x1000 }, > +[SIFIVE_E300_UART1] ={ 0x10023000, 0x1000 }, > +[SIFIVE_E300_QSPI1] ={ 0x10024000, 0x1000 }, > +[SIFIVE_E300_PWM1] = { 0x10025000, 0x1000 }, > +[SIFIVE_E300_QSPI2] ={ 0x10034000, 0x1000 }, > +[SIFIVE_E300_PWM2] = { 0x10035000, 0x1000 }, > +[SIFIVE_E300_XIP] = { 0x2000, 0x2000 }, > +[SIFIVE_E300_DTIM] = { 0x8000, 0x4000 } > +}; > + > +static uint64_t identity_translate(void *opaque, uint64_t addr) > +{ > +return addr; > +} > + > +static uint64_t load_kernel(const char *kernel_filename) > +{ > +uint64_t kernel_entry, kernel_high; > + > +if (load_elf(kernel_filename, identity_translate, NULL, > + &kernel_entry, NULL, &kernel_high, > + /* little_endian = */ 0, ELF_MACHINE, 1, 0) < 0) { "little_endian =" is misleading. Actually it's "big_endian = 0". The same comment is present in the U500 code. -- Best regards, Antony Pavlov
[Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine
This provides a RISC-V Board compatible with the the SiFive E300 SDK. The following machine is implemented: - 'sifive_e300'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM Signed-off-by: Michael Clark --- hw/riscv/sifive_e300.c | 232 + include/hw/riscv/sifive_e300.h | 79 ++ 2 files changed, 311 insertions(+) create mode 100644 hw/riscv/sifive_e300.c create mode 100644 include/hw/riscv/sifive_e300.h diff --git a/hw/riscv/sifive_e300.c b/hw/riscv/sifive_e300.c new file mode 100644 index 000..bbea55a --- /dev/null +++ b/hw/riscv/sifive_e300.c @@ -0,0 +1,232 @@ +/* + * QEMU RISC-V Board Compatible with SiFive E300 SDK + * + * Copyright (c) 2017 SiFive, Inc. + * + * Provides a board compatible with the bsp in the SiFive E300 SDK: + * + * 0) UART + * 1) CLINT (Core Level Interruptor) + * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM + * 5) Flash memory emulated as RAM + * + * The Mask ROM reset vector jumps to the flash payload at 0x2040_. + * The OTP ROM and Flash boot code will be emulated in a future version. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/hw.h" +#include "hw/boards.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/char/serial.h" +#include "target/riscv/cpu.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_prci.h" +#include "hw/riscv/sifive_uart.h" +#include "hw/riscv/sifive_e300.h" +#include "chardev/char.h" +#include "sysemu/arch_init.h" +#include "exec/address-spaces.h" +#include "elf.h" + +static const struct MemmapEntry { +hwaddr base; +hwaddr size; +} sifive_e300_memmap[] = { +[SIFIVE_E300_DEBUG] ={0x0, 0x100 }, +[SIFIVE_E300_MROM] = { 0x1000, 0x2000 }, +[SIFIVE_E300_OTP] = {0x2, 0x2000 }, +[SIFIVE_E300_CLINT] ={ 0x200,0x1 }, +[SIFIVE_E300_PLIC] = { 0xc00, 0x400 }, +[SIFIVE_E300_AON] = { 0x1000, 0x8000 }, +[SIFIVE_E300_PRCI] = { 0x10008000, 0x8000 }, +[SIFIVE_E300_OTP_CTRL] = { 0x1001, 0x1000 }, +[SIFIVE_E300_GPIO0] ={ 0x10012000, 0x1000 }, +[SIFIVE_E300_UART0] ={ 0x10013000, 0x1000 }, +[SIFIVE_E300_QSPI0] ={ 0x10014000, 0x1000 }, +[SIFIVE_E300_PWM0] = { 0x10015000, 0x1000 }, +[SIFIVE_E300_UART1] ={ 0x10023000, 0x1000 }, +[SIFIVE_E300_QSPI1] ={ 0x10024000, 0x1000 }, +[SIFIVE_E300_PWM1] = { 0x10025000, 0x1000 }, +[SIFIVE_E300_QSPI2] ={ 0x10034000, 0x1000 }, +[SIFIVE_E300_PWM2] = { 0x10035000, 0x1000 }, +[SIFIVE_E300_XIP] = { 0x2000, 0x2000 }, +[SIFIVE_E300_DTIM] = { 0x8000, 0x4000 } +}; + +static uint64_t identity_translate(void *opaque, uint64_t addr) +{ +return addr; +} + +static uint64_t load_kernel(const char *kernel_filename) +{ +uint64_t kernel_entry, kernel_high; + +if (load_elf(kernel_filename, identity_translate, NULL, + &kernel_entry, NULL, &kernel_high, + /* little_endian = */ 0, ELF_MACHINE, 1, 0) < 0) { +error_report("qemu: could not load kernel '%s'", kernel_filename); +exit(1); +} +return kernel_entry; +} + +static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, + uintptr_t offset, uintptr_t length) +{ +MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); +memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); +memory_region_add_subregion(parent, offset, mock_mmio); +} + +static void riscv_sifive_e300_init(MachineState *machine) +{ +const struct MemmapEntry *memm