Re: [U-Boot] [PATCH 01/12] clk: rmobile: Split R8A7795 and R8A7796 core clock tables
Hi,
2017-08-21 0:13 GMT+09:00 Marek Vasut :
> The R8A7795 and R8A7796 tables use different constants to identify
> clock in DT, so split the tables and use the correct constants on
> R8A7795. This fixes UART clock misconfiguration on R8A7795.
>
> Signed-off-by: Marek Vasut
> Cc: Nobuhiro Iwamatsu
> ---
> drivers/clk/renesas/clk-rcar-gen3.c | 129
> +++-
> 1 file changed, 96 insertions(+), 33 deletions(-)
Applied, thanks.
Best regards,
Nobuhiro
>
> diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
> b/drivers/clk/renesas/clk-rcar-gen3.c
> index 5ea7d9a1f5..4e74856940 100644
> --- a/drivers/clk/renesas/clk-rcar-gen3.c
> +++ b/drivers/clk/renesas/clk-rcar-gen3.c
> @@ -73,6 +73,8 @@ struct gen3_clk_priv {
> struct clk clk_extal;
> struct clk clk_extalr;
> const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
> + const struct cpg_core_clk *core_clk;
> + u32 core_clk_size;
> const struct mssr_mod_clk *mod_clk;
> u32 mod_clk_size;
> };
> @@ -181,7 +183,7 @@ enum clk_ids {
> MOD_CLK_BASE
> };
>
> -static const struct cpg_core_clk gen3_core_clks[] = {
> +static const struct cpg_core_clk r8a7795_core_clks[] = {
> /* External Clock Inputs */
> DEF_INPUT("extal", CLK_EXTAL),
> DEF_INPUT("extalr", CLK_EXTALR),
> @@ -203,38 +205,38 @@ static const struct cpg_core_clk gen3_core_clks[] = {
> DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
>
> /* Core Clock Outputs */
> - DEF_FIXED("ztr",R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
> - DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
> - DEF_FIXED("zt", R8A7796_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
> - DEF_FIXED("zx", R8A7796_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
> - DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
> - DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
> - DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
> - DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
> - DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
> - DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
> - DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0,12, 1),
> - DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
> - DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
> - DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
> - DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
> - DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
> - DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
> - DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
> - DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
> - DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
> -
> - DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
> - DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
> - DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
> - DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
> -
> - DEF_FIXED("cl", R8A7796_CLK_CL,CLK_PLL1_DIV2, 48, 1),
> - DEF_FIXED("cp", R8A7796_CLK_CP,CLK_EXTAL, 2, 1),
> + DEF_FIXED("ztr",R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
> + DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
> + DEF_FIXED("zt", R8A7795_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
> + DEF_FIXED("zx", R8A7795_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
> + DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
> + DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
> + DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
> + DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
> + DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
> + DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
> + DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0,12, 1),
> + DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
> + DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
> + DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
> + DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
> + DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
> + DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
> + DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
> + DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3,
[U-Boot] [PATCH 01/12] clk: rmobile: Split R8A7795 and R8A7796 core clock tables
The R8A7795 and R8A7796 tables use different constants to identify
clock in DT, so split the tables and use the correct constants on
R8A7795. This fixes UART clock misconfiguration on R8A7795.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/clk/renesas/clk-rcar-gen3.c | 129 +++-
1 file changed, 96 insertions(+), 33 deletions(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
b/drivers/clk/renesas/clk-rcar-gen3.c
index 5ea7d9a1f5..4e74856940 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -73,6 +73,8 @@ struct gen3_clk_priv {
struct clk clk_extal;
struct clk clk_extalr;
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
+ const struct cpg_core_clk *core_clk;
+ u32 core_clk_size;
const struct mssr_mod_clk *mod_clk;
u32 mod_clk_size;
};
@@ -181,7 +183,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk gen3_core_clks[] = {
+static const struct cpg_core_clk r8a7795_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -203,38 +205,38 @@ static const struct cpg_core_clk gen3_core_clks[] = {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
- DEF_FIXED("ztr",R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A7796_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A7796_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED("s0d1", R8A7796_CLK_S0D1, CLK_S0, 1, 1),
- DEF_FIXED("s0d2", R8A7796_CLK_S0D2, CLK_S0, 2, 1),
- DEF_FIXED("s0d3", R8A7796_CLK_S0D3, CLK_S0, 3, 1),
- DEF_FIXED("s0d4", R8A7796_CLK_S0D4, CLK_S0, 4, 1),
- DEF_FIXED("s0d6", R8A7796_CLK_S0D6, CLK_S0, 6, 1),
- DEF_FIXED("s0d8", R8A7796_CLK_S0D8, CLK_S0, 8, 1),
- DEF_FIXED("s0d12", R8A7796_CLK_S0D12, CLK_S0,12, 1),
- DEF_FIXED("s1d1", R8A7796_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A7796_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A7796_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A7796_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A7796_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A7796_CLK_S2D4, CLK_S2, 4, 1),
- DEF_FIXED("s3d1", R8A7796_CLK_S3D1, CLK_S3, 1, 1),
- DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
- DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
-
- DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
- DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
- DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
- DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
-
- DEF_FIXED("cl", R8A7796_CLK_CL,CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A7796_CLK_CP,CLK_EXTAL, 2, 1),
+ DEF_FIXED("ztr",R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A7795_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A7795_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
+ DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
+ DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
+ DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0,12, 1),
+ DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s2d1", R8A7795_CLK_S2D1, CLK_S2, 1, 1),
+ DEF_FIXED("s2d2", R8A7795_CLK_S2D2, CLK_S2, 2, 1),
+ DEF_FIXED("s2d4", R8A7795_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("s3d1", R8A7795_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
+
+ DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
+ DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
+ DEF_GEN3_SD("s
