[PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself. v2: simplify code Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu

Re: Proposal to add CRIU support to DRM render nodes

On 2024-03-28 12:03, Tvrtko Ursulin wrote: Hi Felix, I had one more thought while browsing around the amdgpu CRIU plugin. It appears it relies on the KFD support being compiled in and /dev/kfd present, correct? AFAICT at least, it relies on that to figure out the amdgpu DRM node. In woul

[PATCH 41/43] drm/amd/display: Includes adjustments

From: Rodrigo Siqueira This commit clean up some of the includes used by DCN. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c | 4 drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dio_link_encoder.c | 2 -- .../gpu/drm

[PATCH 42/43] drm/amd/display: Add color logs for dcn20

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dc

[PATCH 39/43] drm/amd/display: Add WBSCL ram coefficient for writeback

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_

[PATCH 33/43] drm/amd/display: Drop legacy code

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h| 10 -- .../amd/display/dc/gpio/dcn21/hw_translate_dcn21.c | 13 - 2 files changed, 23 deletions(-) diff --git a/drivers/gpu/drm/amd/d

[PATCH 31/43] drm/amd/display: Add some missing debug registers

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 4 .../include/asic_reg/dcn/dcn_3_0_0_offset.h | 24 +++ .../include/asic_reg/dcn/dcn_3_0_0_sh_mask.h | 9 +++ .../include/asic_reg

[PATCH 37/43] drm/amd/display: Initialize debug variable data

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn

[PATCH 38/43] drm/amd/display: Fix MPCC DTN logging

From: Eric Bernstein [Why] DTN only logs 'pipe_count' instances of MPCC. However in some cases there are different number of MPCC than DPP (pipe_count). [How] Add mpcc_count parameter to resource_pool and set it during pool construction and use it for DTN logging of MPCC state. Signed-off-by: E

[PATCH 36/43] drm/amd/display: Add missing SFB and OPP_SF

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_inp

[PATCH 34/43] drm/amd/display: Add missing registers

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../include/asic_reg/dcn/dcn_3_0_3_offset.h | 20 +++ .../include/asic_reg/dcn/dcn_3_0_3_sh_mask.h | 11 .../include/asic_reg/dcn/dcn_3_1_2_offset.h | 4 ++ .../include/asic_reg/dcn/dcn_3_1_2_sh

[PATCH 43/43] drm/amd/display: Enable FGCG for DCN351

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c| 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/dis

[PATCH 28/43] drm/amd/display: Initialize DP ref clk with the correct clock

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/dr

[PATCH 29/43] drm/amd/display: Set alpha enable to 0 for some specific formats

From: Rodrigo Siqueira Set alpha_en to 0 in some specific color formats. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dp

[PATCH 30/43] drm/amd/display: Enable cur_rom_en even if cursor degamma is not enabled

From: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/d

[PATCH 35/43] drm/amd/display: Remove redundant RESERVE0 and RESERVE1

From: Rodrigo Siqueira This commit drops the RESERVE0 and RESERVE1 since both of them can be summarized as RESERVED. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a

[PATCH 25/43] drm/amd/display: Fix compiler warnings on high compiler warning levels

From: Aric Cyr [why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues. [how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables

[PATCH 32/43] drm/amd/display: Update DSC compute parameter calculation

From: Rodrigo Siqueira Adjust bytes per pixel calculation to use div_u64. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/ds

[PATCH 40/43] drm/amd/display: Add code comments clock and encode code

From: Rodrigo Siqueira This commit adds some comments to make easier to understand the clock update for DCN 201, the encode function, and other minor comments. Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler --- .../amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c| 11 +++

[PATCH 26/43] drm/amd/display: Allow RCG for Static Screen + LVP for DCN35

From: Roman Li [Why] We want to block IPS2 for static screen but allow it for power state transitions. [How] Set DalDisableIPS=6 for DCN35 which allows: 1. RCG during static screen 2. RCG during LVP 3. IPS2 for display off / S0i3 Reviewed-by: Nicholas Kazlauskas Acked-by: Roman Li Signed-off-

[PATCH 22/43] drm/amd/display: remove context->dml2 dependency from DML21 wrapper

From: Joshua Aberback [Why] When the DML2 wrapper explicitly accesses context->dml2, that creates a dependency on where dc saves the DML object. This dependency makes it harder to have multiple co-existing DML objects, which we would like to have for upcoming functionality. [How] - make all DML

[PATCH 27/43] drm/amd/display: 3.2.279

From: Aric Cyr This version pairs with DMUB FW Release 0.0.211.0 for dcn314, dcn35, dcn351 and brings along the following: - Fix underflow in subvp/non-subvp configs - Fix compiler warnings - Add handling for DC power mode - Add extra logging for DMUB, HUBP and OTG - Add timing pixel encodi

[PATCH 20/43] drm/amd/display: add root clock control function pointer to fix display corruption

From: "Xi (Alex) Liu" [Why and how] External display has corruption because no root clock control function. Add the function pointer to fix the issue. Reviewed-by: Daniel Miess Reviewed-by: Nicholas Kazlauskas Acked-by: Roman Li Signed-off-by: Xi (Alex) Liu Tested-by: Daniel Wheeler ---

[PATCH 23/43] drm/amd/display: Add handling for DC power mode

From: Joshua Aberback [Why] Future implementations will require a distinction between AC power and DC power (wall power and battery power, respectively). To accomplish this, adding a power mode parameter to certain dc interfaces, and adding a separate DML2 instance for DC mode validation. Default

[PATCH 19/43] drm/amd/display: Disable Z8 minimum stutter period check for DCN35

From: Nicholas Kazlauskas [Why] The threshold is no longer useful for blocking suboptimal power states for DCN35 based on real measurement. [How] Reduce to the minimum threshold duration, 1us. Reviewed-by: Gabe Teeger Acked-by: Roman Li Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wh

[PATCH 24/43] drm/amd/display: move build test pattern params as part of pipe resource update for odm

From: Wenjing Liu [why] Move built test pattern as part of pipe resource update for odm to ensure we rebuild test pattern params every time we have an ODM update Reviewed-by: George Shen Acked-by: Roman Li Signed-off-by: Wenjing Liu Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display

[PATCH 21/43] drm/amd/display: Add extra DMUB logging to track message timeout

From: Alvin Lee [Description] - Add logging for first DMUB inbox message that timed out to diagnostic data - It is useful to track the first failed message for debug purposes because once DMUB becomes hung (typically on a message), it will remain hung and all subsequent messages. In these c

[PATCH 14/43] drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35

From: Daniel Miess [Why & How] Enable root clock optimization for HDMISTREAMCLK and only disable it when it's actively being used. Reviewed-by: Charlene Liu Acked-by: Roman Li Signed-off-by: Daniel Miess Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h| 1 +

[PATCH 18/43] drm/amd/display: Add extra logging for HUBP and OTG

From: Alvin Lee [Description] Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL, OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more debuggability for a system crash. Reviewed-by: Samson Tam Acked-by: Roman Li Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/di

[PATCH 16/43] drm/amd/display: Skip on writeback when it's not applicable

From: Alex Hung [WHY] dynamic memory safety error detector (KASAN) catches and generates error messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not support certain features which are not initialized. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Link:

[PATCH 17/43] drm/amd/display: Add OTG check for set AV mute

From: "Leo (Hanghong) Ma" [Why && How] OTG can be disabled before setting dpms on. Add check to skip wait when setting AV mute if OTG is disabled. Reviewed-by: Wenjing Liu Acked-by: Roman Li Signed-off-by: Leo (Hanghong) Ma Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/d

[PATCH 15/43] drm/amd/display: Allow HPO PG for DCN35

From: Duncan Ma [Why] HPO can be power gated unconditionally for DCN35. [How] Set disable flag to false. Reviewed-by: Nicholas Kazlauskas Acked-by: Roman Li Signed-off-by: Duncan Ma Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +- 1 file

[PATCH 11/43] drm/amd/display: update pipe topology log to support subvp

From: Wenjing Liu [why] There is an ambiguity in subvp pipe topology log. The log doesn't show subvp relation to main stream and it is not clear that certain stream is an internal stream for subvp pipes. [how] Separate subvp pipe topology logging from main pipe topology. Log main stream indices

[PATCH 08/43] drm/amd/display: FEC overhead should be checked once for mst slot nums

From: Hersen Wu [Why] Mst slot nums equals to pbn / pbn_div. Today, pbn_div refers to dm_mst_get_pbn_divider -> dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps, which includes effect of FEC overhead already. As result, we should not include effect of FEC overhead again while calculating pbn by

[PATCH 13/43] drm/amd/display: Add dummy interface for tracing DCN32 SMU messages

From: George Shen [Why/How] Some issues may require a trace of the previous SMU messages from DC to understand the context and aid in debugging. Actual logging to be implemented when needed. Reviewed-by: Josip Pavic Acked-by: Roman Li Signed-off-by: George Shen Tested-by: Daniel Wheeler ---

[PATCH 10/43] drm/amd/display: Add dmub additional interface support for FAMS

From: Dillon Varone [WHY&HOW] Update dmub and driver interface for future FAMS revisions. Reviewed-by: Anthony Koo Acked-by: Roman Li Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hws

[PATCH 05/43] drm/amd/display: Toggle additional RCO options in DCN35

From: Daniel Miess [Why] With root clock optimization now enabled for DCN35 there are still RCO registers still not being toggled [How] Add in logic to toggle RCO registers for DPPCLK, DPSTREAMCLK and DSCCLK Reviewed-by: Charlene Liu Acked-by: Roman Li Signed-off-by: Daniel Miess Tested-by:

[PATCH 12/43] drm/amd/display: Enable DTBCLK DTO earlier in the sequence

From: Sung Joon Kim [why] As per programming guide, we need to enable the virtual pixel clock via DTBCLK DTO and ungate the clock before we begin programming OPP/OPTC control registers. Otherwise, the double-buffered registers will be left pending until the clocks are enabled. [how] Move the DTB

[PATCH 07/43] drm/amd/display: Expand supported Replay residency mode

From: Leon Huang [Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by: Robin Chen Acked-by: Roman Li Signed-off-by: L

[PATCH 06/43] drm/amd/display: Decouple dcn35 and dcn351 dmub firmware

From: Roman Li [Why] dcn351 dmub fw was decoupled from dcn35. [How] Add dcn351 dmub fw load path. Reviewed-by: Rodrigo Siqueira Acked-by: Roman Li Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++- 1 file changed, 6 insertio

[PATCH 09/43] drm/amd/display: handle invalid connector indices

From: Joshua Aberback [Why] The function to count the number of valid connectors does not guarantee that the first n indices are valid, only that there exist n valid indices. When invalid indices are present, this results in later valid connectors being missed, as processing would end after check

[PATCH 03/43] drm/amd/display: fix underflow in some two display subvp/non-subvp configs

From: Samson Tam [Why] In two display configuration, switching between subvp and non-subvp may cause underflow because it moves an existing pipe between displays [How] Create helper function for applying pipe split flags Apply pipe split flags prior to deciding on subvp During subvp check, do

[PATCH 01/43] drm/amd/display: Fix compiler redefinition warnings for certain configs

From: Mounika Adhuri [why & how] Modified definitions of 1 function and 2 structs to remove warnings on certain specific compiler configurations due to redefinition. Reviewed-by: Martin Leung Acked-by: Roman Li Signed-off-by: Mounika Adhuri Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/

[PATCH 04/43] drm/amd/display: optimize dml2 pipe resource allocation order

From: Wenjing Liu [why] There could be cases that we are transition from MPC to ODM combine. In this case if we map pipes before unmapping MPC pipes, we might temporarly run out of pipes. The change reorders pipe resource allocation. So we unmapping pipes before mapping new pipes. Reviewed-by: D

[PATCH 02/43] drm/amd/display: Add timing pixel encoding for mst mode validation

From: Hersen Wu [Why] Mode pbn is not calculated correctly because timing pixel encoding is not checked within convert_dc_color_depth_into_bpc. [How] Get mode kbps from dc_bandwidth_in_kbps_from_timing, then calculate pbn by kbps_to_peak_pbn. Reviewed-by: Wayne Lin Acked-by: Roman Li Signed-o

[PATCH 00/43] DC Patches Apr 1, 2024

From: Roman Li This DC patchset brings improvements in multiple areas. In summary, we have: - Fix underflow in subvp/non-subvp configs - Fix compiler warnings - Add handling for DC power mode - Add extra logging for DMUB, HUBP and OTG - Add timing pixel encoding for mst mode validation - Expand

Re: [PATCH] drm/amdgpu: use vm_update_mode=0 as default in sriov for gfx10.3 onwards

On 2024-03-28 13:59, Danijel Slivka wrote: Apply this rule to all newer asics in sriov case. For asic with VF MMIO access protection avoid using CPU for VM table updates. CPU pagetable updates have issues with HDP flush as VF MMIO access protection blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_C

[linux-next:master] BUILD REGRESSION a6bd6c9333397f5a0e2667d4d82fef8c970108f2

tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master branch HEAD: a6bd6c997f5a0e2667d4d82fef8c970108f2 Add linux-next specific files for 20240328 Error/Warning: (recently discovered and may have been fixed) ERROR: modpost: "memcpy&quo

[PATCH] drm/amdgpu: use vm_update_mode=0 as default in sriov for gfx10.3 onwards

Apply this rule to all newer asics in sriov case. For asic with VF MMIO access protection avoid using CPU for VM table updates. CPU pagetable updates have issues with HDP flush as VF MMIO access protection blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register during sriov runti

Re: [PATCH v9 1/3] drm/buddy: Implement tracking clear page feature

On 28/03/2024 16:07, Paneer Selvam, Arunpravin wrote: Hi Matthew, On 3/26/2024 11:39 PM, Matthew Auld wrote: On 18/03/2024 21:40, Arunpravin Paneer Selvam wrote: - Add tracking clear page feature. - Driver should enable the DRM_BUDDY_CLEARED flag if it    successfully clears the blocks in the

Re: [PATCH v9 1/3] drm/buddy: Implement tracking clear page feature

Hi Matthew, On 3/26/2024 11:39 PM, Matthew Auld wrote: On 18/03/2024 21:40, Arunpravin Paneer Selvam wrote: - Add tracking clear page feature. - Driver should enable the DRM_BUDDY_CLEARED flag if it    successfully clears the blocks in the free path. On the otherhand,    DRM buddy marks each b

Re: Proposal to add CRIU support to DRM render nodes

Hi Felix, I had one more thought while browsing around the amdgpu CRIU plugin. It appears it relies on the KFD support being compiled in and /dev/kfd present, correct? AFAICT at least, it relies on that to figure out the amdgpu DRM node. In would be probably good to consider designing thin

Re: [PATCH 1/2] drm/amd/display: Introduce overlay cursor mode

On 2024-03-28 11:48, Robert Mader wrote: Hi, On 15.03.24 18:09, sunpeng...@amd.com wrote: From: Leo Li [Why] DCN is the display hardware for amdgpu. DRM planes are backed by DCN hardware pipes, which carry pixel data from one end (memory), to the other (output encoder). Each DCN pipe has

Re: [PATCH] drm/amdgpu: Fix VCN allocation in CPX partition

[AMD Official Use Only - General] Acked-by: Alex Deucher From: Lazar, Lijo Sent: Wednesday, March 27, 2024 10:05 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Deucher, Alexander ; Zhu, James ; Kamal, Asad Subject: [PATCH] drm/amdgpu: Fix VCN alloc

[PATCH v3 02/14] ARM: Implement ARCH_HAS_KERNEL_FPU_SUPPORT

ARM provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. Add a wrapper header, and export CFLAGS adjustments as found in lib/raid6/Makefile. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v2)

Re: [PATCH v3 12/14] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT

On Wed, 27 Mar 2024 13:00:43 -0700 Samuel Holland wrote: > Now that all previously-supported architectures select > ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead > of the existing list of architectures. It can also take advantage of the > common kernel-mode FPU API and

[PATCH v3 01/14] arch: Add ARCH_HAS_KERNEL_FPU_SUPPORT

Several architectures provide an API to enable the FPU and run floating-point SIMD code in kernel space. However, the function names, header locations, and semantics are inconsistent across architectures, and FPU support may be gated behind other Kconfig options. Provide a standard way for archite

[PATCH v3 08/14] powerpc: Implement ARCH_HAS_KERNEL_FPU_SUPPORT

PowerPC provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. The PowerPC API also requires a non-preemptible context. Add a wrapper header, and export the CFLAGS adjustments. Acked-by: Michael Ellerman (powerpc) Reviewed-by: Chris

[PATCH v3 00/14] Unified cross-architecture kernel-mode FPU API

This series unifies the kernel-mode FPU API across several architectures by wrapping the existing functions (where needed) in consistently-named functions placed in a consistent header location, with mostly the same semantics: they can be called from preemptible or non-preemptible task context, and

[PATCH v3 06/14] lib/raid6: Use CC_FLAGS_FPU for NEON CFLAGS

Now that CC_FLAGS_FPU is exported and can be used anywhere in the source tree, use it instead of duplicating the flags here. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v1) lib/raid6/Makefile | 31 --- 1 file changed, 8 insert

[PATCH v3 10/14] riscv: Add support for kernel-mode FPU

This is motivated by the amdgpu DRM driver, which needs floating-point code to support recent hardware. That code is not performance-critical, so only provide a minimal non-preemptible implementation for now. Support is limited to riscv64 because riscv32 requires runtime (libgcc) assistance to con

[PATCH v3 09/14] x86: Implement ARCH_HAS_KERNEL_FPU_SUPPORT

x86 already provides kernel_fpu_begin() and kernel_fpu_end(), but in a different header. Add a wrapper header, and export the CFLAGS adjustments as found in lib/Makefile. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v1) arch/x86/Kconfig | 1 +

[PATCH v3 07/14] LoongArch: Implement ARCH_HAS_KERNEL_FPU_SUPPORT

LoongArch already provides kernel_fpu_begin() and kernel_fpu_end() in asm/fpu.h, so it only needs to add kernel_fpu_available() and export the CFLAGS adjustments. Acked-by: WANG Xuerui Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- Changes in v3: - Rebase on v6.9-rc1 arch/

[PATCH v3 11/14] drm/amd/display: Only use hard-float, not altivec on powerpc

From: Michael Ellerman The compiler flags enable altivec, but that is not required; hard-float is sufficient for the code to build and function. Drop altivec from the compiler flags and adjust the enable/disable code to only enable FPU use. Signed-off-by: Michael Ellerman Acked-by: Alex Deuche

[PATCH v3 03/14] ARM: crypto: Use CC_FLAGS_FPU for NEON CFLAGS

Now that CC_FLAGS_FPU is exported and can be used anywhere in the source tree, use it instead of duplicating the flags here. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v1) arch/arm/lib/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) di

Re: [PATCH v3 12/14] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT

On 2024-03-27 4:25 PM, Andrew Morton wrote: > On Wed, 27 Mar 2024 13:00:43 -0700 Samuel Holland > wrote: > >> Now that all previously-supported architectures select >> ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead >> of the existing list of architectures. It can also t

[PATCH v3 04/14] arm64: Implement ARCH_HAS_KERNEL_FPU_SUPPORT

arm64 provides an equivalent to the common kernel-mode FPU API, but in a different header and using different function names. Add a wrapper header, and export CFLAGS adjustments as found in lib/raid6/Makefile. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v2

[PATCH v3 12/14] drm/amd/display: Use ARCH_HAS_KERNEL_FPU_SUPPORT

Now that all previously-supported architectures select ARCH_HAS_KERNEL_FPU_SUPPORT, this code can depend on that symbol instead of the existing list of architectures. It can also take advantage of the common kernel-mode FPU API and method of adjusting CFLAGS. Acked-by: Alex Deucher Reviewed-by: C

[PATCH v3 13/14] selftests/fpu: Move FP code to a separate translation unit

This ensures no compiler-generated floating-point code can appear outside kernel_fpu_{begin,end}() sections, and some architectures enforce this separation. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v2) Changes in v2: - Declare test_fpu() in a header

[PATCH v3 05/14] arm64: crypto: Use CC_FLAGS_FPU for NEON CFLAGS

Now that CC_FLAGS_FPU is exported and can be used anywhere in the source tree, use it instead of duplicating the flags here. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v2) Changes in v2: - New patch for v2 arch/arm64/lib/Makefile | 6 ++ 1 file ch

[PATCH v3 14/14] selftests/fpu: Allow building on other architectures

Now that ARCH_HAS_KERNEL_FPU_SUPPORT provides a common way to compile and run floating-point code, this test is no longer x86-specific. Reviewed-by: Christoph Hellwig Signed-off-by: Samuel Holland --- (no changes since v1) lib/Kconfig.debug | 2 +- lib/Makefile| 25 ++--

RE: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

[AMD Official Use Only - General] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: amd-gfx On Behalf Of Tao Zhou Sent: Thursday, March 28, 2024 18:28 To: amd-gfx@lists.freedesktop.org Cc: Zhou1, Tao Subject: [PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4

Re: [PATCH v3 1/5] drm/amdgpu: Add a new runtime mode definition

On 3/27/2024 4:40 PM, Ma Jun wrote: > Add a new runtime pm mode AMDGPU_RUNPM_BAMACO > and related macro definition > > Signed-off-by: Ma Jun Series is Reviewed-by: Lijo Lazar Thanks, Lijo > --- > drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 > 1 file changed, 4 insertions(+) > > dif

[PATCH] drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

SDMA_CNTL is not set in some cases, driver configures it by itself. Signed-off-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

Re: [RFC PATCH v3 3/6] drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid

On Wed, 27 Mar 2024, Melissa Wen wrote: > Replace raw edid handling (struct edid) with the opaque EDID type > (struct drm_edid) on amdgpu_dm_connector for consistency. It may also > prevent mismatch of approaches in different parts of the driver code. > Working in progress. It was only exercised w

Re: [RFC PATCH v3 0/6] drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid

On Wed, 27 Mar 2024, Melissa Wen wrote: > 2. Most of the edid data handled by `dm_helpers_parse_edid_caps()` are >in drm_edid halpers, but there are still a few that are not managed by >them yet. For example: >``` > edid_caps->serial_number = edid_buf->serial; > edid_caps->

RE: [PATCH v2 4/4] drm/amd/pm: Categorize RAS messages on SMUv13.0.6

[AMD Official Use Only - General] Series is Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Lazar, Lijo Sent: Thursday, March 28, 2024 10:36 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Deucher, Alexander ; Wang, Yang(Kevin) Subject: [PATCH v2 4/4] drm/

RE: [PATCH] drm/amd/pm: fix the high voltage issue after unload

[AMD Official Use Only - General] Reviewed-by: Hawking Zhang Regards, Hawking -Original Message- From: Kenneth Feng Sent: Thursday, March 28, 2024 14:02 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Feng, Kenneth Subject: [PATCH] drm/amd/pm: fix the high voltage issue after un