Subject: RE: [PATCH] drm/amdgpu: refine cz uvd clock gate logic.
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, November 11, 2016 12:25 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subjec
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, November 11, 2016 12:25 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH] drm/amdgpu: refine cz uvd clock gate logic.
>
On Fri, Nov 11, 2016 at 12:24 AM, Rex Zhu wrote:
> sw clockgate was used on uvd6.0.
> when uvd is idle, we gate the uvd clock.
> when decode, we ungate the uvd clock.
>
> Change-Id: I79ecdc5d0f48e97919386a08acca994f1fa05484
> Signed-off-by: Rex Zhu
Reviewed-by: Alex Deucher
> ---
> drivers/gp
sw clockgate was used on uvd6.0.
when uvd is idle, we gate the uvd clock.
when decode, we ungate the uvd clock.
Change-Id: I79ecdc5d0f48e97919386a08acca994f1fa05484
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 6 ++
drivers/gpu/drm/amd/powerplay/hwmg
