On Fri, Apr 3, 2026 at 5:34 AM Jesse Zhang wrote:
>
> Previously, the per-pipe reset sequence was incorrect, leading to unreliable
> recovery and potential firmware hangs. The reset logic has now been fixed
> to properly handle HQD cleanup while the pipe is held in reset before
> bringing it out of reset.
>
> Signed-off-by: Jesse Zhang
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 7aa3853f8db7..17c590444af4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -1563,6 +1563,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block
> *ip_block)
> !amdgpu_sriov_vf(adev) &&
> !adev->debug_disable_gpu_ring_reset) {
> adev->gfx.compute_supported_reset |=
> AMDGPU_RESET_TYPE_PER_QUEUE;
> + adev->gfx.compute_supported_reset |=
> AMDGPU_RESET_TYPE_PER_PIPE;
> adev->gfx.gfx_supported_reset |=
> AMDGPU_RESET_TYPE_PER_QUEUE;
> }
> break;
> @@ -5362,6 +5363,11 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring
> *ring,
> return amdgpu_ring_reset_helper_end(ring, timedout_fence);
> }
>
> +static bool gfx_v12_compute_pipe_reset_support(struct amdgpu_device *adev)
> +{
> + return !!(adev->gfx.compute_supported_reset &
> AMDGPU_RESET_TYPE_PER_PIPE);
> +}
I think you can replace both gfx_v12_compute_pipe_reset_support() and
gfx_v12_pipe_reset_support() with
amdgpu_ring_is_reset_type_supported(ring, AMDGPU_RESET_TYPE_PER_PIPE).
Alex
> +
> /*
> * With MEC pipe reset asserted, clear CP_HQD_ACTIVE /
> CP_HQD_DEQUEUE_REQUEST for
> * every queue on (me, pipe). HQDs must be torn down while pipe reset stays
> @@ -5396,7 +5402,7 @@ static int gfx_v12_0_reset_compute_pipe(struct
> amdgpu_ring *ring)
> uint32_t reset_val, clean_val;
> int r = 0;
>
> - if (!gfx_v12_pipe_reset_support(adev))
> + if (!gfx_v12_compute_pipe_reset_support(adev))
> return -EOPNOTSUPP;
>
> gfx_v12_0_set_safe_mode(adev, 0);
> --
> 2.49.0
>
