Re: [PATCH 1/2] drm/amdgpu: Use asic specific pa mask

2026-05-13 Thread Kasiviswanathan, Harish 
AMD General





From: Lazar, Lijo 
Sent: Wednesday, May 13, 2026 5:43 AM
To: Kasiviswanathan, Harish ; 
[email protected] 
Subject: Re: [PATCH 1/2] drm/amdgpu: Use asic specific pa mask



On 13-May-26 12:30 AM, Harish Kasiviswanathan wrote:
> For PTE creation use asic specific physical page address mask
>
> Signed-off-by: Harish Kasiviswanathan 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c  | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c  | 4 
>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 1 +
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 1 +
>   9 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 13bec8461cde..631c8a7cc99a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -170,7 +170,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, 
> void *cpu_pt_addr,
>/*
> * The following is for PTE only. GART does not have PDEs.
>*/
> - value = addr & 0xF000ULL;
> + value = addr & adev->gmc.pa_mask;
>value |= flags;
>writeq(value, ptr + (gpu_page_idx * 8));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 676e3aaa1f27..886311fbc2d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -280,6 +280,7 @@ struct amdgpu_gmc {
>u64 real_vram_size;
>int vram_mtrr;
>u64 mc_mask;
> + uint64_tpa_mask;
>const struct firmware   *fw;/* MC firmware */
>uint32_tfw_version;
>struct amdgpu_irq_src   vm_fault;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index f2ccf30da324..1e98a9eb8e11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -843,6 +843,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block 
> *ip_block)
> * internal address space.
> */
>adev->gmc.mc_mask = 0xULL; /* 48 bit MC */
> + adev->gmc.pa_mask = 0xF000ULL; /* 48 bit PA */

This patch uses pa_mask as a value which represents the max PTE width.
It doesn't represent tha actual physical address capability - as in this
case it's only 44-bit. Suggest to change pa_mask to reflect actual
capability or rename the variable.

[HK] : Is pte_pa_mask better?

Thanks,
Lijo

>
>r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
>if (r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 93b1912e28c8..4b93afe7ac8b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -818,6 +818,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block 
> *ip_block)
> * internal address space.
> */
>adev->gmc.mc_mask = 0xULL; /* 48 bit MC */
> + adev->gmc.pa_mask = 0xF000ULL; /* 48 bit PA */
>
>r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
>if (r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> index 8bea8d0d16b4..a921e4c007ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> @@ -813,6 +813,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
> *ip_block)
>   {
>int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
>struct amdgpu_device *adev = ip_block->adev;
> + uint64_t pa_mask = 0;
>int i;
>
>adev->mmhub.funcs->init(adev);
> @@ -842,6 +843,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
> *ip_block)
> * block size 512 (9bit)
> */
>amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
> + pa_mask = 0xF000ULL; /* 48 bit PA */
>break;
>case IP_VERSION(12, 1, 0):
>bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
> @@ -854,6 +856,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
> *ip_block)
> * block size 512 (9bit)
&

Re: [PATCH 1/2] drm/amdgpu: Use asic specific pa mask

2026-05-13 Thread Lazar, Lijo 




On 13-May-26 12:30 AM, Harish Kasiviswanathan wrote:

For PTE creation use asic specific physical page address mask

Signed-off-by: Harish Kasiviswanathan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c  | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c  | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c  | 4 
  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c   | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c   | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c   | 1 +
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   | 1 +
  9 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 13bec8461cde..631c8a7cc99a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -170,7 +170,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void 
*cpu_pt_addr,
/*
 * The following is for PTE only. GART does not have PDEs.
*/
-   value = addr & 0xF000ULL;
+   value = addr & adev->gmc.pa_mask;
value |= flags;
writeq(value, ptr + (gpu_page_idx * 8));
  
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

index 676e3aaa1f27..886311fbc2d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -280,6 +280,7 @@ struct amdgpu_gmc {
u64 real_vram_size;
int vram_mtrr;
u64 mc_mask;
+   uint64_tpa_mask;
const struct firmware   *fw;/* MC firmware */
uint32_tfw_version;
struct amdgpu_irq_src   vm_fault;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f2ccf30da324..1e98a9eb8e11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -843,6 +843,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block 
*ip_block)
 * internal address space.
 */
adev->gmc.mc_mask = 0xULL; /* 48 bit MC */
+   adev->gmc.pa_mask = 0xF000ULL; /* 48 bit PA */


This patch uses pa_mask as a value which represents the max PTE width.
It doesn't represent tha actual physical address capability - as in this 
case it's only 44-bit. Suggest to change pa_mask to reflect actual 
capability or rename the variable.


Thanks,
Lijo

  
  	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));

if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 93b1912e28c8..4b93afe7ac8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -818,6 +818,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block 
*ip_block)
 * internal address space.
 */
adev->gmc.mc_mask = 0xULL; /* 48 bit MC */
+   adev->gmc.pa_mask = 0xF000ULL; /* 48 bit PA */
  
  	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));

if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index 8bea8d0d16b4..a921e4c007ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -813,6 +813,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
  {
int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
struct amdgpu_device *adev = ip_block->adev;
+   uint64_t pa_mask = 0;
int i;
  
  	adev->mmhub.funcs->init(adev);

@@ -842,6 +843,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
 * block size 512 (9bit)
 */
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+   pa_mask = 0xF000ULL; /* 48 bit PA */
break;
case IP_VERSION(12, 1, 0):
bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
@@ -854,6 +856,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
 * block size 512 (9bit)
 */
amdgpu_vm_adjust_size(adev, 128 * 1024 * 1024, 9, 4, 57);
+   pa_mask = 0x000FF000ULL; /* 52 bit PA */
break;
default:
break;
@@ -910,6 +913,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block 
*ip_block)
 * internal address space.
 */
adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK;
+   adev->gmc.pa_mask = pa_mask;
  
  	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));

if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index b39f37597429..675e0fbec8cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@