On Mon, Jul 26, 2010 at 01:13:22PM -0700, Luis R. Rodriguez wrote:
> On Sat, Jun 19, 2010 at 08:32:44AM -0700, Maxim Levitsky wrote:
> > On Sat, 2010-06-19 at 16:02 +0300, Maxim Levitsky wrote:
> > > On Sat, 2010-06-19 at 08:38 -0400, Bob Copeland wrote:
> > > > On Sat, Jun 19, 2010 at 10:49:34AM
On Mon, Jul 26, 2010 at 03:43:04PM -0700, Luis R. Rodriguez wrote:
> I see.. thanks Mathew... in that case since L1 works on all devices we
> could just force enable L1 for all PCIE devices. What do you think?
Works for me.
--
Matthew Garrett | mj...@srcf.ucam.org
__
On Mon, Jul 26, 2010 at 3:33 PM, Matthew Garrett wrote:
> On Mon, Jul 26, 2010 at 03:31:28PM -0700, Luis R. Rodriguez wrote:
>> On Mon, Jul 26, 2010 at 3:29 PM, Matthew Garrett wrote:
>> > On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote:
>> >
>> >> What I meant was that the PCI
On Mon, Jul 26, 2010 at 03:31:28PM -0700, Luis R. Rodriguez wrote:
> On Mon, Jul 26, 2010 at 3:29 PM, Matthew Garrett wrote:
> > On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote:
> >
> >> What I meant was that the PCI config space would already have L1
> >> enabled if L1 worked, s
On Mon, Jul 26, 2010 at 3:29 PM, Matthew Garrett wrote:
> On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote:
>
>> What I meant was that the PCI config space would already have L1
>> enabled if L1 worked, so I don't see why we would need to nitpick out
>> specifics here. All Atheros
On Mon, Jul 26, 2010 at 3:24 PM, Matthew Garrett wrote:
> On Mon, Jul 26, 2010 at 03:20:23PM -0700, Luis R. Rodriguez wrote:
>> On Mon, Jul 26, 2010 at 2:14 PM, Matthew Garrett wrote:
>> > On Mon, Jul 26, 2010 at 02:06:51PM -0700, Luis R. Rodriguez wrote:
>> >
>> >> No, ASPM must be enabled by th
On Mon, Jul 26, 2010 at 03:26:37PM -0700, Luis R. Rodriguez wrote:
> What I meant was that the PCI config space would already have L1
> enabled if L1 worked, so I don't see why we would need to nitpick out
> specifics here. All Atheros PCIE chips should work with L1. The advise
> given is to disab
On Mon, Jul 26, 2010 at 3:21 PM, Matthew Garrett wrote:
> On Mon, Jul 26, 2010 at 03:15:32PM -0700, Luis R. Rodriguez wrote:
>> On Mon, Jul 26, 2010 at 2:25 PM, Matthew Garrett wrote:
>> > This may need to be done on a chip by chip basis. Take a look at
>> > http://www.atheros.cz/inffile.php?inf=
On Mon, Jul 26, 2010 at 03:20:23PM -0700, Luis R. Rodriguez wrote:
> On Mon, Jul 26, 2010 at 2:14 PM, Matthew Garrett wrote:
> > On Mon, Jul 26, 2010 at 02:06:51PM -0700, Luis R. Rodriguez wrote:
> >
> >> No, ASPM must be enabled by the Systems Integrator through the BIOS, there
> >> are
> >> oth
On Mon, Jul 26, 2010 at 2:25 PM, Matthew Garrett wrote:
> On Tue, Jul 27, 2010 at 12:17:13AM +0300, Maxim Levitsky wrote:
>
>> However, it is possible, (and that what I asked you) that some ath5k
>> devices aren't 'pre 1.1 pcie devices' so linux won't disable ASPM L0s
>> for them.
>> So indeed for
On Mon, Jul 26, 2010 at 03:15:32PM -0700, Luis R. Rodriguez wrote:
> On Mon, Jul 26, 2010 at 2:25 PM, Matthew Garrett wrote:
> > This may need to be done on a chip by chip basis. Take a look at
> > http://www.atheros.cz/inffile.php?inf=68&bit=32&atheros=AR5002G&system=4
> > and some of the other i
On Mon, Jul 26, 2010 at 2:14 PM, Matthew Garrett wrote:
> On Mon, Jul 26, 2010 at 02:06:51PM -0700, Luis R. Rodriguez wrote:
>
>> No, ASPM must be enabled by the Systems Integrator through the BIOS, there
>> are
>> other settings that have to be taken care of like modifying some PCI
>> entrance
On Mon, Jul 26, 2010 at 2:17 PM, Maxim Levitsky wrote:
> On Mon, 2010-07-26 at 14:06 -0700, Luis R. Rodriguez wrote:
>> On Mon, Jul 26, 2010 at 01:49:22PM -0700, Maxim Levitsky wrote:
>> > On Mon, 2010-07-26 at 13:13 -0700, Luis R. Rodriguez wrote:
>> > > On Sat, Jun 19, 2010 at 08:32:44AM -0700,
On Mon, Jul 26, 2010 at 02:06:51PM -0700, Luis R. Rodriguez wrote:
> No, ASPM must be enabled by the Systems Integrator through the BIOS, there are
> other settings that have to be taken care of like modifying some PCI entrance
> and
> exit latency timers, the number of FTS packets we send to exi
On Tue, Jul 27, 2010 at 12:17:13AM +0300, Maxim Levitsky wrote:
> However, it is possible, (and that what I asked you) that some ath5k
> devices aren't 'pre 1.1 pcie devices' so linux won't disable ASPM L0s
> for them.
> So indeed for 'good feeling' it is ok to disable L0s from ath5k
> explicitly,
On Mon, 2010-07-26 at 14:06 -0700, Luis R. Rodriguez wrote:
> On Mon, Jul 26, 2010 at 01:49:22PM -0700, Maxim Levitsky wrote:
> > On Mon, 2010-07-26 at 13:13 -0700, Luis R. Rodriguez wrote:
> > > On Sat, Jun 19, 2010 at 08:32:44AM -0700, Maxim Levitsky wrote:
> > > > On Sat, 2010-06-19 at 16:02 +
On Mon, Jul 26, 2010 at 01:49:22PM -0700, Maxim Levitsky wrote:
> On Mon, 2010-07-26 at 13:13 -0700, Luis R. Rodriguez wrote:
> > On Sat, Jun 19, 2010 at 08:32:44AM -0700, Maxim Levitsky wrote:
> > > On Sat, 2010-06-19 at 16:02 +0300, Maxim Levitsky wrote:
> > > > On Sat, 2010-06-19 at 08:38 -040
On Mon, 2010-07-26 at 13:13 -0700, Luis R. Rodriguez wrote:
> On Sat, Jun 19, 2010 at 08:32:44AM -0700, Maxim Levitsky wrote:
> > On Sat, 2010-06-19 at 16:02 +0300, Maxim Levitsky wrote:
> > > On Sat, 2010-06-19 at 08:38 -0400, Bob Copeland wrote:
> > > > On Sat, Jun 19, 2010 at 10:49:34AM +0300
On Sat, Jun 19, 2010 at 08:32:44AM -0700, Maxim Levitsky wrote:
> On Sat, 2010-06-19 at 16:02 +0300, Maxim Levitsky wrote:
> > On Sat, 2010-06-19 at 08:38 -0400, Bob Copeland wrote:
> > > On Sat, Jun 19, 2010 at 10:49:34AM +0300, Maxim Levitsky wrote:
> > > > How this patch?
> > >
> > > Looks fi
On Mon, Jul 26, 2010 at 07:34:04PM +0300, Maxim Levitsky wrote:
> Just want to summarize and finally put that problem to rest.
>
> Was the patch that removes & sets on CONFIG_PCIEASPM? accepted?
>
> Is it possible to check that all ath5k pcie devices that must not use
> L0s actually have the 'PC
On Mon, Jul 26, 2010 at 9:34 AM, Maxim Levitsky wrote:
> Hi,
>
> Just want to summarize and finally put that problem to rest.
>
> Was the patch that removes & sets on CONFIG_PCIEASPM? accepted?
>
> Is it possible to check that all ath5k pcie devices that must not use
> L0s actually have the 'PCI_E
Hi,
Just want to summarize and finally put that problem to rest.
Was the patch that removes & sets on CONFIG_PCIEASPM? accepted?
Is it possible to check that all ath5k pcie devices that must not use
L0s actually have the 'PCI_EXP_DEVCAP_RBER' disabled (this bit causes
pcie device be marked as le
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