RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Yes, thank you, Dan, I realise much more than just the right number of I/O 
pins, Cheers, Neil

 

From: casper@lists.berkeley.edu  On Behalf Of Dan 
Werthimer
Sent: 14 November 2023 22:01
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

thanks for this research on FPGA LVDS pair resources. 

 

as you know, just because an FPGA has 1152 pairs at 1.4 Gb/sec, doesn't mean 
you can input and correlate1152 antennas at 700 MHz bandwidth (real sampling), 

or 576 antennas at 1.4 GHz bandwidth (complex sampling),  as the FPGA fabric to 
cross correlate all those signals goes as the square of the number of antennas,

you'd have to compile the 1 bit correlator and see if it fits...  

best wishes,

 

dan

 

 

 

 

On Tue, Nov 14, 2023 at 1:54 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Hi Dan,

 

Quite right!

Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential I/O 
pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and the 
VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O pairs.

 

Altera (Intel) do the Stratix 10 GX with a maximum of 1152 LVDS pairs running 
at 1.4 Gbps.

 

Thanks, Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 21:30
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

for a single frequency channel correlator (continuum correlator), an XF 
architecture (lag correlator) is the way to go,

the number of antennas in your correlator will likely be limited by the number 
of signals you can get into the FPGA. 

(the correlator will be I/O bound, not compute bound, assuming you have a large 
FPGA). 

 

i haven't looked at the number of LVDS inputs available on a large FPGA 
recently, 

but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
(1024 pins). 

if so, you can have 512 digitizers, which is 256 complex digitizers, which is 
128 antennas dual pol, or 256 antenna single pol. 

 

as david hawkins suggested, could also use the high speed serdes on the FPGA. 

the new pricy FPGAs have serdes that can work at >100 Gbps. 

and the larger pricy FPGAs have 32 of these serdes, which means you can send 
3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at 
1Gcomplexsamples/sec, or 800 antennas dual pol. 

but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 
100Gbit/sec signal - 

the easiest way to convert 100 signals into a single 100Gsps signal would be to 
use an FPGA, 

and that would defeat your goal of using a single FPGA for your correlator.

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 12:43 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA with a lot of pins 
you can get about 512 ADC's 

(256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer 
and your correlator...

 

if you only need a small number of spectral channels, you could build an XF 
correlator

with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol) in 
a large FPGA.   

 

with an XF architecture, the FPGA utilization is  J  x  
number_of_sp

Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

thanks for this research on FPGA LVDS pair resources.

as you know, just because an FPGA has 1152 pairs at 1.4 Gb/sec, doesn't
mean you can input and correlate1152 antennas at 700 MHz bandwidth (real
sampling),
or 576 antennas at 1.4 GHz bandwidth (complex sampling),  as the FPGA
fabric to cross correlate all those signals goes as the square of the
number of antennas,
you'd have to compile the 1 bit correlator and see if it fits...

best wishes,

dan




On Tue, Nov 14, 2023 at 1:54 PM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Hi Dan,
>
>
>
> Quite right!
>
> Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential
> I/O pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and
> the VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O
> pairs.
>
>
>
> Altera (Intel) do the Stratix 10 GX with a maximum of 1152 LVDS pairs
> running at 1.4 Gbps.
>
>
>
> Thanks, Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 21:30
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> for a single frequency channel correlator (continuum correlator), an XF
> architecture (lag correlator) is the way to go,
>
> the number of antennas in your correlator will likely be limited by the
> number of signals you can get into the FPGA.
>
> (the correlator will be I/O bound, not compute bound, assuming you have a
> large FPGA).
>
>
>
> i haven't looked at the number of LVDS inputs available on a large FPGA
> recently,
>
> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS
> pairs (1024 pins).
>
> if so, you can have 512 digitizers, which is 256 complex digitizers, which
> is 128 antennas dual pol, or 256 antenna single pol.
>
>
>
> as david hawkins suggested, could also use the high speed serdes on the
> FPGA.
>
> the new pricy FPGAs have serdes that can work at >100 Gbps.
>
> and the larger pricy FPGAs have 32 of these serdes, which means you can
> send 3.2 Tbits/sec into those FGPAs.
>
> that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at
> 1Gcomplexsamples/sec, or 800 antennas dual pol.
>
> but it would take a lot of electronics to convert 100 1Gbit/sec signals
> into a 100Gbit/sec signal -
>
> the easiest way to convert 100 signals into a single 100Gsps signal would
> be to use an FPGA,
>
> and that would defeat your goal of using a single FPGA for your correlator.
>
>
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> On Sat, Nov 11, 2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> Thanks Dan,
>
>
>
> Yes, one antenna for one receiver, and there is only one frequency
> channel, and a single polarisation, so quite a simple configuration.
>
>
>
> A good idea to use differential inputs as single bit ADCs.
>
>
>
> So the FX correlator looks the better architecture.
>
>
>
> So are you saying the FPGA FX correlator would manage making the
> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
> FPGA, Xilinx or Altera ?
>
>
>
> Cheers,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 20:23
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> by number of receiver channels, i presume you mean number of antennas?
>
> are these single or dual polarization?
>
>
>
> how many spectral channels do you need in your correlator ?
>
>
>
> for a large number of spectral channels,
>
> you'll likely want to use an FX architecture correlator (not XF).
>
> in an FX correlator the number of ADC bits doesn't change the FPGA
> utilization for the DSP very much.
>
>
>
> one fun thing you can do with a 1 bit correlator, is use the LVDS
> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
> with a lot of pins you can get about 512 ADC's
>
> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
> digitizer and your correlator...
>
>
>
> if you only need a small number of spectral channels, you could build an
> XF correlator
>
> with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single
> pol) in a large FPGA.
>
>
>
> with an XF architecture, the FPGA utilization is  J  x
> num

RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Hi Dan,

 

Quite right!

Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential I/O 
pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and the 
VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O pairs.

 

Altera (Intel) do the Stratix 10 GX with a maximum of 1152 LVDS pairs running 
at 1.4 Gbps.

 

Thanks, Neil

 

From: casper@lists.berkeley.edu  On Behalf Of Dan 
Werthimer
Sent: 11 November 2023 21:30
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

for a single frequency channel correlator (continuum correlator), an XF 
architecture (lag correlator) is the way to go,

the number of antennas in your correlator will likely be limited by the number 
of signals you can get into the FPGA. 

(the correlator will be I/O bound, not compute bound, assuming you have a large 
FPGA). 

 

i haven't looked at the number of LVDS inputs available on a large FPGA 
recently, 

but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
(1024 pins). 

if so, you can have 512 digitizers, which is 256 complex digitizers, which is 
128 antennas dual pol, or 256 antenna single pol. 

 

as david hawkins suggested, could also use the high speed serdes on the FPGA. 

the new pricy FPGAs have serdes that can work at >100 Gbps. 

and the larger pricy FPGAs have 32 of these serdes, which means you can send 
3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at 
1Gcomplexsamples/sec, or 800 antennas dual pol. 

but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 
100Gbit/sec signal - 

the easiest way to convert 100 signals into a single 100Gsps signal would be to 
use an FPGA, 

and that would defeat your goal of using a single FPGA for your correlator.

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 12:43 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA with a lot of pins 
you can get about 512 ADC's 

(256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer 
and your correlator...

 

if you only need a small number of spectral channels, you could build an XF 
correlator

with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol) in 
a large FPGA.   

 

with an XF architecture, the FPGA utilization is  J  x  
number_of_spectral_channels. 

for FX, the utilization goes as K  x  log_base_2(spectral_channels). 

 

but constant K >> constant J,  

so sometimes (rarely) it is better to use XF, depending on the number of 
spectral channels. 

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 11:47 AM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

 

Many thanks,

Neil Salmon 

-- 
You received this message because you are subscribed to the Google Groups 
&q

Re: [casper] state of the art single bit correlators

[Karl Warnick]

Kristian,

This piqued my interest as I've been talking with a research group that 
wants to do exactly this for fast optical fiber detonation cameras. Do 
you have any direct experience with using switch optical transceivers 
connected to fiber lines for sensing, or has anyone already done this?


Best,
Karl

On 11/13/2023 7:21 AM, Kristian Zarb Adami wrote:
I would imagine if you wanted to go to crazy bandwidths you could even 
use optical transceivers on switches as single bit digitisers...


On Mon, 13 Nov 2023, 14:56 Dan Werthimer,  wrote:


hi neil,

paul horowitz, at harvard, had a PhD student who characterized and
used FPGA LVDS inputs as ADC's for a seti experiment.
that thesis is available, and i think there is a publication as
well - paul will know.

best wishes,

dan



On Mon, Nov 13, 2023 at 12:48 AM salmon.na <http://salmon.na> via
casper@lists.berkeley.edu  wrote:

Hi Dan,

Just one further question, in terms of building a single bit
cross-correlator on an FPGA, exploiting differential LVDS pair
for single bit digitisation, might there be a suitable
reference for this that I can include in the paper and an IEEE
transaction journal?

Many thanks,

Neil

*From:*casper@lists.berkeley.edu 
*On Behalf Of *Dan Werthimer
*Sent:* 11 November 2023 21:52
*To:* casper@lists.berkeley.edu
*Subject:* Re: [casper] state of the art single bit correlators

hi neil,

i don't think waiting 5 years will help:

there will be faster serdes - the current chips handle ~5
Tbit/sec and that will probably double every two years,

but that won't help you because you need other fpga's to
convert your slow 1 gsps data rate to 100, 200, 400, or 800
Gbit/sec serial.

and the fpga's will have more computing capability.

but i don't think there will be more than 512 LVDS (low speed
1 Gsps) inputs, as there's no market demand for that anymore.

there are chips with much higher pin counts (CPUs have 4700
pins), and would be easy for AMD or Intel to make an FPGA with
more LVDS inputs,

but there's no market.

best wishes,

dan

Dan Werthimer

Astronomy Dept and Space Sciences Lab

University of California, Berkeley

On Sat, Nov 11, 2023 at 1:39 PM salmon.na <http://salmon.na>
via casper@lists.berkeley.edu  wrote:

Hi Dan,

Those are attractive looking numbers.

Is it possible to say how that might scale over the next
5-years, will the number of pins go up, faster than the
processing speed, or the number of gate on board? Is it
likely to remain I/O bound of compute bound?

Many thanks,

Neil

*From:*casper@lists.berkeley.edu
 *On Behalf Of *Dan Werthimer
*Sent:* 11 November 2023 21:30
*To:* casper@lists.berkeley.edu
        *Subject:* Re: [casper] state of the art single bit
correlators

hi neil,

for a single frequency channel correlator (continuum
correlator), an XF architecture (lag correlator) is the
way to go,

the number of antennas in your correlator will likely be
limited by the number of signals you can get into the FPGA.

(the correlator will be I/O bound, not compute bound,
assuming you have a large FPGA).

i haven't looked at the number of LVDS inputs available on
a large FPGA recently,

but i think for a ~1800 pin package,  there might be up to
~~512 LVDS pairs (1024 pins).

if so, you can have 512 digitizers, which is 256 complex
digitizers, which is 128 antennas dual pol, or 256 antenna
single pol.

as david hawkins suggested, could also use the high speed
serdes on the FPGA.

the new pricy FPGAs have serdes that can work at >100 Gbps.

and the larger pricy FPGAs have 32 of these serdes, which
means you can send 3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600
complex streams at 1Gcomplexsamples/sec, or 800 antennas
dual pol.

but it would take a lot of electronics to convert 100
1Gbit/sec signals into a 100Gbit/sec signal -

the easiest way to convert 100 signals into a single
100Gsps signal would be to use an FPGA,

and that would defeat your goal of using a single FPGA for
your correlator.

best wishes,

dan

On Sat, Nov 11, 2023 at 12:43 PM salmon.na
&l

RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Certainly a great read, many thanks!

 

From: 'Jonathan Weintroub' via casper@lists.berkeley.edu 
 
Sent: 13 November 2023 13:59
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

Hi Neil, Dan,

 

That would be the thesis of the brilliant Curtis Mead, downloadable here:

 

https://dash.harvard.edu/handle/1/11158246

 

Jono

 





On Nov 13, 2023, at 8:56 AM, Dan Werthimer mailto:d...@ssl.berkeley.edu> > wrote:

 

 

hi neil, 

 

paul horowitz, at harvard, had a PhD student who characterized and used FPGA 
LVDS inputs as ADC's for a seti experiment.  

that thesis is available, and i think there is a publication as well - paul 
will know. 

 

best wishes,

 

dan

 

 

 

On Mon, Nov 13, 2023 at 12:48 AM salmon.na 
<https://www.google.com/url?q=http://salmon.na&source=gmail-imap&ust=170048859500&usg=AOvVaw1KVjqBORslLsCVV9Y4ma5L>
  via casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Hi Dan, 

 

Just one further question, in terms of building a single bit cross-correlator 
on an FPGA, exploiting differential LVDS pair for single bit digitisation, 
might there be a suitable reference for this that I can include in the paper 
and an IEEE transaction journal?

 

Many thanks,

Neil  

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 21:52
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

i don't think waiting 5 years will help: 

there will be faster serdes - the current chips handle ~5 Tbit/sec and that 
will probably double every two years, 

but that won't help you because you need other fpga's to convert your slow 1 
gsps data rate to 100, 200, 400, or 800 Gbit/sec serial. 

and the fpga's will have more computing capability. 

but i don't think there will be more than 512 LVDS (low speed 1 Gsps) inputs, 
as there's no market demand for that anymore. 

there are chips with much higher pin counts (CPUs have 4700 pins), and would be 
easy for AMD or Intel to make an FPGA with more LVDS inputs, 

but there's no market.  

 

best wishes,

 

dan

 

 

 

Dan Werthimer

Astronomy Dept and Space Sciences Lab

University of California, Berkeley

 

 

On Sat, Nov 11, 2023 at 1:39 PM salmon.na 
<https://www.google.com/url?q=http://salmon.na&source=gmail-imap&ust=170048859500&usg=AOvVaw1KVjqBORslLsCVV9Y4ma5L>
  via casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Hi Dan, 

 

Those are attractive looking numbers. 

 

Is it possible to say how that might scale over the next 5-years, will the 
number of pins go up, faster than the processing speed, or the number of gate 
on board? Is it likely to remain I/O bound of compute bound?

 

Many thanks,

Neil 

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 21:30
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

for a single frequency channel correlator (continuum correlator), an XF 
architecture (lag correlator) is the way to go,

the number of antennas in your correlator will likely be limited by the number 
of signals you can get into the FPGA. 

(the correlator will be I/O bound, not compute bound, assuming you have a large 
FPGA). 

 

i haven't looked at the number of LVDS inputs available on a large FPGA 
recently, 

but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
(1024 pins). 

if so, you can have 512 digitizers, which is 256 complex digitizers, which is 
128 antennas dual pol, or 256 antenna single pol. 

 

as david hawkins suggested, could also use the high speed serdes on the FPGA. 

the new pricy FPGAs have serdes that can work at >100 Gbps. 

and the larger pricy FPGAs have 32 of these serdes, which means you can send 
3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at 
1Gcomplexsamples/sec, or 800 antennas dual pol. 

but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 
100Gbit/sec signal - 

the easiest way to convert 100 signals into a single 100Gsps signal would be to 
use an FPGA, 

and that would defeat your goal of using a single FPGA for your correlator.

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 12:43 PM salmon.na 
<https://www.google.com/url?q=http://salmon.na&source=gmail-imap&ust=170048859500&usg=AOvVaw1KVjqBORslLsCVV9Y4ma5L>
  via casper@lists.b

Re: [casper] state of the art single bit correlators

[Kristian Zarb Adami]

I would imagine if you wanted to go to crazy bandwidths you could even use
optical transceivers on switches as single bit digitisers...

On Mon, 13 Nov 2023, 14:56 Dan Werthimer,  wrote:

>
> hi neil,
>
> paul horowitz, at harvard, had a PhD student who characterized and used
> FPGA LVDS inputs as ADC's for a seti experiment.
> that thesis is available, and i think there is a publication as well -
> paul will know.
>
> best wishes,
>
> dan
>
>
>
> On Mon, Nov 13, 2023 at 12:48 AM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
>> Hi Dan,
>>
>>
>>
>> Just one further question, in terms of building a single bit
>> cross-correlator on an FPGA, exploiting differential LVDS pair for single
>> bit digitisation, might there be a suitable reference for this that I can
>> include in the paper and an IEEE transaction journal?
>>
>>
>>
>> Many thanks,
>>
>> Neil
>>
>>
>>
>> *From:* casper@lists.berkeley.edu  *On Behalf
>> Of *Dan Werthimer
>> *Sent:* 11 November 2023 21:52
>> *To:* casper@lists.berkeley.edu
>> *Subject:* Re: [casper] state of the art single bit correlators
>>
>>
>>
>>
>>
>> hi neil,
>>
>>
>>
>> i don't think waiting 5 years will help:
>>
>> there will be faster serdes - the current chips handle ~5 Tbit/sec and
>> that will probably double every two years,
>>
>> but that won't help you because you need other fpga's to convert your
>> slow 1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.
>>
>> and the fpga's will have more computing capability.
>>
>> but i don't think there will be more than 512 LVDS (low speed 1 Gsps)
>> inputs, as there's no market demand for that anymore.
>>
>> there are chips with much higher pin counts (CPUs have 4700 pins), and
>> would be easy for AMD or Intel to make an FPGA with more LVDS inputs,
>>
>> but there's no market.
>>
>>
>>
>> best wishes,
>>
>>
>>
>> dan
>>
>>
>>
>>
>>
>>
>>
>> Dan Werthimer
>>
>> Astronomy Dept and Space Sciences Lab
>>
>> University of California, Berkeley
>>
>>
>>
>>
>>
>> On Sat, Nov 11, 2023 at 1:39 PM salmon.na via casper@lists.berkeley.edu <
>> casper@lists.berkeley.edu> wrote:
>>
>> Hi Dan,
>>
>>
>>
>> Those are attractive looking numbers.
>>
>>
>>
>> Is it possible to say how that might scale over the next 5-years, will
>> the number of pins go up, faster than the processing speed, or the number
>> of gate on board? Is it likely to remain I/O bound of compute bound?
>>
>>
>>
>> Many thanks,
>>
>> Neil
>>
>>
>>
>> *From:* casper@lists.berkeley.edu  *On Behalf
>> Of *Dan Werthimer
>> *Sent:* 11 November 2023 21:30
>> *To:* casper@lists.berkeley.edu
>> *Subject:* Re: [casper] state of the art single bit correlators
>>
>>
>>
>>
>>
>> hi neil,
>>
>>
>>
>> for a single frequency channel correlator (continuum correlator), an XF
>> architecture (lag correlator) is the way to go,
>>
>> the number of antennas in your correlator will likely be limited by the
>> number of signals you can get into the FPGA.
>>
>> (the correlator will be I/O bound, not compute bound, assuming you have a
>> large FPGA).
>>
>>
>>
>> i haven't looked at the number of LVDS inputs available on a large FPGA
>> recently,
>>
>> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS
>> pairs (1024 pins).
>>
>> if so, you can have 512 digitizers, which is 256 complex digitizers,
>> which is 128 antennas dual pol, or 256 antenna single pol.
>>
>>
>>
>> as david hawkins suggested, could also use the high speed serdes on the
>> FPGA.
>>
>> the new pricy FPGAs have serdes that can work at >100 Gbps.
>>
>> and the larger pricy FPGAs have 32 of these serdes, which means you can
>> send 3.2 Tbits/sec into those FGPAs.
>>
>> that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams
>> at 1Gcomplexsamples/sec, or 800 antennas dual pol.
>>
>> but it would take a lot of electronics to convert 100 1Gbit/sec signals
>> into a 100Gbit/sec signal -
>>
>> the easiest way to convert 100 signals into a single 100Gsps signal would
>> be to use a

Re: [casper] state of the art single bit correlators

['Jonathan Weintroub' via casper@lists.berkeley.edu]

Hi Neil, Dan,

That would be the thesis of the brilliant Curtis Mead, downloadable here:

https://dash.harvard.edu/handle/1/11158246

Jono


> On Nov 13, 2023, at 8:56 AM, Dan Werthimer  wrote:
> 
> 
> hi neil, 
> 
> paul horowitz, at harvard, had a PhD student who characterized and used FPGA 
> LVDS inputs as ADC's for a seti experiment.  
> that thesis is available, and i think there is a publication as well - paul 
> will know. 
> 
> best wishes,
> 
> dan
> 
> 
> 
> On Mon, Nov 13, 2023 at 12:48 AM salmon.na 
> <https://www.google.com/url?q=http://salmon.na&source=gmail-imap&ust=170048859500&usg=AOvVaw1KVjqBORslLsCVV9Y4ma5L>
>  via casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
> mailto:casper@lists.berkeley.edu>> wrote:
>> Hi Dan,
>> 
>>  
>> 
>> Just one further question, in terms of building a single bit 
>> cross-correlator on an FPGA, exploiting differential LVDS pair for single 
>> bit digitisation, might there be a suitable reference for this that I can 
>> include in the paper and an IEEE transaction journal?
>> 
>>  
>> 
>> Many thanks,
>> 
>> Neil  
>> 
>>  
>> 
>> From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
>> mailto:casper@lists.berkeley.edu>> On Behalf Of 
>> Dan Werthimer
>> Sent: 11 November 2023 21:52
>> To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>
>> Subject: Re: [casper] state of the art single bit correlators
>> 
>>  
>> 
>>  
>> 
>> hi neil, 
>> 
>>  
>> 
>> i don't think waiting 5 years will help: 
>> 
>> there will be faster serdes - the current chips handle ~5 Tbit/sec and that 
>> will probably double every two years, 
>> 
>> but that won't help you because you need other fpga's to convert your slow 1 
>> gsps data rate to 100, 200, 400, or 800 Gbit/sec serial. 
>> 
>> and the fpga's will have more computing capability. 
>> 
>> but i don't think there will be more than 512 LVDS (low speed 1 Gsps) 
>> inputs, as there's no market demand for that anymore. 
>> 
>> there are chips with much higher pin counts (CPUs have 4700 pins), and would 
>> be easy for AMD or Intel to make an FPGA with more LVDS inputs, 
>> 
>> but there's no market.  
>> 
>>  
>> 
>> best wishes,
>> 
>>  
>> 
>> dan
>> 
>>  
>> 
>>  
>> 
>>  
>> 
>> Dan Werthimer
>> 
>> Astronomy Dept and Space Sciences Lab
>> 
>> University of California, Berkeley
>> 
>>  
>> 
>>  
>> 
>> On Sat, Nov 11, 2023 at 1:39 PM salmon.na 
>> <https://www.google.com/url?q=http://salmon.na&source=gmail-imap&ust=170048859500&usg=AOvVaw1KVjqBORslLsCVV9Y4ma5L>
>>  via casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
>> mailto:casper@lists.berkeley.edu>> wrote:
>> 
>> Hi Dan,
>> 
>>  
>> 
>> Those are attractive looking numbers.
>> 
>>  
>> 
>> Is it possible to say how that might scale over the next 5-years, will the 
>> number of pins go up, faster than the processing speed, or the number of 
>> gate on board? Is it likely to remain I/O bound of compute bound?
>> 
>>  
>> 
>> Many thanks,
>> 
>> Neil
>> 
>>  
>> 
>> From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
>> mailto:casper@lists.berkeley.edu>> On Behalf Of 
>> Dan Werthimer
>> Sent: 11 November 2023 21:30
>> To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>
>> Subject: Re: [casper] state of the art single bit correlators
>> 
>>  
>> 
>>  
>> 
>> hi neil, 
>> 
>>  
>> 
>> for a single frequency channel correlator (continuum correlator), an XF 
>> architecture (lag correlator) is the way to go,
>> 
>> the number of antennas in your correlator will likely be limited by the 
>> number of signals you can get into the FPGA. 
>> 
>> (the correlator will be I/O bound, not compute bound, assuming you have a 
>> large FPGA). 
>> 
>>  
>> 
>> i haven't looked at the number of LVDS inputs available on a large FPGA 
>> recently, 
>> 
>> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
>> (1024 pins). 
>> 
>> if so, you can have 512 digitizers, which is 256 complex digitizers, 

Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

paul horowitz, at harvard, had a PhD student who characterized and used
FPGA LVDS inputs as ADC's for a seti experiment.
that thesis is available, and i think there is a publication as well - paul
will know.

best wishes,

dan



On Mon, Nov 13, 2023 at 12:48 AM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Hi Dan,
>
>
>
> Just one further question, in terms of building a single bit
> cross-correlator on an FPGA, exploiting differential LVDS pair for single
> bit digitisation, might there be a suitable reference for this that I can
> include in the paper and an IEEE transaction journal?
>
>
>
> Many thanks,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 21:52
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> i don't think waiting 5 years will help:
>
> there will be faster serdes - the current chips handle ~5 Tbit/sec and
> that will probably double every two years,
>
> but that won't help you because you need other fpga's to convert your slow
> 1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.
>
> and the fpga's will have more computing capability.
>
> but i don't think there will be more than 512 LVDS (low speed 1 Gsps)
> inputs, as there's no market demand for that anymore.
>
> there are chips with much higher pin counts (CPUs have 4700 pins), and
> would be easy for AMD or Intel to make an FPGA with more LVDS inputs,
>
> but there's no market.
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> Dan Werthimer
>
> Astronomy Dept and Space Sciences Lab
>
> University of California, Berkeley
>
>
>
>
>
> On Sat, Nov 11, 2023 at 1:39 PM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> Hi Dan,
>
>
>
> Those are attractive looking numbers.
>
>
>
> Is it possible to say how that might scale over the next 5-years, will the
> number of pins go up, faster than the processing speed, or the number of
> gate on board? Is it likely to remain I/O bound of compute bound?
>
>
>
> Many thanks,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 21:30
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> for a single frequency channel correlator (continuum correlator), an XF
> architecture (lag correlator) is the way to go,
>
> the number of antennas in your correlator will likely be limited by the
> number of signals you can get into the FPGA.
>
> (the correlator will be I/O bound, not compute bound, assuming you have a
> large FPGA).
>
>
>
> i haven't looked at the number of LVDS inputs available on a large FPGA
> recently,
>
> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS
> pairs (1024 pins).
>
> if so, you can have 512 digitizers, which is 256 complex digitizers, which
> is 128 antennas dual pol, or 256 antenna single pol.
>
>
>
> as david hawkins suggested, could also use the high speed serdes on the
> FPGA.
>
> the new pricy FPGAs have serdes that can work at >100 Gbps.
>
> and the larger pricy FPGAs have 32 of these serdes, which means you can
> send 3.2 Tbits/sec into those FGPAs.
>
> that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at
> 1Gcomplexsamples/sec, or 800 antennas dual pol.
>
> but it would take a lot of electronics to convert 100 1Gbit/sec signals
> into a 100Gbit/sec signal -
>
> the easiest way to convert 100 signals into a single 100Gsps signal would
> be to use an FPGA,
>
> and that would defeat your goal of using a single FPGA for your correlator.
>
>
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> On Sat, Nov 11, 2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> Thanks Dan,
>
>
>
> Yes, one antenna for one receiver, and there is only one frequency
> channel, and a single polarisation, so quite a simple configuration.
>
>
>
> A good idea to use differential inputs as single bit ADCs.
>
>
>
> So the FX correlator looks the better architecture.
>
>
>
> So are you saying the FPGA FX correlator would manage making the
> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
> FPGA, Xilinx or Altera ?
>
>
>

RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Hi Dan, 

 

Just one further question, in terms of building a single bit cross-correlator 
on an FPGA, exploiting differential LVDS pair for single bit digitisation, 
might there be a suitable reference for this that I can include in the paper 
and an IEEE transaction journal?

 

Many thanks,

Neil  

 

From: casper@lists.berkeley.edu  On Behalf Of Dan 
Werthimer
Sent: 11 November 2023 21:52
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

i don't think waiting 5 years will help: 

there will be faster serdes - the current chips handle ~5 Tbit/sec and that 
will probably double every two years, 

but that won't help you because you need other fpga's to convert your slow 1 
gsps data rate to 100, 200, 400, or 800 Gbit/sec serial. 

and the fpga's will have more computing capability. 

but i don't think there will be more than 512 LVDS (low speed 1 Gsps) inputs, 
as there's no market demand for that anymore. 

there are chips with much higher pin counts (CPUs have 4700 pins), and would be 
easy for AMD or Intel to make an FPGA with more LVDS inputs, 

but there's no market.  

 

best wishes,

 

dan

 

 

 

Dan Werthimer

Astronomy Dept and Space Sciences Lab

University of California, Berkeley

 

 

On Sat, Nov 11, 2023 at 1:39 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Hi Dan, 

 

Those are attractive looking numbers. 

 

Is it possible to say how that might scale over the next 5-years, will the 
number of pins go up, faster than the processing speed, or the number of gate 
on board? Is it likely to remain I/O bound of compute bound?

 

Many thanks,

Neil 

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 21:30
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

for a single frequency channel correlator (continuum correlator), an XF 
architecture (lag correlator) is the way to go,

the number of antennas in your correlator will likely be limited by the number 
of signals you can get into the FPGA. 

(the correlator will be I/O bound, not compute bound, assuming you have a large 
FPGA). 

 

i haven't looked at the number of LVDS inputs available on a large FPGA 
recently, 

but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
(1024 pins). 

if so, you can have 512 digitizers, which is 256 complex digitizers, which is 
128 antennas dual pol, or 256 antenna single pol. 

 

as david hawkins suggested, could also use the high speed serdes on the FPGA. 

the new pricy FPGAs have serdes that can work at >100 Gbps. 

and the larger pricy FPGAs have 32 of these serdes, which means you can send 
3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at 
1Gcomplexsamples/sec, or 800 antennas dual pol. 

but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 
100Gbit/sec signal - 

the easiest way to convert 100 signals into a single 100Gsps signal would be to 
use an FPGA, 

and that would defeat your goal of using a single FPGA for your correlator.

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 12:43 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps

Re: [casper] state of the art single bit correlators

['salmon.na' via casper@lists.berkeley.edu]

Hi Dan, that's great information - very helpful.many thanks, best wishes 
NeilSent from my Galaxy
 Original message From: Dan Werthimer  
Date: 11/11/2023  21:51  (GMT+00:00) To: casper@lists.berkeley.edu Subject: Re: 
[casper] state of the art single bit correlators hi neil, i don't think waiting 
5 years will help: there will be faster serdes - the current chips handle ~5 
Tbit/sec and that will probably double every two years, but that won't help you 
because you need other fpga's to convert your slow 1 gsps data rate to 100, 
200, 400, or 800 Gbit/sec serial. and the fpga's will have more computing 
capability. but i don't think there will be more than 512 LVDS (low speed 1 
Gsps) inputs, as there's no market demand for that anymore. there are chips 
with much higher pin counts (CPUs have 4700 pins), and would be easy for AMD or 
Intel to make an FPGA with more LVDS inputs, but there's no market.  best 
wishes,danDan WerthimerAstronomy Dept and Space Sciences LabUniversity of 
California, BerkeleyOn Sat, Nov 11, 2023 at 1:39 PM salmon.na via 
casper@lists.berkeley.edu  wrote:Hi Dan,  Those are 
attractive looking numbers.  Is it possible to say how that might scale over 
the next 5-years, will the number of pins go up, faster than the processing 
speed, or the number of gate on board? Is it likely to remain I/O bound of 
compute bound? Many thanks,Neil  From: casper@lists.berkeley.edu 
 On Behalf Of Dan WerthimerSent: 11 November 2023 
21:30To: casper@lists.berkeley.eduSubject: Re: [casper] state of the art single 
bit correlators  hi neil,  for a single frequency channel correlator (continuum 
correlator), an XF architecture (lag correlator) is the way to go,the number of 
antennas in your correlator will likely be limited by the number of signals you 
can get into the FPGA. (the correlator will be I/O bound, not compute bound, 
assuming you have a large FPGA).  i haven't looked at the number of LVDS inputs 
available on a large FPGA recently, but i think for a ~1800 pin package,  there 
might be up to ~~512 LVDS pairs (1024 pins). if so, you can have 512 
digitizers, which is 256 complex digitizers, which is 128 antennas dual pol, or 
256 antenna single pol.  as david hawkins suggested, could also use the high 
speed serdes on the FPGA. the new pricy FPGAs have serdes that can work at >100 
Gbps. and the larger pricy FPGAs have 32 of these serdes, which means you can 
send 3.2 Tbits/sec into those FGPAs.that data rate is 3200 real 1Gsps bit 
streams,  or 1600 complex streams at 1Gcomplexsamples/sec, or 800 antennas dual 
pol. but it would take a lot of electronics to convert 100 1Gbit/sec signals 
into a 100Gbit/sec signal - the easiest way to convert 100 signals into a 
single 100Gsps signal would be to use an FPGA, and that would defeat your goal 
of using a single FPGA for your correlator.  best wishes, dan   On Sat, Nov 11, 
2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu 
 wrote:Thanks Dan, Yes, one antenna for one 
receiver, and there is only one frequency channel, and a single polarisation, 
so quite a simple configuration. A good idea to use differential inputs as 
single bit ADCs.  So the FX correlator looks the better architecture.  So are 
you saying the FPGA FX correlator would manage making the cross-correlations of 
512 single bit channels at 1 GbpS, on say a single FPGA, Xilinx or Altera ? 
Cheers,Neil From: casper@lists.berkeley.edu  On 
Behalf Of Dan WerthimerSent: 11 November 2023 20:23To: 
casper@lists.berkeley.eduSubject: Re: [casper] state of the art single bit 
correlators  hi neil,  by number of receiver channels, i presume you mean 
number of antennas? are these single or dual polarization?  how many spectral 
channels do you need in your correlator ?    for a large number of spectral 
channels, you'll likely want to use an FX architecture correlator (not XF).in 
an FX correlator the number of ADC bits doesn't change the FPGA utilization for 
the DSP very much.  one fun thing you can do with a 1 bit correlator, is use 
the LVDS differential inputs on the FPGA as 1 Gsps digitizers.   on a large 
FPGA with a lot of pins you can get about 512 ADC's (256 antennas, dual pol) 
built into the FPGA, so the FPGA can be your digitizer and your correlator... 
if you only need a small number of spectral channels, you could build an XF 
correlatorwith ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas 
single pol) in a large FPGA.    with an XF architecture, the FPGA utilization 
is  J  x  number_of_spectral_channels. for FX, the utilization goes as K  x  
log_base_2(spectral_channels).  but constant K >> constant J,  so sometimes 
(rarely) it is better to use XF, depending on the number of spectral channels.  
 best wishes, dan   On Sat, Nov 11, 2023 at 11:47 AM salmon.na via 
casper@lists.berkeley.edu  wrote:For a paper on 
non-radioastronomy aperture synthesis technology I need to kno

Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

i don't think waiting 5 years will help:
there will be faster serdes - the current chips handle ~5 Tbit/sec and that
will probably double every two years,
but that won't help you because you need other fpga's to convert your slow
1 gsps data rate to 100, 200, 400, or 800 Gbit/sec serial.
and the fpga's will have more computing capability.
but i don't think there will be more than 512 LVDS (low speed 1 Gsps)
inputs, as there's no market demand for that anymore.
there are chips with much higher pin counts (CPUs have 4700 pins), and
would be easy for AMD or Intel to make an FPGA with more LVDS inputs,
but there's no market.

best wishes,

dan



Dan Werthimer
Astronomy Dept and Space Sciences Lab
University of California, Berkeley


On Sat, Nov 11, 2023 at 1:39 PM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Hi Dan,
>
>
>
> Those are attractive looking numbers.
>
>
>
> Is it possible to say how that might scale over the next 5-years, will the
> number of pins go up, faster than the processing speed, or the number of
> gate on board? Is it likely to remain I/O bound of compute bound?
>
>
>
> Many thanks,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 21:30
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> for a single frequency channel correlator (continuum correlator), an XF
> architecture (lag correlator) is the way to go,
>
> the number of antennas in your correlator will likely be limited by the
> number of signals you can get into the FPGA.
>
> (the correlator will be I/O bound, not compute bound, assuming you have a
> large FPGA).
>
>
>
> i haven't looked at the number of LVDS inputs available on a large FPGA
> recently,
>
> but i think for a ~1800 pin package,  there might be up to ~~512 LVDS
> pairs (1024 pins).
>
> if so, you can have 512 digitizers, which is 256 complex digitizers, which
> is 128 antennas dual pol, or 256 antenna single pol.
>
>
>
> as david hawkins suggested, could also use the high speed serdes on the
> FPGA.
>
> the new pricy FPGAs have serdes that can work at >100 Gbps.
>
> and the larger pricy FPGAs have 32 of these serdes, which means you can
> send 3.2 Tbits/sec into those FGPAs.
>
> that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at
> 1Gcomplexsamples/sec, or 800 antennas dual pol.
>
> but it would take a lot of electronics to convert 100 1Gbit/sec signals
> into a 100Gbit/sec signal -
>
> the easiest way to convert 100 signals into a single 100Gsps signal would
> be to use an FPGA,
>
> and that would defeat your goal of using a single FPGA for your correlator.
>
>
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> On Sat, Nov 11, 2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> Thanks Dan,
>
>
>
> Yes, one antenna for one receiver, and there is only one frequency
> channel, and a single polarisation, so quite a simple configuration.
>
>
>
> A good idea to use differential inputs as single bit ADCs.
>
>
>
> So the FX correlator looks the better architecture.
>
>
>
> So are you saying the FPGA FX correlator would manage making the
> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
> FPGA, Xilinx or Altera ?
>
>
>
> Cheers,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 20:23
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> by number of receiver channels, i presume you mean number of antennas?
>
> are these single or dual polarization?
>
>
>
> how many spectral channels do you need in your correlator ?
>
>
>
> for a large number of spectral channels,
>
> you'll likely want to use an FX architecture correlator (not XF).
>
> in an FX correlator the number of ADC bits doesn't change the FPGA
> utilization for the DSP very much.
>
>
>
> one fun thing you can do with a 1 bit correlator, is use the LVDS
> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
> with a lot of pins you can get about 512 ADC's
>
> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
> digitizer and your correlator...
>
>
>
> if you only need a small number of spectral channels, you c

Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

regarding how big an FPGA you need:

let's assume 512 complex signals at 1 Gbit/sec real, 1 Gbit/sec imag:

you'll need ~512^2 / 2 = 2^17 complex multipliers, which can be made from
2^18  four bit look up tables, assuming a 500 MHz FPGA clock.
for the accumulators, you need 2^18 adders, 2^18 counters, and you'll also
need 2^18 registers (for readout), assuming a 500 MHz clock.
i think that will all fit into a giant FPGA, but it will be tight.  i
suggest you compile it and see.

best wishes,

dan


Dan Werthimer
Astronomy Dept and Space Sciences Lab
University of California, Berkeley


On Sat, Nov 11, 2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Thanks Dan,
>
>
>
> Yes, one antenna for one receiver, and there is only one frequency
> channel, and a single polarisation, so quite a simple configuration.
>
>
>
> A good idea to use differential inputs as single bit ADCs.
>
>
>
> So the FX correlator looks the better architecture.
>
>
>
> So are you saying the FPGA FX correlator would manage making the
> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
> FPGA, Xilinx or Altera ?
>
>
>
> Cheers,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 20:23
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> by number of receiver channels, i presume you mean number of antennas?
>
> are these single or dual polarization?
>
>
>
> how many spectral channels do you need in your correlator ?
>
>
>
> for a large number of spectral channels,
>
> you'll likely want to use an FX architecture correlator (not XF).
>
> in an FX correlator the number of ADC bits doesn't change the FPGA
> utilization for the DSP very much.
>
>
>
> one fun thing you can do with a 1 bit correlator, is use the LVDS
> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
> with a lot of pins you can get about 512 ADC's
>
> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
> digitizer and your correlator...
>
>
>
> if you only need a small number of spectral channels, you could build an
> XF correlator
>
> with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single
> pol) in a large FPGA.
>
>
>
> with an XF architecture, the FPGA utilization is  J  x
> number_of_spectral_channels.
>
> for FX, the utilization goes as K  x  log_base_2(spectral_channels).
>
>
>
> but constant K >> constant J,
>
> so sometimes (rarely) it is better to use XF, depending on the number of
> spectral channels.
>
>
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> On Sat, Nov 11, 2023 at 11:47 AM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> For a paper on non-radioastronomy aperture synthesis technology I need to
> know how many receiver channels can run into an almost top of the range
> FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So
> each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m
> wondering if there are scaling laws for this and I only need to have a ball
> park figure, ie a precision of say a factor of three or thereabouts. Any
> associate papers related to that which might have clues to the capabilities
> would be helpful.
>
>
>
> Many thanks,
>
> Neil Salmon
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To view this discussion on the web visit
> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk
> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk?utm_medium=email&utm_source=footer>
> .
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To view this discussion on the web visit
> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAGHS_vEdvQAJ9Q5-JOAS1QfJ%3DW8AfQMU9D48cnt_gQ56GA%3DqiA%40mail.gmail.com
> <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAGHS_vEdvQAJ9Q5-JO

RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Hi Dan, 

 

Those are attractive looking numbers. 

 

Is it possible to say how that might scale over the next 5-years, will the 
number of pins go up, faster than the processing speed, or the number of gate 
on board? Is it likely to remain I/O bound of compute bound?

 

Many thanks,

Neil 

 

From: casper@lists.berkeley.edu  On Behalf Of Dan 
Werthimer
Sent: 11 November 2023 21:30
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

for a single frequency channel correlator (continuum correlator), an XF 
architecture (lag correlator) is the way to go,

the number of antennas in your correlator will likely be limited by the number 
of signals you can get into the FPGA. 

(the correlator will be I/O bound, not compute bound, assuming you have a large 
FPGA). 

 

i haven't looked at the number of LVDS inputs available on a large FPGA 
recently, 

but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs 
(1024 pins). 

if so, you can have 512 digitizers, which is 256 complex digitizers, which is 
128 antennas dual pol, or 256 antenna single pol. 

 

as david hawkins suggested, could also use the high speed serdes on the FPGA. 

the new pricy FPGAs have serdes that can work at >100 Gbps. 

and the larger pricy FPGAs have 32 of these serdes, which means you can send 
3.2 Tbits/sec into those FGPAs.

that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at 
1Gcomplexsamples/sec, or 800 antennas dual pol. 

but it would take a lot of electronics to convert 100 1Gbit/sec signals into a 
100Gbit/sec signal - 

the easiest way to convert 100 signals into a single 100Gsps signal would be to 
use an FPGA, 

and that would defeat your goal of using a single FPGA for your correlator.

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 12:43 PM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA with a lot of pins 
you can get about 512 ADC's 

(256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer 
and your correlator...

 

if you only need a small number of spectral channels, you could build an XF 
correlator

with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol) in 
a large FPGA.   

 

with an XF architecture, the FPGA utilization is  J  x  
number_of_spectral_channels. 

for FX, the utilization goes as K  x  log_base_2(spectral_channels). 

 

but constant K >> constant J,  

so sometimes (rarely) it is better to use XF, depending on the number of 
spectral channels. 

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 11:47 AM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

 

Many thanks,

Neil Salmon 

-- 
You received this message because you are subscribed to the Google Groups 
"casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> "

Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

for a single frequency channel correlator (continuum correlator), an XF
architecture (lag correlator) is the way to go,
the number of antennas in your correlator will likely be limited by the
number of signals you can get into the FPGA.
(the correlator will be I/O bound, not compute bound, assuming you have a
large FPGA).

i haven't looked at the number of LVDS inputs available on a large FPGA
recently,
but i think for a ~1800 pin package,  there might be up to ~~512 LVDS pairs
(1024 pins).
if so, you can have 512 digitizers, which is 256 complex digitizers, which
is 128 antennas dual pol, or 256 antenna single pol.

as david hawkins suggested, could also use the high speed serdes on the
FPGA.
the new pricy FPGAs have serdes that can work at >100 Gbps.
and the larger pricy FPGAs have 32 of these serdes, which means you can
send 3.2 Tbits/sec into those FGPAs.
that data rate is 3200 real 1Gsps bit streams,  or 1600 complex streams at
1Gcomplexsamples/sec, or 800 antennas dual pol.
but it would take a lot of electronics to convert 100 1Gbit/sec signals
into a 100Gbit/sec signal -
the easiest way to convert 100 signals into a single 100Gsps signal would
be to use an FPGA,
and that would defeat your goal of using a single FPGA for your correlator.


best wishes,

dan



On Sat, Nov 11, 2023 at 12:43 PM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> Thanks Dan,
>
>
>
> Yes, one antenna for one receiver, and there is only one frequency
> channel, and a single polarisation, so quite a simple configuration.
>
>
>
> A good idea to use differential inputs as single bit ADCs.
>
>
>
> So the FX correlator looks the better architecture.
>
>
>
> So are you saying the FPGA FX correlator would manage making the
> cross-correlations of 512 single bit channels at 1 GbpS, on say a single
> FPGA, Xilinx or Altera ?
>
>
>
> Cheers,
>
> Neil
>
>
>
> *From:* casper@lists.berkeley.edu  *On Behalf
> Of *Dan Werthimer
> *Sent:* 11 November 2023 20:23
> *To:* casper@lists.berkeley.edu
> *Subject:* Re: [casper] state of the art single bit correlators
>
>
>
>
>
> hi neil,
>
>
>
> by number of receiver channels, i presume you mean number of antennas?
>
> are these single or dual polarization?
>
>
>
> how many spectral channels do you need in your correlator ?
>
>
>
> for a large number of spectral channels,
>
> you'll likely want to use an FX architecture correlator (not XF).
>
> in an FX correlator the number of ADC bits doesn't change the FPGA
> utilization for the DSP very much.
>
>
>
> one fun thing you can do with a 1 bit correlator, is use the LVDS
> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
> with a lot of pins you can get about 512 ADC's
>
> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
> digitizer and your correlator...
>
>
>
> if you only need a small number of spectral channels, you could build an
> XF correlator
>
> with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single
> pol) in a large FPGA.
>
>
>
> with an XF architecture, the FPGA utilization is  J  x
> number_of_spectral_channels.
>
> for FX, the utilization goes as K  x  log_base_2(spectral_channels).
>
>
>
> but constant K >> constant J,
>
> so sometimes (rarely) it is better to use XF, depending on the number of
> spectral channels.
>
>
>
>
>
> best wishes,
>
>
>
> dan
>
>
>
>
>
>
>
> On Sat, Nov 11, 2023 at 11:47 AM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
> For a paper on non-radioastronomy aperture synthesis technology I need to
> know how many receiver channels can run into an almost top of the range
> FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So
> each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m
> wondering if there are scaling laws for this and I only need to have a ball
> park figure, ie a precision of say a factor of three or thereabouts. Any
> associate papers related to that which might have clues to the capabilities
> would be helpful.
>
>
>
> Many thanks,
>
> Neil Salmon
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
> To view this discussion on the web visit
> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk
> <https://groups.google.

RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Many thanks Dan, cheers, Neil

 

From: salmon.na via casper@lists.berkeley.edu  
Sent: 11 November 2023 20:43
To: casper@lists.berkeley.edu
Subject: RE: [casper] state of the art single bit correlators

 

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > On Behalf Of 
Dan Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> 
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA with a lot of pins 
you can get about 512 ADC's 

(256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer 
and your correlator...

 

if you only need a small number of spectral channels, you could build an XF 
correlator

with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol) in 
a large FPGA.   

 

with an XF architecture, the FPGA utilization is  J  x  
number_of_spectral_channels. 

for FX, the utilization goes as K  x  log_base_2(spectral_channels). 

 

but constant K >> constant J,  

so sometimes (rarely) it is better to use XF, depending on the number of 
spectral channels. 

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 11:47 AM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

 

Many thanks,

Neil Salmon 

-- 
You received this message because you are subscribed to the Google Groups 
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RE: [casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

Thanks Dan,

 

Yes, one antenna for one receiver, and there is only one frequency channel, and 
a single polarisation, so quite a simple configuration.

 

A good idea to use differential inputs as single bit ADCs. 

 

So the FX correlator looks the better architecture. 

 

So are you saying the FPGA FX correlator would manage making the 
cross-correlations of 512 single bit channels at 1 GbpS, on say a single FPGA, 
Xilinx or Altera ?

 

Cheers,

Neil

 

From: casper@lists.berkeley.edu  On Behalf Of Dan 
Werthimer
Sent: 11 November 2023 20:23
To: casper@lists.berkeley.edu
Subject: Re: [casper] state of the art single bit correlators

 

 

hi neil, 

 

by number of receiver channels, i presume you mean number of antennas? 

are these single or dual polarization? 

 

how many spectral channels do you need in your correlator ?   

 

for a large number of spectral channels, 

you'll likely want to use an FX architecture correlator (not XF).

in an FX correlator the number of ADC bits doesn't change the FPGA utilization 
for the DSP very much. 

 

one fun thing you can do with a 1 bit correlator, is use the LVDS differential 
inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA with a lot of pins 
you can get about 512 ADC's 

(256 antennas, dual pol) built into the FPGA, so the FPGA can be your digitizer 
and your correlator...

 

if you only need a small number of spectral channels, you could build an XF 
correlator

with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol) in 
a large FPGA.   

 

with an XF architecture, the FPGA utilization is  J  x  
number_of_spectral_channels. 

for FX, the utilization goes as K  x  log_base_2(spectral_channels). 

 

but constant K >> constant J,  

so sometimes (rarely) it is better to use XF, depending on the number of 
spectral channels. 

 

 

best wishes,

 

dan

 

 

 

On Sat, Nov 11, 2023 at 11:47 AM salmon.na <http://salmon.na>  via 
casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu>  
mailto:casper@lists.berkeley.edu> > wrote:

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

 

Many thanks,

Neil Salmon 

-- 
You received this message because you are subscribed to the Google Groups 
"casper@lists.berkeley.edu <mailto:casper@lists.berkeley.edu> " group.
To unsubscribe from this group and stop receiving emails from it, send an email 
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<mailto:casper+unsubscr...@lists.berkeley.edu> .
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<https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk?utm_medium=email&utm_source=footer>
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Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi niel,

oops, i just re-read your email and my undestanding is that you are
digitizing complex IQ data at 1 Gsps for I and 1 Gsps for Q  (1 GHz
bandwidth).

so please cut my numbers in my email from a few minutes ago (appended
below) in half:
you can get ~512 signals digitized (or brought in from 512 external 1 bit
digitizers) on a large FGPA,
but that's only 256 complex signals,  or 128 dual pol antennas.
i think the correlator for this many signals will fit in a large FPGA, but
as i mentioned, only if you have a very small number of spectral channels...

best wishes,

dan


On Sat, Nov 11, 2023 at 12:22 PM Dan Werthimer 
wrote:

>
> hi neil,
>
> by number of receiver channels, i presume you mean number of antennas?
> are these single or dual polarization?
>
> how many spectral channels do you need in your correlator ?
>
> for a large number of spectral channels,
> you'll likely want to use an FX architecture correlator (not XF).
> in an FX correlator the number of ADC bits doesn't change the FPGA
> utilization for the DSP very much.
>
> one fun thing you can do with a 1 bit correlator, is use the LVDS
> differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
> with a lot of pins you can get about 512 ADC's
> (256 antennas, dual pol) built into the FPGA, so the FPGA can be your
> digitizer and your correlator...
>
> if you only need a small number of spectral channels, you could build an
> XF correlator
> with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single
> pol) in a large FPGA.
>
> with an XF architecture, the FPGA utilization is  J  x
> number_of_spectral_channels.
> for FX, the utilization goes as K  x  log_base_2(spectral_channels).
>
> but constant K >> constant J,
> so sometimes (rarely) it is better to use XF, depending on the number of
> spectral channels.
>
>
> best wishes,
>
> dan
>
>
>
> On Sat, Nov 11, 2023 at 11:47 AM salmon.na via casper@lists.berkeley.edu <
> casper@lists.berkeley.edu> wrote:
>
>> For a paper on non-radioastronomy aperture synthesis technology I need to
>> know how many receiver channels can run into an almost top of the range
>> FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So
>> each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m
>> wondering if there are scaling laws for this and I only need to have a ball
>> park figure, ie a precision of say a factor of three or thereabouts. Any
>> associate papers related to that which might have clues to the capabilities
>> would be helpful.
>>
>>
>>
>> Many thanks,
>>
>> Neil Salmon
>>
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>> "casper@lists.berkeley.edu" group.
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>> email to casper+unsubscr...@lists.berkeley.edu.
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>> 
>> .
>>
>

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Re: [casper] state of the art single bit correlators

[Dan Werthimer]

hi neil,

by number of receiver channels, i presume you mean number of antennas?
are these single or dual polarization?

how many spectral channels do you need in your correlator ?

for a large number of spectral channels,
you'll likely want to use an FX architecture correlator (not XF).
in an FX correlator the number of ADC bits doesn't change the FPGA
utilization for the DSP very much.

one fun thing you can do with a 1 bit correlator, is use the LVDS
differential inputs on the FPGA as 1 Gsps digitizers.   on a large FPGA
with a lot of pins you can get about 512 ADC's
(256 antennas, dual pol) built into the FPGA, so the FPGA can be your
digitizer and your correlator...

if you only need a small number of spectral channels, you could build an
XF correlator
with ~512 inputs...  (~256 antennas, dual pol, or ~512 antennas single pol)
in a large FPGA.

with an XF architecture, the FPGA utilization is  J  x
number_of_spectral_channels.
for FX, the utilization goes as K  x  log_base_2(spectral_channels).

but constant K >> constant J,
so sometimes (rarely) it is better to use XF, depending on the number of
spectral channels.


best wishes,

dan



On Sat, Nov 11, 2023 at 11:47 AM salmon.na via casper@lists.berkeley.edu <
casper@lists.berkeley.edu> wrote:

> For a paper on non-radioastronomy aperture synthesis technology I need to
> know how many receiver channels can run into an almost top of the range
> FPGA optimally designed single-bit cross-correlator running a 2 Gbps. So
> each receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m
> wondering if there are scaling laws for this and I only need to have a ball
> park figure, ie a precision of say a factor of three or thereabouts. Any
> associate papers related to that which might have clues to the capabilities
> would be helpful.
>
>
>
> Many thanks,
>
> Neil Salmon
>
> --
> You received this message because you are subscribed to the Google Groups "
> casper@lists.berkeley.edu" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to casper+unsubscr...@lists.berkeley.edu.
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> https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/005601da14d7%24ede171b0%24c9a45510%24%40tiscali.co.uk
> 
> .
>

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RE: [EXTERNAL] [casper] state of the art single bit correlators

['Hawkins, David W (US 334B)' via casper@lists.berkeley.edu]

Hi Neil,

For your 1-bit correlation, are you going to implement a lag correlator?

If so, then your logic could be:

  *   ISERDES operating at 1Gbps sampling the complex-valued baseband
  *   4-bits at 250MHz or 8-bits at 125MHz inside the FPGA
  *   Logic to perform 4-bits or 8-bits digital delay line
  *   Logic for 4 or 8 times 1-bit complex-valued correlation and averaging of 
those 4 or 8-bit samples
  *   If you offset your product table so the answers in the table are all 
positive, then you just need an accumulator for your correlation lags
  *   At this point you have correlation products that will generate a 
carry-out at a slow-rate, so you can count those using a carry in on a counter.
  *   You can further decimate the carries, eg., divide-by-2 or 4 to bring the 
clock rate of the counter down to say 125MHz/4  ~ 30MHz

A 4-bit x 4-bit correlator will have 16 inputs (4-bits I + Q for two inputs), 
but FPGA LUTs have 6-inputs, so you will use 3 LUTs for the inputs plus another 
LUT to combine the results of that, so call it 4 LUTs to get each bit of your 
4-bit correlation. If you do some form of deleted-inner-product (like used on 
2-bit correlators) you can probably get away with a 3-bit or 4-bit product, 
which you would register and average … so 16 LUTs and 4 registers for each 
correlation cell.

If your dump rate is say 1s, then at 1GHz sample rate, your number of samples 
is 1G. The number of bits you need in your correlation and accumulation logic 
is log2(1G) = 30-bits, but since the SNR improvement is sqrt(N), so the minimum 
number of bits you want to keep in the accumulation is about 15-bits, i.e., the 
15 MSBs of that accumulator. That means you don’t have to read the LSBs that 
are implemented in the correlation logic, and is the reason why counting the 
carry-out from that logic works fine.

So ….

  *   16 LUTs + 4-registers in each correlation cell
  *   26 more bits in the accumulation logic
Scaled by the number of lags in your correlation result.

Another option to consider, is to use a high-speed transceiver, sample at say 
16Gbps, digitally downconvert and filter the 8GHz of real-valued sampled 
bandwidth down to 2GHz, and that oversampling-by-4 will give you 6dB 
improvement in SNR, so you can implement a 2-bit correlator on the result.

The tradeoff will be a whole lot of LVDS inputs at 1Gbps vs a whole lot of 
transceiver inputs at 16Gbps.

1-bit correlation using high-speed transceivers has been demonstrated by a 
number of people on this list. You just need to force the transceiver into 
lock-to-reference mode to ensure it operates like a synchronous sampler (rather 
than letting the clock-and-data recovery unit track the phase of an incoming 
data stream).

Regards,
Dave

From: salmon.na via casper@lists.berkeley.edu 
Sent: Saturday, November 11, 2023 11:48 AM
To: casper@lists.berkeley.edu
Subject: [EXTERNAL] [casper] state of the art single bit correlators

For a paper on non-radioastronomy aperture synthesis technology I need to know 
how many receiver channels can run into an almost top of the range FPGA 
optimally designed single-bit cross-correlator running a 2 Gbps. So each 
receiver is digitised (sine and cosine) in single bits 1 Gbps. I’m wondering if 
there are scaling laws for this and I only need to have a ball park figure, ie 
a precision of say a factor of three or thereabouts. Any associate papers 
related to that which might have clues to the capabilities would be helpful.

Many thanks,
Neil Salmon
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[casper] state of the art single bit correlators

[salmon.na via casper@lists.berkeley.edu]

For a paper on non-radioastronomy aperture synthesis technology I need to
know how many receiver channels can run into an almost top of the range FPGA
optimally designed single-bit cross-correlator running a 2 Gbps. So each
receiver is digitised (sine and cosine) in single bits 1 Gbps. I'm wondering
if there are scaling laws for this and I only need to have a ball park
figure, ie a precision of say a factor of three or thereabouts. Any
associate papers related to that which might have clues to the capabilities
would be helpful.

 

Many thanks,

Neil Salmon 

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