[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-05 Thread Tulio Magno Quites Machado Filho via cfe-commits 

https://github.com/tuliom closed 
https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-05 Thread via cfe-commits 

github-actions[bot] wrote:



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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-05 Thread via cfe-commits 

wwwatermiao wrote:

> > Hi, @momchil-velikov, Hi, @CarolineConcatto, it will be great if you help 
> > to review this patch as soon as possible! Thank you！
> 
> Patch is accepted, you don't need more approvals, go ahead and commit.

Thank you for your reply, could you help me merge this since I am not a 
commiter? 

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-05 Thread Momchil Velikov via cfe-commits 

momchil-velikov wrote:

> Hi, @momchil-velikov, Hi, @CarolineConcatto, it will be great if you help to 
> review this patch as soon as possible! Thank you！

Patch is accepted, you don't need more approvals, go ahead and commit.

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-05 Thread via cfe-commits 

wwwatermiao wrote:

Hi, @momchil-velikov, Hi, @CarolineConcatto, it will be great if you help to 
review this patch as soon as possible! Thank you！

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-04 Thread via cfe-commits 

wwwatermiao wrote:

> > I thought that this fix will automatically pull from main to other branch 
> > at some tiime
> 
> main is the basis for all future release branches (20.x and later), but we 
> don't automatically pull fixes into release branches that are already created 
> (19.x).
> 
> See 
> https://llvm.org/docs/GitHub.html#backporting-fixes-to-the-release-branches 
> for backporting instructions.

Thank you for your reply, i'll cherry-pick to these branch after this patch 
merging.

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-04 Thread Eli Friedman via cfe-commits 

efriedma-quic wrote:

> I thought that this fix will automatically pull from main to other branch at 
> some tiime

main is the basis for all future release branches (20.x and later), but we 
don't automatically pull fixes into release branches that are already created 
(19.x).

See https://llvm.org/docs/GitHub.html#backporting-fixes-to-the-release-branches 
for backporting instructions.

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-03 Thread via cfe-commits 

wwwatermiao wrote:

Hi, @momchil-velikov, Hi, @CarolineConcatto, can you help me to review this 
patch plz? Thank you!

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-03 Thread via cfe-commits 

https://github.com/wwwatermiao updated 
https://github.com/llvm/llvm-project/pull/118109

>From 4ced088ff94ec203d24e87371fad044260f2f032 Mon Sep 17 00:00:00 2001
From: chenmiao 
Date: Fri, 29 Nov 2024 23:57:48 +0800
Subject: [PATCH] [AArch64][SME] Fix bug on SMELd1St1

Patch[1] has update intrinsic interface for ld1/st1, while based on ARM's 
document,
"If the intrinsic also has a vnum argument, the ZA slice number is calculated 
by adding vnum to slice.".
But the "vnum" did not work for our realization now, this patch fix this point.

[1]https://github.com/llvm/llvm-project/commit/ee31ba0dd923c3a4628cf3887e137843e43c8b22
---
 clang/lib/CodeGen/CGBuiltin.cpp   |   7 +-
 .../sme-intrinsics/acle_sme_ld1_vnum.c| 168 --
 .../sme-intrinsics/acle_sme_st1_vnum.c| 168 --
 3 files changed, 229 insertions(+), 114 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e0504c0e38b22a..256687d8b037b5 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10628,7 +10628,7 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
   NewOps.push_back(Ops[2]);
 
   llvm::Value *BasePtr = Ops[3];
-
+  llvm::Value *RealSlice = Ops[1];
   // If the intrinsic contains the vnum parameter, multiply it with the vector
   // size in bytes.
   if (Ops.size() == 5) {
@@ -10640,10 +10640,13 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
 Builder.CreateMul(StreamingVectorLengthCall, Ops[4], "mulvl");
 // The type of the ptr parameter is void *, so use Int8Ty here.
 BasePtr = Builder.CreateGEP(Int8Ty, Ops[3], Mulvl);
+RealSlice = Builder.CreateZExt(RealSlice, Int64Ty);
+RealSlice = Builder.CreateAdd(RealSlice, Ops[4]);
+RealSlice = Builder.CreateTrunc(RealSlice, Int32Ty);
   }
   NewOps.push_back(BasePtr);
   NewOps.push_back(Ops[0]);
-  NewOps.push_back(Ops[1]);
+  NewOps.push_back(RealSlice);
   Function *F = CGM.getIntrinsic(IntID);
   return Builder.CreateCall(F, NewOps);
 }
diff --git a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c 
b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
index fcbd17559dc702..fb86690f07f1d8 100644
--- a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
+++ b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
@@ -12,9 +12,12 @@
 // CHECK-C-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-C-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-C-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[MULVL]]
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-C-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-C-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-C-NEXT:ret void
 //
 // CHECK-CXX-LABEL: define dso_local void 
@_Z23test_svld1_hor_vnum_za8ju10__SVBool_tPKvl(
@@ -23,9 +26,12 @@
 // CHECK-CXX-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-CXX-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-CXX-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 
[[MULVL]]
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-CXX-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-CXX-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-CXX-NEXT:ret void
 //
 void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, const void 
*ptr, int64_t vnum) __arm_streaming __arm_out("za") {
@@ -40,9 +46,12 @@ void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t 
pg, const void *ptr,
 // CHECK-C-NEXT:[[TMP1:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-C-NEXT:[[MULVL:%.*]] = mul i64 [[TMP1]], [[VNUM]]
 // CHECK-C-NEXT:[[TMP2:%.*]] = ge

[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-02 Thread via cfe-commits 

wwwatermiao wrote:

> It would be good to land this and get this cherry-picked onto the 
> release/19.x branch. Any objection in merging this @wwwatermiao?

Thank you for mentioning this，I think that all the branch would have this 
problem. While this is my first time merge a request so is this necessary to 
merge onto all branch? I thought that this fix will automatically pull from 
main to other branch at some tiime.

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-02 Thread via cfe-commits 

wwwatermiao wrote:

> @wwwatermiao I noticed the author name in the commit is `unknown`. Is that 
> intentional? Would you like to change it?

Thank you! I'll change it later.

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-02 Thread Sander de Smalen via cfe-commits 

sdesmalen-arm wrote:

It would be good to land this and get this cherry-picked onto the release/19.x 
branch. Any objection in merging this @wwwatermiao?

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-02 Thread Tulio Magno Quites Machado Filho via cfe-commits 

tuliom wrote:

@wwwatermiao I noticed the author name in the commit is `unknown`.
Is that intentional? Would you like to change it?

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-12-02 Thread Sander de Smalen via cfe-commits 

https://github.com/sdesmalen-arm approved this pull request.

LGTM, thanks for fixing!

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-11-30 Thread via cfe-commits 

wwwatermiao wrote:

Hi, @tuliom, can you help review my patch plz? Thank you!

https://github.com/llvm/llvm-project/pull/118109
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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-11-29 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang-codegen

Author: None (wwwatermiao)


Changes

Patch[1] has update intrinsic interface for ld1/st1, while based on ARM's 
document, "If the intrinsic also has a vnum argument, the ZA slice number is 
calculated by adding vnum to slice.". But the "vnum" did not work for our 
realization now, this patch fix this point.

[1]https://github.com/llvm/llvm-project/commit/ee31ba0dd923c3a4628cf3887e137843e43c8b22

---

Patch is 51.17 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/118109.diff


3 Files Affected:

- (modified) clang/lib/CodeGen/CGBuiltin.cpp (+5-2) 
- (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c 
(+112-56) 
- (modified) clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_st1_vnum.c 
(+112-56) 


``diff
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e0504c0e38b22a..256687d8b037b5 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10628,7 +10628,7 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
   NewOps.push_back(Ops[2]);
 
   llvm::Value *BasePtr = Ops[3];
-
+  llvm::Value *RealSlice = Ops[1];
   // If the intrinsic contains the vnum parameter, multiply it with the vector
   // size in bytes.
   if (Ops.size() == 5) {
@@ -10640,10 +10640,13 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
 Builder.CreateMul(StreamingVectorLengthCall, Ops[4], "mulvl");
 // The type of the ptr parameter is void *, so use Int8Ty here.
 BasePtr = Builder.CreateGEP(Int8Ty, Ops[3], Mulvl);
+RealSlice = Builder.CreateZExt(RealSlice, Int64Ty);
+RealSlice = Builder.CreateAdd(RealSlice, Ops[4]);
+RealSlice = Builder.CreateTrunc(RealSlice, Int32Ty);
   }
   NewOps.push_back(BasePtr);
   NewOps.push_back(Ops[0]);
-  NewOps.push_back(Ops[1]);
+  NewOps.push_back(RealSlice);
   Function *F = CGM.getIntrinsic(IntID);
   return Builder.CreateCall(F, NewOps);
 }
diff --git a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c 
b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
index fcbd17559dc702..fb86690f07f1d8 100644
--- a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
+++ b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
@@ -12,9 +12,12 @@
 // CHECK-C-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-C-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-C-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[MULVL]]
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-C-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-C-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-C-NEXT:ret void
 //
 // CHECK-CXX-LABEL: define dso_local void 
@_Z23test_svld1_hor_vnum_za8ju10__SVBool_tPKvl(
@@ -23,9 +26,12 @@
 // CHECK-CXX-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-CXX-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-CXX-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 
[[MULVL]]
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-CXX-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-CXX-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-CXX-NEXT:ret void
 //
 void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t pg, const void 
*ptr, int64_t vnum) __arm_streaming __arm_out("za") {
@@ -40,9 +46,12 @@ void test_svld1_hor_vnum_za8(uint32_t slice_base, svbool_t 
pg, const void *ptr,
 // CHECK-C-NEXT:[[TMP1:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-C-NEXT:[[MULVL:%.*]] = mul i64 [[TMP1]], [[VNUM]]
 // CHECK-C-NEXT:[[TMP2:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[MULVL]]
-/

[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-11-29 Thread via cfe-commits 

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[clang] [AArch64][SME] Fix bug on SMELd1St1 (PR #118109)

2024-11-29 Thread via cfe-commits 

https://github.com/wwwatermiao created 
https://github.com/llvm/llvm-project/pull/118109

Patch[1] has update intrinsic interface for ld1/st1, while based on ARM's 
document, "If the intrinsic also has a vnum argument, the ZA slice number is 
calculated by adding vnum to slice.". But the "vnum" did not work for our 
realization now, this patch fix this point.

[1]https://github.com/llvm/llvm-project/commit/ee31ba0dd923c3a4628cf3887e137843e43c8b22

>From d6db1e0e50a0d8c505f52a87fb6ca8898c837a5f Mon Sep 17 00:00:00 2001
From: unknown 
Date: Fri, 29 Nov 2024 23:57:48 +0800
Subject: [PATCH] [AArch64][SME] Fix bug on SMELd1St1

Patch[1] has update intrinsic interface for ld1/st1, while based on ARM's 
document,
"If the intrinsic also has a vnum argument, the ZA slice number is calculated 
by adding vnum to slice.".
But the "vnum" did not work for our realization now, this patch fix this point.

[1]https://github.com/llvm/llvm-project/commit/ee31ba0dd923c3a4628cf3887e137843e43c8b22
---
 clang/lib/CodeGen/CGBuiltin.cpp   |   7 +-
 .../sme-intrinsics/acle_sme_ld1_vnum.c| 168 --
 .../sme-intrinsics/acle_sme_st1_vnum.c| 168 --
 3 files changed, 229 insertions(+), 114 deletions(-)

diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e0504c0e38b22a..256687d8b037b5 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10628,7 +10628,7 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
   NewOps.push_back(Ops[2]);
 
   llvm::Value *BasePtr = Ops[3];
-
+  llvm::Value *RealSlice = Ops[1];
   // If the intrinsic contains the vnum parameter, multiply it with the vector
   // size in bytes.
   if (Ops.size() == 5) {
@@ -10640,10 +10640,13 @@ Value *CodeGenFunction::EmitSMELd1St1(const 
SVETypeFlags &TypeFlags,
 Builder.CreateMul(StreamingVectorLengthCall, Ops[4], "mulvl");
 // The type of the ptr parameter is void *, so use Int8Ty here.
 BasePtr = Builder.CreateGEP(Int8Ty, Ops[3], Mulvl);
+RealSlice = Builder.CreateZExt(RealSlice, Int64Ty);
+RealSlice = Builder.CreateAdd(RealSlice, Ops[4]);
+RealSlice = Builder.CreateTrunc(RealSlice, Int32Ty);
   }
   NewOps.push_back(BasePtr);
   NewOps.push_back(Ops[0]);
-  NewOps.push_back(Ops[1]);
+  NewOps.push_back(RealSlice);
   Function *F = CGM.getIntrinsic(IntID);
   return Builder.CreateCall(F, NewOps);
 }
diff --git a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c 
b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
index fcbd17559dc702..fb86690f07f1d8 100644
--- a/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
+++ b/clang/test/CodeGen/AArch64/sme-intrinsics/acle_sme_ld1_vnum.c
@@ -12,9 +12,12 @@
 // CHECK-C-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-C-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-C-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 [[MULVL]]
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-C-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-C-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-C-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-C-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-C-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-C-NEXT:ret void
 //
 // CHECK-CXX-LABEL: define dso_local void 
@_Z23test_svld1_hor_vnum_za8ju10__SVBool_tPKvl(
@@ -23,9 +26,12 @@
 // CHECK-CXX-NEXT:[[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
 // CHECK-CXX-NEXT:[[MULVL:%.*]] = mul i64 [[TMP0]], [[VNUM]]
 // CHECK-CXX-NEXT:[[TMP1:%.*]] = getelementptr i8, ptr [[PTR]], i64 
[[MULVL]]
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[SLICE_BASE]])
-// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], 15
-// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[ADD]])
+// CHECK-CXX-NEXT:[[TMP2:%.*]] = trunc i64 [[VNUM]] to i32
+// CHECK-CXX-NEXT:[[TMP3:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP3]])
+// CHECK-CXX-NEXT:[[ADD:%.*]] = add i32 [[SLICE_BASE]], [[TMP2]]
+// CHECK-CXX-NEXT:[[TMP4:%.*]] = add i32 [[ADD]], 15
+// CHECK-CXX-NEXT:tail call void @llvm.aarch64.sme.ld1b.horiz( [[PG]], ptr [[TMP1]], i32 0, i32 [[TMP4]])
 // CHECK-CXX-NEXT:ret void
 //
 void test_svld1_hor_vnum_za8(uint32_t slice_ba