[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-06-04 Thread Jiahao Guo via cfe-commits 

https://github.com/E00N777 closed 
https://github.com/llvm/llvm-project/pull/199415
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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-06-03 Thread Andrzej Warzyński via cfe-commits 

https://github.com/banach-space approved this pull request.

Thank you, LGTM!

https://github.com/llvm/llvm-project/pull/199415
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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-06-03 Thread Jiahao Guo via cfe-commits 

https://github.com/E00N777 commented:

@banach-spaceSorry for the late reply, I noticed that lowering logic was 
implemented in PR: https://github.com/llvm/llvm-project/pull/196776. 
I just need to migrate test cases.

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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-06-03 Thread Jiahao Guo via cfe-commits 

https://github.com/E00N777 updated 
https://github.com/llvm/llvm-project/pull/199415

>From c04a0e8310e565b1311e2b908535fabb28bf0cfc Mon Sep 17 00:00:00 2001
From: E0N777 
Date: Sun, 24 May 2026 20:37:10 +0800
Subject: [PATCH] [CIR][AArch64] Lower NEON vslid intrinsics

---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  |  2 ++
 clang/test/CodeGen/AArch64/neon-intrinsics.c  | 26 
 clang/test/CodeGen/AArch64/neon/intrinsics.c  | 31 +++
 3 files changed, 33 insertions(+), 26 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index a06b76d453d48..f0384ade6cf04 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -436,6 +436,8 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
   case NEON::BI__builtin_neon_vqrshrnd_n_u64:
   case NEON::BI__builtin_neon_vsrid_n_s64:
   case NEON::BI__builtin_neon_vsrid_n_u64:
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64:
 break;
   }
 
diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c 
b/clang/test/CodeGen/AArch64/neon-intrinsics.c
index c4eac89e78bc1..06fe4a7489c1d 100644
--- a/clang/test/CodeGen/AArch64/neon-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c
@@ -14527,32 +14527,6 @@ uint64x1_t test_vqshlu_n_s64(int64x1_t a) {
   return vqshlu_n_s64(a, 1);
 }
 
-// CHECK-LABEL: define dso_local i64 @test_vslid_n_s64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:[[VSLID_N_S64:%.*]] = bitcast i64 [[A]] to <1 x i64>
-// CHECK-NEXT:[[VSLID_N_S641:%.*]] = bitcast i64 [[B]] to <1 x i64>
-// CHECK-NEXT:[[VSLID_N_S642:%.*]] = call <1 x i64> 
@llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[VSLID_N_S64]], <1 x i64> 
[[VSLID_N_S641]], i32 63)
-// CHECK-NEXT:[[VSLID_N_S643:%.*]] = bitcast <1 x i64> [[VSLID_N_S642]] to 
i64
-// CHECK-NEXT:ret i64 [[VSLID_N_S643]]
-//
-int64_t test_vslid_n_s64(int64_t a, int64_t b) {
-  return (int64_t)vslid_n_s64(a, b, 63);
-}
-
-// CHECK-LABEL: define dso_local i64 @test_vslid_n_u64(
-// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] {
-// CHECK-NEXT:  [[ENTRY:.*:]]
-// CHECK-NEXT:[[VSLID_N_U64:%.*]] = bitcast i64 [[A]] to <1 x i64>
-// CHECK-NEXT:[[VSLID_N_U641:%.*]] = bitcast i64 [[B]] to <1 x i64>
-// CHECK-NEXT:[[VSLID_N_U642:%.*]] = call <1 x i64> 
@llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[VSLID_N_U64]], <1 x i64> 
[[VSLID_N_U641]], i32 63)
-// CHECK-NEXT:[[VSLID_N_U643:%.*]] = bitcast <1 x i64> [[VSLID_N_U642]] to 
i64
-// CHECK-NEXT:ret i64 [[VSLID_N_U643]]
-//
-uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
-  return (uint64_t)vslid_n_u64(a, b, 63);
-}
-
 // CHECK-LABEL: define dso_local i8 @test_vqshrnh_n_s16(
 // CHECK-SAME: i16 noundef [[A:%.*]]) #[[ATTR0]] {
 // CHECK-NEXT:  [[ENTRY:.*:]]
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c 
b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index efa2691ef611e..716366ee6b79c 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -6437,3 +6437,34 @@ poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) {
 // LLVM:ret <2 x i64> [[VSRI_N2]]
   return vsriq_n_p64(a, b, 64);
 }
+
+//===--===//
+// 2.1.3.1.6.  Vector shift left and insert (scalar)
+// 
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert
+//===--===//
+
+// ALL-LABEL: @test_vslid_n_s64(
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x 
!s64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (int64_t)vslid_n_s64(a, b, 63);
+}
+
+// ALL-LABEL: @test_vslid_n_u64(
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x 
!u64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (uint64_t)vslid_

[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread Andrzej Warzyński via cfe-commits 


@@ -354,24 +354,21 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
   case NEON::BI__builtin_neon_vrecpxh_f16:
   case NEON::BI__builtin_neon_vrsqrteh_f16:
   case NEON::BI__builtin_neon_vrsqrtsh_f16:
-  case NEON::BI__builtin_neon_vmaxv_s8:
-  case NEON::BI__builtin_neon_vmaxvq_s8:
-  case NEON::BI__builtin_neon_vmaxv_s16:
-  case NEON::BI__builtin_neon_vmaxvq_s16:
-  case NEON::BI__builtin_neon_vmaxv_s32:
-  case NEON::BI__builtin_neon_vmaxvq_s32:
-  case NEON::BI__builtin_neon_vmaxv_u8:
-  case NEON::BI__builtin_neon_vmaxvq_u8:
-  case NEON::BI__builtin_neon_vmaxv_u16:
-  case NEON::BI__builtin_neon_vmaxvq_u16:
-  case NEON::BI__builtin_neon_vmaxv_u32:
-  case NEON::BI__builtin_neon_vmaxvq_u32:
-  case NEON::BI__builtin_neon_vmaxv_f32:
-  case NEON::BI__builtin_neon_vmaxvq_f32:
-  case NEON::BI__builtin_neon_vmaxvq_f64:
 return emitNeonCall(cgf.cgm, cgf.getBuilder(),
 {cgf.convertType(expr->getArg(0)->getType())}, ops,
 llvmIntrName, cgf.convertType(expr->getType()), loc);
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64: {
+// The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs
+// in <1 x i64> and unwrap the result back to i64.
+mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType());
+cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1);
+llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
+mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
+  llvmIntrName, vecTy, loc);
+return cgf.getBuilder().createBitcast(result,
+  cgf.convertType(expr->getType()));

banach-space wrote:

This one should go via `emitCommonNeonSISDBuiltinExpr` ;-) See also 
clang/include/clang/Basic/AArch64CodeGenUtils.h (search for e.g. `vslid_n_u64)

https://github.com/llvm/llvm-project/pull/199415
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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread Andrzej Warzyński via cfe-commits 

https://github.com/banach-space commented:

Please don't forget to delete the old tests ;-)

https://github.com/llvm/llvm-project/pull/199415
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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff origin/main HEAD --extensions cpp,c -- 
clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
clang/test/CodeGen/AArch64/neon/intrinsics.c --diff_from_common_commit
``

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:





View the diff from clang-format here.


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index ae299dc46..77c62bcf6 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -381,8 +381,8 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
 llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
 mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
   llvmIntrName, vecTy, loc);
-return cgf.getBuilder().createBitcast(
-result, cgf.convertType(expr->getType()));
+return cgf.getBuilder().createBitcast(result,
+  cgf.convertType(expr->getType()));
   }
   }
 

``




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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread via cfe-commits 

llvmorg-github-actions[bot] wrote:




@llvm/pr-subscribers-clang

Author: Jiahao Guo (E00N777)


Changes

### summary

part of: https://github.com/llvm/llvm-project/issues/185382

this is a follow up of : https://github.com/llvm/llvm-project/pull/198309

This adds CIR lowering for the scalar AArch64 NEON shift-left-and-insert 
intrinsics `vslid_n_s64` and `vslid_n_u64`.

These ACLE builtins expose scalar `i64` interfaces, but the corresponding LLVM 
intrinsic is vector-shaped:

  ```llvm
  llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) -> 
<1 x i64>
  ```
  
  The new lowering wraps the scalar 64-bit operands in one-lane CIR vector 
types, emits the aarch64.neon.vsli LLVM
  intrinsic call, and bitcasts the result back to the scalar return type.

---
Full diff: https://github.com/llvm/llvm-project/pull/199415.diff


2 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+12) 
- (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+31) 


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 18ec9e24722bd..319333d8e46ff 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -357,6 +357,18 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
 return emitNeonCall(cgf.cgm, cgf.getBuilder(),
 {cgf.convertType(expr->getArg(0)->getType())}, ops,
 llvmIntrName, cgf.convertType(expr->getType()), loc);
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64: {
+// The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs
+// in <1 x i64> and unwrap the result back to i64.
+mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType());
+cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1);
+llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
+mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
+  llvmIntrName, vecTy, loc);
+return cgf.getBuilder().createBitcast(
+result, cgf.convertType(expr->getType()));
+  }
   }
 
   return nullptr;
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c 
b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b4fbdcc5436ed..07937d5209e45 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -5096,3 +5096,34 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) {
 // LLVM-NEXT:ret i64 [[VADDLVQ_U32_I]]
   return vaddlvq_u32(a);
 }
+
+//===--===//
+// 2.1.3.1.6.  Vector shift left and insert (scalar)
+// 
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert
+//===--===//
+
+// ALL-LABEL: @test_vslid_n_s64(
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x 
!s64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (int64_t)vslid_n_s64(a, b, 63);
+}
+
+// ALL-LABEL: @test_vslid_n_u64(
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x 
!u64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (uint64_t)vslid_n_u64(a, b, 63);
+}

``




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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread Jiahao Guo via cfe-commits 

https://github.com/E00N777 created 
https://github.com/llvm/llvm-project/pull/199415

### summary

part of: https://github.com/llvm/llvm-project/issues/185382

this is a follow up of : https://github.com/llvm/llvm-project/pull/198309

This adds CIR lowering for the scalar AArch64 NEON shift-left-and-insert 
intrinsics `vslid_n_s64` and `vslid_n_u64`.

These ACLE builtins expose scalar `i64` interfaces, but the corresponding LLVM 
intrinsic is vector-shaped:

  ```llvm
  llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) -> <1 x i64>
  ```
  
  The new lowering wraps the scalar 64-bit operands in one-lane CIR vector 
types, emits the aarch64.neon.vsli LLVM
  intrinsic call, and bitcasts the result back to the scalar return type.

>From abe724454c697dbc32c377a9386e66bc538eb6ee Mon Sep 17 00:00:00 2001
From: E0N777 
Date: Sun, 24 May 2026 20:37:10 +0800
Subject: [PATCH] [CIR][AArch64] Lower NEON vslid intrinsics

---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  | 12 +++
 clang/test/CodeGen/AArch64/neon/intrinsics.c  | 31 +++
 2 files changed, 43 insertions(+)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 18ec9e24722bd..319333d8e46ff 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -357,6 +357,18 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
 return emitNeonCall(cgf.cgm, cgf.getBuilder(),
 {cgf.convertType(expr->getArg(0)->getType())}, ops,
 llvmIntrName, cgf.convertType(expr->getType()), loc);
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64: {
+// The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs
+// in <1 x i64> and unwrap the result back to i64.
+mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType());
+cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1);
+llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
+mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
+  llvmIntrName, vecTy, loc);
+return cgf.getBuilder().createBitcast(
+result, cgf.convertType(expr->getType()));
+  }
   }
 
   return nullptr;
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c 
b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b4fbdcc5436ed..07937d5209e45 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -5096,3 +5096,34 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) {
 // LLVM-NEXT:ret i64 [[VADDLVQ_U32_I]]
   return vaddlvq_u32(a);
 }
+
+//===--===//
+// 2.1.3.1.6.  Vector shift left and insert (scalar)
+// 
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert
+//===--===//
+
+// ALL-LABEL: @test_vslid_n_s64(
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x 
!s64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (int64_t)vslid_n_s64(a, b, 63);
+}
+
+// ALL-LABEL: @test_vslid_n_u64(
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x 
!u64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (uint64_t)vslid_n_u64(a, b, 63);
+}

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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread Jiahao Guo via cfe-commits 

https://github.com/E00N777 updated 
https://github.com/llvm/llvm-project/pull/199415

>From 450277144b8d4085084f1f25adea772689f93072 Mon Sep 17 00:00:00 2001
From: E0N777 
Date: Sun, 24 May 2026 20:37:10 +0800
Subject: [PATCH] [CIR][AArch64] Lower NEON vslid intrinsics

---
 .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp  | 12 +++
 clang/test/CodeGen/AArch64/neon/intrinsics.c  | 31 +++
 2 files changed, 43 insertions(+)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 18ec9e24722bd..e3c03c76cf3ad 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -357,6 +357,18 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
 return emitNeonCall(cgf.cgm, cgf.getBuilder(),
 {cgf.convertType(expr->getArg(0)->getType())}, ops,
 llvmIntrName, cgf.convertType(expr->getType()), loc);
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64: {
+// The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs
+// in <1 x i64> and unwrap the result back to i64.
+mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType());
+cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1);
+llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
+mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
+  llvmIntrName, vecTy, loc);
+return cgf.getBuilder().createBitcast(result,
+  cgf.convertType(expr->getType()));
+  }
   }
 
   return nullptr;
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c 
b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b4fbdcc5436ed..07937d5209e45 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -5096,3 +5096,34 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) {
 // LLVM-NEXT:ret i64 [[VADDLVQ_U32_I]]
   return vaddlvq_u32(a);
 }
+
+//===--===//
+// 2.1.3.1.6.  Vector shift left and insert (scalar)
+// 
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert
+//===--===//
+
+// ALL-LABEL: @test_vslid_n_s64(
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x 
!s64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (int64_t)vslid_n_s64(a, b, 63);
+}
+
+// ALL-LABEL: @test_vslid_n_u64(
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x 
!u64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (uint64_t)vslid_n_u64(a, b, 63);
+}

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[clang] [CIR][AArch64] Lower NEON vslid intrinsics (PR #199415)

2026-05-25 Thread via cfe-commits 

llvmorg-github-actions[bot] wrote:




@llvm/pr-subscribers-clangir

Author: Jiahao Guo (E00N777)


Changes

### summary

part of: https://github.com/llvm/llvm-project/issues/185382

this is a follow up of : https://github.com/llvm/llvm-project/pull/198309

This adds CIR lowering for the scalar AArch64 NEON shift-left-and-insert 
intrinsics `vslid_n_s64` and `vslid_n_u64`.

These ACLE builtins expose scalar `i64` interfaces, but the corresponding LLVM 
intrinsic is vector-shaped:

  ```llvm
  llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) -> 
<1 x i64>
  ```
  
  The new lowering wraps the scalar 64-bit operands in one-lane CIR vector 
types, emits the aarch64.neon.vsli LLVM
  intrinsic call, and bitcasts the result back to the scalar return type.

---
Full diff: https://github.com/llvm/llvm-project/pull/199415.diff


2 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+12) 
- (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+31) 


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index 18ec9e24722bd..319333d8e46ff 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -357,6 +357,18 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr(
 return emitNeonCall(cgf.cgm, cgf.getBuilder(),
 {cgf.convertType(expr->getArg(0)->getType())}, ops,
 llvmIntrName, cgf.convertType(expr->getType()), loc);
+  case NEON::BI__builtin_neon_vslid_n_s64:
+  case NEON::BI__builtin_neon_vslid_n_u64: {
+// The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs
+// in <1 x i64> and unwrap the result back to i64.
+mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType());
+cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1);
+llvm::SmallVector argTypes = {vecTy, vecTy, ops[2].getType()};
+mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops,
+  llvmIntrName, vecTy, loc);
+return cgf.getBuilder().createBitcast(
+result, cgf.convertType(expr->getType()));
+  }
   }
 
   return nullptr;
diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c 
b/clang/test/CodeGen/AArch64/neon/intrinsics.c
index b4fbdcc5436ed..07937d5209e45 100644
--- a/clang/test/CodeGen/AArch64/neon/intrinsics.c
+++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c
@@ -5096,3 +5096,34 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) {
 // LLVM-NEXT:ret i64 [[VADDLVQ_U32_I]]
   return vaddlvq_u32(a);
 }
+
+//===--===//
+// 2.1.3.1.6.  Vector shift left and insert (scalar)
+// 
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert
+//===--===//
+
+// ALL-LABEL: @test_vslid_n_s64(
+int64_t test_vslid_n_s64(int64_t a, int64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x 
!s64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (int64_t)vslid_n_s64(a, b, 63);
+}
+
+// ALL-LABEL: @test_vslid_n_u64(
+uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) {
+// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} 
: (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x 
!u64i>
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64>
+// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64>
+// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x 
i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63)
+// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64
+// LLVM: ret i64 [[RET]]
+  return (uint64_t)vslid_n_u64(a, b, 63);
+}

``




https://github.com/llvm/llvm-project/pull/199415
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