[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-21 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor approved this pull request.

lgtm

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-14 Thread Andy Kaylor via cfe-commits 


@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s
+
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {

andykaylor wrote:

It still needs the additional test cases.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-14 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 deleted 
https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-13 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 updated 
https://github.com/llvm/llvm-project/pull/169648

>From 2182c2f98a94481d3e3a539fffaf02ab2bcf5769 Mon Sep 17 00:00:00 2001
From: AnkitDubeycs25 
Date: Wed, 26 Nov 2025 18:17:45 +0530
Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store
 Intrinsics

Implement CIR lowering for X86 AVX-512 compress store builtins by
adding emitX86CompressStore() which emits a masked_compressstore MLIR
op, wired up for all compres store builtin variants.
---
 clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp| 23 +++
 .../CodeGenBuiltins/X86/avx512vl-builtins.c   | 10 
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6ca8a0e7a460f..344da9a2a6e0c 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+  mlir::Value ptr = ops[0];
+  return builder.emitIntrinsicCallOp(loc, "masked_compressstore", resultTy,
+   mlir::ValueRange{ops[1], ops[0], 
maskValue});
+}
+
 // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins.
 //
 // The vector is split into lanes of 8 word elements (16 bits). The lower or
@@ -1231,7 +1242,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask: {
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -1250,10 +1266,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
-cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
-return mlir::Value{};
+return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c 
b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
index e3cbc0fc10524..c280f2380cf57 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
@@ -727,3 +727,13 @@ __m256i test_mm256_maskz_load_epi64(__mmask8 __U, void 
const *__P) {
   // OGCG: @llvm.masked.load.v4i64.p0(ptr align 32 %{{.*}}, <4 x i1> %{{.*}}, 
<4 x i64> %{{.*}})  
   return _mm256_maskz_load_epi64(__U, __P); 
 }
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {
+  // CIR-LABEL: test_compress_store
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store
+  // LLVM: @llvm.masked.compressstore
+  // OGCG-LABEL: @test_compress_store
+  // OGCG: @llvm.masked.compressstore
+  return _mm_mask_compressstoreu_pd(__P, __U, __A);
+}

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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-13 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 updated 
https://github.com/llvm/llvm-project/pull/169648

>From 15da7125da27d71389482cac29e15a2813e67a66 Mon Sep 17 00:00:00 2001
From: AnkitDubeycs25 
Date: Wed, 26 Nov 2025 18:17:45 +0530
Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store
 Intrinsics

Implement CIR lowering for X86 AVX-512 compress store builtins by
adding emitX86CompressStore() which emits a masked_compressstore MLIR
op, wired up for all compres store builtin variants.
---
 clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp| 23 +++--
 .../CodeGenBuiltins/X86/avx512vl-builtins.c   | 50 +++
 2 files changed, 68 insertions(+), 5 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6ca8a0e7a460f..b9ed2829faad3 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+
+  return builder.emitIntrinsicCallOp(loc, "masked_compressstore", resultTy,
+   mlir::ValueRange{ops[1], ptr, maskValue});
+}
+
 // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins.
 //
 // The vector is split into lanes of 8 word elements (16 bits). The lower or
@@ -1231,7 +1242,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask: {
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -1250,10 +1266,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
-cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
-return mlir::Value{};
+return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c 
b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
index e3cbc0fc10524..019584173e3a7 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
@@ -727,3 +727,53 @@ __m256i test_mm256_maskz_load_epi64(__mmask8 __U, void 
const *__P) {
   // OGCG: @llvm.masked.load.v4i64.p0(ptr align 32 %{{.*}}, <4 x i1> %{{.*}}, 
<4 x i64> %{{.*}})  
   return _mm256_maskz_load_epi64(__U, __P); 
 }
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {
+  // CIR-LABEL: test_compress_store
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store
+  // LLVM: @llvm.masked.compressstore
+  // OGCG-LABEL: @test_compress_store
+  // OGCG: @llvm.masked.compressstore
+  return _mm_mask_compressstoreu_pd(__P, __U, __A);
+}
+
+void test_compress_store_pd256(void *__P, __mmask8 __U, __m256d __A) {
+  // CIR-LABEL: test_compress_store_pd256
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store_pd256
+  // LLVM: @llvm.masked.compressstore
+  // OGCG-LABEL: @test_compress_store_pd256
+  // OGCG: @llvm.masked.compressstore
+  return _mm256_mask_compressstoreu_pd(__P, __U, __A);
+}
+
+void test_compress_store_ps128(void *__P, __mmask8 __U, __m128 __A) {
+  // CIR-LABEL: test_compress_store_ps128
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store_ps128
+  // LLVM: @llvm.masked.compressstore
+  // OGCG-LABEL: @test_compress_store_ps128
+  // OGCG: @llvm.masked.compressstore
+  return _mm_mask_compressstoreu_ps(__P, __U, __A);
+}
+
+void test_compress_store_epi32(void *__P, __mmask8 __U, __m128i __A) {
+  // CIR-LABEL: test_compress_store_epi32
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLV

[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-12 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 updated 
https://github.com/llvm/llvm-project/pull/169648

>From de5d5b1bede7a4430eeffdaec8b04f57d535e2e1 Mon Sep 17 00:00:00 2001
From: AnkitDubeycs25 
Date: Wed, 26 Nov 2025 18:17:45 +0530
Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store
 Intrinsics

Implement CIR lowering for X86 AVX-512 compress store builtins by
adding emitX86CompressStore() which emits a masked_compressstore MLIR
op, wired up for all compres store builtin variants.
---
 clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp| 24 +++
 .../CodeGenBuiltins/X86/avx512vl-builtins.c   | 10 
 2 files changed, 29 insertions(+), 5 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6ca8a0e7a460f..eb915c010723e 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -86,6 +86,18 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+
+  return builder.emitIntrinsicCallOp(
+  loc, "masked_compressstore", resultTy,
+  mlir::ValueRange{ops[1], ops[0], maskValue});
+}
+
 // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins.
 //
 // The vector is split into lanes of 8 word elements (16 bits). The lower or
@@ -1231,7 +1243,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask: {
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -1250,10 +1267,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
-cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
-return mlir::Value{};
+return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c 
b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
index e3cbc0fc10524..c280f2380cf57 100644
--- a/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
+++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c
@@ -727,3 +727,13 @@ __m256i test_mm256_maskz_load_epi64(__mmask8 __U, void 
const *__P) {
   // OGCG: @llvm.masked.load.v4i64.p0(ptr align 32 %{{.*}}, <4 x i1> %{{.*}}, 
<4 x i64> %{{.*}})  
   return _mm256_maskz_load_epi64(__U, __P); 
 }
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {
+  // CIR-LABEL: test_compress_store
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store
+  // LLVM: @llvm.masked.compressstore
+  // OGCG-LABEL: @test_compress_store
+  // OGCG: @llvm.masked.compressstore
+  return _mm_mask_compressstoreu_pd(__P, __U, __A);
+}

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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-11 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 edited 
https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-11 Thread via cfe-commits 


@@ -0,0 +1,5 @@
+#include 

AnkitDubeycs25 wrote:

Resolved succesfully

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 


@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s
+
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {

andykaylor wrote:

Can you move this to the existing 
`clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c` test. Also, this only 
tests one of the variations. Can you port the others from 
`clang/test/CodeGen/X86/avx512vl-builtins.c`:

```
void test_mm_mask_compressstoreu_pd(void *__P, __mmask8 __U, __m128d __A) {
  // CHECK-LABEL: test_mm_mask_compressstoreu_pd
  // CHECK: @llvm.masked.compressstore.v2f64(<2 x double> %{{.*}}, ptr %{{.*}}, 
<2 x i1> %{{.*}})
  return _mm_mask_compressstoreu_pd(__P,__U,__A); 
}
void test_mm256_mask_compressstoreu_pd(void *__P, __mmask8 __U, __m256d __A) {
  // CHECK-LABEL: test_mm256_mask_compressstoreu_pd
  // CHECK: @llvm.masked.compressstore.v4f64(<4 x double> %{{.*}}, ptr %{{.*}}, 
<4 x i1> %{{.*}})
  return _mm256_mask_compressstoreu_pd(__P,__U,__A); 
}
void test_mm_mask_compressstoreu_epi64(void *__P, __mmask8 __U, __m128i __A) {
  // CHECK-LABEL: test_mm_mask_compressstoreu_epi64
  // CHECK: @llvm.masked.compressstore.v2i64(<2 x i64> %{{.*}}, ptr %{{.*}}, <2 
x i1> %{{.*}})
  return _mm_mask_compressstoreu_epi64(__P,__U,__A); 
}
void test_mm256_mask_compressstoreu_epi64(void *__P, __mmask8 __U, __m256i __A) 
{
  // CHECK-LABEL: test_mm256_mask_compressstoreu_epi64
  // CHECK: @llvm.masked.compressstore.v4i64(<4 x i64> %{{.*}}, ptr %{{.*}}, <4 
x i1> %{{.*}})
  return _mm256_mask_compressstoreu_epi64(__P,__U,__A); 
}
void test_mm_mask_compressstoreu_ps(void *__P, __mmask8 __U, __m128 __A) {
  // CHECK-LABEL: test_mm_mask_compressstoreu_ps
  // CHECK: @llvm.masked.compressstore.v4f32(<4 x float> %{{.*}}, ptr %{{.*}}, 
<4 x i1> %{{.*}})
  return _mm_mask_compressstoreu_ps(__P,__U,__A); 
}
void test_mm256_mask_compressstoreu_ps(void *__P, __mmask8 __U, __m256 __A) {
  // CHECK-LABEL: test_mm256_mask_compressstoreu_ps
  // CHECK: @llvm.masked.compressstore.v8f32(<8 x float> %{{.*}}, ptr %{{.*}}, 
<8 x i1> %{{.*}})
  return _mm256_mask_compressstoreu_ps(__P,__U,__A); 
}
void test_mm_mask_compressstoreu_epi32(void *__P, __mmask8 __U, __m128i __A) {
  // CHECK-LABEL: test_mm_mask_compressstoreu_epi32
  // CHECK: @llvm.masked.compressstore.v4i32(<4 x i32> %{{.*}}, ptr %{{.*}}, <4 
x i1> %{{.*}})
  return _mm_mask_compressstoreu_epi32(__P,__U,__A); 
}
void test_mm256_mask_compressstoreu_epi32(void *__P, __mmask8 __U, __m256i __A) 
{
  // CHECK-LABEL: test_mm256_mask_compressstoreu_epi32
  // CHECK: @llvm.masked.compressstore.v8i32(<8 x i32> %{{.*}}, ptr %{{.*}}, <8 
x i1> %{{.*}})
  return _mm256_mask_compressstoreu_epi32(__P,__U,__A); 
}
```
The check lines will need to be updated, of course, but otherwise you should be 
able to use these directly.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 


@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s
+
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {
+  // CIR-LABEL: test_compress_store
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store
+  // LLVM: @llvm.x86.avx512.mask.compress.store
+  // OGCG-LABEL: @test_compress_store
+  // OGCG: @llvm.x86.avx512.mask.compress.store
+  return _mm_mask_compressstoreu_pd(__P, __U, __A);
+}

andykaylor wrote:

You're missing a newline at the end of the file. It's a minor point, but we try 
to be consistent about this.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 


@@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+  mlir::Value ptr = ops[0];

andykaylor wrote:

I do see any value in saving this to a temporary. I realize classic codegen 
does that too, but I don't see any value in it there either. It could be an 
artifact of some earlier state.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 


@@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+  mlir::Value ptr = ops[0];
+  return emitIntrinsicCallOp(builder, loc, "masked_compressstore", resultTy,
+ mlir::ValueRange{ops[1], ptr, maskValue});

andykaylor wrote:

```suggestion
  return emitIntrinsicCallOp(builder, loc, "masked_compressstore", resultTy,
 mlir::ValueRange{ops[1], ops[0], maskValue});
```

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor edited 
https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-09 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor commented:

This looks great. I just have one nit about the implementation and a couple of 
requests to change the test.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-08 Thread via cfe-commits 

AnkitDubeycs25 wrote:

Sorry for the long delay! I've addressed all the review comments:

Updated function signature to use CIRGenBuilderTy &builder, mlir::Location loc
Switched to mlir::ValueRange
Moved test to clang/test/CIR/CodeGenBuiltins/X86/ with proper RUN/CIR/LLVM/OGCG 
check lines
Fixed clang-format issues
Rebased onto latest main

@andykaylor @bcardosolopes please take another look!

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2026-05-08 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 updated 
https://github.com/llvm/llvm-project/pull/169648

>From f6f3a83c0ebed7578df841570b7ac636307cfded Mon Sep 17 00:00:00 2001
From: AnkitDubeycs25 
Date: Wed, 26 Nov 2025 18:17:45 +0530
Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Implement Compress Store
 Intrinsics

Implement CIR lowering for X86 AVX-512 compress store builtins by
adding emitX86CompressStore() which emits a masked_compressstore MLIR
op, wired up for all compres store builtin variants.
---
 clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp| 23 +++
 .../X86/compressStore_builtin.c   | 18 +++
 2 files changed, 36 insertions(+), 5 deletions(-)
 create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/compressStore_builtin.c

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 6ca8a0e7a460f..7932935dc41ff 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -86,6 +86,17 @@ static mlir::Value getMaskVecValue(CIRGenBuilderTy &builder, 
mlir::Location loc,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder,
+mlir::Location loc,
+ArrayRef ops) {
+  auto resultTy = cast(ops[1].getType());
+  mlir::Value maskValue =
+  getMaskVecValue(builder, loc, ops[2], resultTy.getSize());
+  mlir::Value ptr = ops[0];
+  return emitIntrinsicCallOp(builder, loc, "masked_compressstore", resultTy,
+ mlir::ValueRange{ops[1], ptr, maskValue});
+}
+
 // Builds the VecShuffleOp for pshuflw and pshufhw x86 builtins.
 //
 // The vector is split into lanes of 8 word elements (16 bits). The lower or
@@ -1231,7 +1242,12 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask: {
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -1250,10 +1266,7 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, 
const CallExpr *expr) {
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
-cgm.errorNYI(expr->getSourceRange(),
- std::string("unimplemented X86 builtin call: ") +
- getContext().BuiltinInfo.getName(builtinID));
-return mlir::Value{};
+return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGenBuiltins/X86/compressStore_builtin.c 
b/clang/test/CIR/CodeGenBuiltins/X86/compressStore_builtin.c
new file mode 100644
index 0..42134ef46fc4a
--- /dev/null
+++ b/clang/test/CIR/CodeGenBuiltins/X86/compressStore_builtin.c
@@ -0,0 +1,18 @@
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s 
-triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl 
-emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
+// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s
+
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A) {
+  // CIR-LABEL: test_compress_store
+  // CIR: cir.call_llvm_intrinsic "masked_compressstore"
+  // LLVM-LABEL: @test_compress_store
+  // LLVM: @llvm.x86.avx512.mask.compress.store
+  // OGCG-LABEL: @test_compress_store
+  // OGCG: @llvm.x86.avx512.mask.compress.store
+  return _mm_mask_compressstoreu_pd(__P, __U, __A);
+}
\ No newline at end of file

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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-18 Thread Bruno Cardoso Lopes via cfe-commits 

bcardosolopes wrote:

This also needs to pass clang-format

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-02 Thread via cfe-commits 

github-actions[bot] wrote:


# :penguin: Linux x64 Test Results

* 3053 tests passed
* 7 tests skipped

All tests passed but another part of the build **failed**. Click on a failure 
below to see the details.


tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenAtomic.cpp.o

```
FAILED: 
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenAtomic.cpp.o
sccache /opt/llvm/bin/clang++ -DCLANG_EXPORTS -DGTEST_HAS_RTTI=0 -D_DEBUG 
-D_GLIBCXX_ASSERTIONS -D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE 
-D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/lib/CIR/CodeGen
 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen
 -I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/include 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/include
 -I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/include 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/include 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/../mlir/include 
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/mlir/include
 -gmlt -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror 
-Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra 
-Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers 
-pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough 
-Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor 
-Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion 
-Wno-pass-failed -Wmisleading-indentation -Wctad-maybe-unsupported 
-fdiagnostics-color -ffunction-sections -fdata-sections -fno-common 
-Woverloaded-virtual -Wno-nested-anon-types -O3 -DNDEBUG -std=c++17  
-fno-exceptions -funwind-tables -fno-rtti -UNDEBUG -MD -MT 
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenAtomic.cpp.o -MF 
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenAtomic.cpp.o.d -o 
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/CIRGenAtomic.cpp.o -c 
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/CIRGenAtomic.cpp:419:11:
 error: enumeration values 'AO__scoped_atomic_udec_wrap' and 
'AO__scoped_atomic_uinc_wrap' not handled in switch [-Werror,-Wswitch]
419 |   switch (expr->getOp()) {
|   ^
1 error generated.
```


If these failures are unrelated to your changes (for example tests are broken 
or flaky at HEAD), please open an issue at 
https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-02 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff origin/main HEAD --extensions cpp,c -- 
clang/test/CIR/CodeGen/X86/compressStore_builtin.c 
clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp --diff_from_common_commit
``

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:





View the diff from clang-format here.


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 5c3e7f751..d45ee7e90 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -90,13 +90,17 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
-static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf,
+const CallExpr *expr,
+ArrayRef ops) {
   auto ResultTy = cast(ops[1].getType());
-  mlir::Value MaskValue = getMaskVecValue(cgf, expr, ops[2],  
cast(ResultTy).getSize());
+  mlir::Value MaskValue = getMaskVecValue(
+  cgf, expr, ops[2], cast(ResultTy).getSize());
   mlir::Value ptr = ops[0];
 
-  return emitIntrinsicCallOp(cgf, expr, "masked_compressstore", ResultTy, 
llvm::SmallVector{ops[1], ptr, MaskValue});
-
+  return emitIntrinsicCallOp(
+  cgf, expr, "masked_compressstore", ResultTy,
+  llvm::SmallVector{ops[1], ptr, MaskValue});
 }
 mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
@@ -408,7 +412,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:{
+  case X86::BI__builtin_ia32_expandloadqi512_mask: {
 cgm.errorNYI(expr->getSourceRange(),
  std::string("unimplemented X86 builtin call: ") +
  getContext().BuiltinInfo.getName(builtinID));

``




https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 


@@ -419,6 +432,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
+return emitX86CompressStore(*this, expr, ops);

andykaylor wrote:

```suggestion
return emitX86CompressStore(builder, getLoc(expr->getExprLoc()), ops);
```

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 


@@ -90,6 +90,14 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){

andykaylor wrote:

```suggestion
static mlir::Value emitX86CompressStore(CIRGenBuilderTy &builder, 
mlir::Location loc, ArrayRef ops){
```
The signature of `emitIntrinsicCallOp` has recently been updated. This change 
makes the function you are adding consistent with it.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor commented:

Thanks for the patch! I have a few requests for changes.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 


@@ -90,6 +90,14 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){
+  auto ResultTy = cast(ops[1].getType());
+  mlir::Value MaskValue = getMaskVecValue(cgf, expr, ops[2],  
cast(ResultTy).getSize());
+  mlir::Value ptr = ops[0];
+
+  return emitIntrinsicCallOp(cgf, expr, "masked_compressstore", ResultTy, 
llvm::SmallVector{ops[1], ptr, MaskValue});

andykaylor wrote:

```suggestion
  return emitIntrinsicCallOp(builder, loc, "masked_compressstore", ResultTy, 
mlir::ValueRange{ops[1], ptr, MaskValue});
```

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 


@@ -0,0 +1,5 @@
+#include 

andykaylor wrote:

This test should be moved to 
`clang/test/CIR/CodeGenBuiltins/X86/avx512vl-builtins.c` which is also being 
added in https://github.com/llvm/llvm-project/pull/169582. The test will need 
RUN lines and CIR, LLVM, and OGCG checks added.

https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-12-01 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor edited 
https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 ready_for_review 
https://github.com/llvm/llvm-project/pull/169648
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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: AnkitDubeycs25 (AnkitDubeycs25)


Changes

This is my first commit. Requesting reviews.

---
Full diff: https://github.com/llvm/llvm-project/pull/169648.diff


2 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+15-1) 
- (added) clang/test/CIR/CodeGen/X86/compressStore_builtin.c (+5) 


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index e7aa8a234efd9..5c3e7f7512851 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -90,6 +90,14 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){
+  auto ResultTy = cast(ops[1].getType());
+  mlir::Value MaskValue = getMaskVecValue(cgf, expr, ops[2],  
cast(ResultTy).getSize());
+  mlir::Value ptr = ops[0];
+
+  return emitIntrinsicCallOp(cgf, expr, "masked_compressstore", ResultTy, 
llvm::SmallVector{ops[1], ptr, MaskValue});
+
+}
 mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
   if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -400,7 +408,12 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask:{
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -419,6 +432,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
+return emitX86CompressStore(*this, expr, ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGen/X86/compressStore_builtin.c 
b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
new file mode 100644
index 0..1407e21428aee
--- /dev/null
+++ b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
@@ -0,0 +1,5 @@
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A){
+return _mm_mask_compressstoreu_pd (__P, __U, __A);
+}
\ No newline at end of file

``




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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clangir

Author: AnkitDubeycs25 (AnkitDubeycs25)


Changes

This is my first commit. Requesting reviews.

---
Full diff: https://github.com/llvm/llvm-project/pull/169648.diff


2 Files Affected:

- (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp (+15-1) 
- (added) clang/test/CIR/CodeGen/X86/compressStore_builtin.c (+5) 


``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index e7aa8a234efd9..5c3e7f7512851 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -90,6 +90,14 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){
+  auto ResultTy = cast(ops[1].getType());
+  mlir::Value MaskValue = getMaskVecValue(cgf, expr, ops[2],  
cast(ResultTy).getSize());
+  mlir::Value ptr = ops[0];
+
+  return emitIntrinsicCallOp(cgf, expr, "masked_compressstore", ResultTy, 
llvm::SmallVector{ops[1], ptr, MaskValue});
+
+}
 mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
   if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -400,7 +408,12 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask:{
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -419,6 +432,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
+return emitX86CompressStore(*this, expr, ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGen/X86/compressStore_builtin.c 
b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
new file mode 100644
index 0..1407e21428aee
--- /dev/null
+++ b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
@@ -0,0 +1,5 @@
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A){
+return _mm_mask_compressstoreu_pd (__P, __U, __A);
+}
\ No newline at end of file

``




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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 created 
https://github.com/llvm/llvm-project/pull/169648

This is my first commit. Requesting reviews.

>From 738a2111fdc5f56d3f5f53a9d3a05fed689b74f3 Mon Sep 17 00:00:00 2001
From: AnkitDubeycs25 
Date: Wed, 26 Nov 2025 18:17:45 +0530
Subject: [PATCH] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics

This is my first commit. Requesting reviews.
---
 clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp   | 16 +++-
 .../test/CIR/CodeGen/X86/compressStore_builtin.c |  5 +
 2 files changed, 20 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/CIR/CodeGen/X86/compressStore_builtin.c

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index e7aa8a234efd9..5c3e7f7512851 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -90,6 +90,14 @@ static mlir::Value getMaskVecValue(CIRGenFunction &cgf, 
const CallExpr *expr,
   return maskVec;
 }
 
+static mlir::Value emitX86CompressStore(CIRGenFunction &cgf, const CallExpr 
*expr, ArrayRef ops){
+  auto ResultTy = cast(ops[1].getType());
+  mlir::Value MaskValue = getMaskVecValue(cgf, expr, ops[2],  
cast(ResultTy).getSize());
+  mlir::Value ptr = ops[0];
+
+  return emitIntrinsicCallOp(cgf, expr, "masked_compressstore", ResultTy, 
llvm::SmallVector{ops[1], ptr, MaskValue});
+
+}
 mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
   if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -400,7 +408,12 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_expandloadhi512_mask:
   case X86::BI__builtin_ia32_expandloadqi128_mask:
   case X86::BI__builtin_ia32_expandloadqi256_mask:
-  case X86::BI__builtin_ia32_expandloadqi512_mask:
+  case X86::BI__builtin_ia32_expandloadqi512_mask:{
+cgm.errorNYI(expr->getSourceRange(),
+ std::string("unimplemented X86 builtin call: ") +
+ getContext().BuiltinInfo.getName(builtinID));
+return {};
+  }
   case X86::BI__builtin_ia32_compressstoredf128_mask:
   case X86::BI__builtin_ia32_compressstoredf256_mask:
   case X86::BI__builtin_ia32_compressstoredf512_mask:
@@ -419,6 +432,7 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned 
builtinID,
   case X86::BI__builtin_ia32_compressstoreqi128_mask:
   case X86::BI__builtin_ia32_compressstoreqi256_mask:
   case X86::BI__builtin_ia32_compressstoreqi512_mask:
+return emitX86CompressStore(*this, expr, ops);
   case X86::BI__builtin_ia32_expanddf128_mask:
   case X86::BI__builtin_ia32_expanddf256_mask:
   case X86::BI__builtin_ia32_expanddf512_mask:
diff --git a/clang/test/CIR/CodeGen/X86/compressStore_builtin.c 
b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
new file mode 100644
index 0..1407e21428aee
--- /dev/null
+++ b/clang/test/CIR/CodeGen/X86/compressStore_builtin.c
@@ -0,0 +1,5 @@
+#include 
+
+void test_compress_store(void *__P, __mmask8 __U, __m128d __A){
+return _mm_mask_compressstoreu_pd (__P, __U, __A);
+}
\ No newline at end of file

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[clang] [CIR][CIRGen][Builtin][X86] Compress Store Intrinsics (PR #169648)

2025-11-28 Thread via cfe-commits 

https://github.com/AnkitDubeycs25 converted_to_draft 
https://github.com/llvm/llvm-project/pull/169648
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