[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: The surface type lowering itself appears to work, but the test hits existing NYIs in CUDA runtime registration: - CIRGenNVCUDARuntime::handleVarRegistration (Surface and Texture registration), - LoweringPreparePass (Surface registration NYI) OG CodeGen implements these through registerDeviceSurf / registerDeviceTex, but CIR currently has no corresponding implementation. Should support for surface registration be added as part of this PR? https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 deleted https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Men-cotton updated
https://github.com/llvm/llvm-project/pull/196079
>From a881019f9c4942ca96f0ea643bbc32586c8eb28a Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/8] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index fc939cd9605ab..a88f662e5a132 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -132,6 +132,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index ecdfb7cb42c0e..8c00ec186ef94 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -66,6 +66,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 4921dc6b7761c246230591c01a7cb42560d6922f Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/8] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From b64a002698c6dddb1fe0a34f56b2bdd5d1fa20fa Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/8] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/C
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
github-actions[bot] wrote:
# :penguin: Linux x64 Test Results
The build failed before running any tests. Click on a failure below to see the
details.
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/Targets/NVPTX.cpp.o
```
FAILED:
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/Targets/NVPTX.cpp.o
sccache /opt/llvm/bin/clang++ -DCLANG_EXPORTS -D_DEBUG -D_GLIBCXX_ASSERTIONS
-D_GLIBCXX_USE_CXX11_ABI=1 -D_GNU_SOURCE
-D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_EXTENSIVE
-D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/lib/CIR/CodeGen
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/include
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/clang/include
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/include
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/include
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/../mlir/include
-I/home/gha/actions-runner/_work/llvm-project/llvm-project/build/tools/mlir/include
-gmlt -fPIC -fno-semantic-interposition -fvisibility-inlines-hidden -Werror
-Werror=date-time -Werror=unguarded-availability-new -Wall -Wextra
-Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers
-pedantic -Wno-long-long -Wc++98-compat-extra-semi -Wimplicit-fallthrough
-Wcovered-switch-default -Wno-noexcept-type -Wnon-virtual-dtor
-Wdelete-non-virtual-dtor -Wsuggest-override -Wstring-conversion
-Wno-pass-failed -Wmisleading-indentation -Wctad-maybe-unsupported
-fdiagnostics-color -ffunction-sections -fdata-sections -fno-common
-Woverloaded-virtual -Wno-nested-anon-types -O3 -DNDEBUG -std=c++17 -UNDEBUG
-fno-exceptions -funwind-tables -fno-rtti -MD -MT
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/Targets/NVPTX.cpp.o -MF
tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/Targets/NVPTX.cpp.o.d
-o tools/clang/lib/CIR/CodeGen/CMakeFiles/obj.clangCIR.dir/Targets/NVPTX.cpp.o
-c
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp:41:14:
error: member access into incomplete type 'CIRGenModule'
41 | if (cgm.getLangOpts().CUDA) {
| ^
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/../CIRGenTypes.h:46:7:
note: forward declaration of 'clang::CIRGen::CIRGenModule'
46 | class CIRGenModule;
| ^
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp:56:12:
error: member access into incomplete type 'CIRGenModule'
56 | if (cgm.getLangOpts().OpenCL || cgm.getLangOpts().CUDA) {
|^
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/../CIRGenTypes.h:46:7:
note: forward declaration of 'clang::CIRGen::CIRGenModule'
46 | class CIRGenModule;
| ^
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp:56:40:
error: member access into incomplete type 'CIRGenModule'
56 | if (cgm.getLangOpts().OpenCL || cgm.getLangOpts().CUDA) {
|^
/home/gha/actions-runner/_work/llvm-project/llvm-project/clang/lib/CIR/CodeGen/Targets/../CIRGenTypes.h:46:7:
note: forward declaration of 'clang::CIRGen::CIRGenModule'
46 | class CIRGenModule;
| ^
3 errors generated.
```
If these failures are unrelated to your changes (for example tests are broken
or flaky at HEAD), please open an issue at
https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.
https://github.com/llvm/llvm-project/pull/196079
___
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Men-cotton updated
https://github.com/llvm/llvm-project/pull/196079
>From a881019f9c4942ca96f0ea643bbc32586c8eb28a Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/7] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index fc939cd9605ab..a88f662e5a132 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -132,6 +132,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index ecdfb7cb42c0e..8c00ec186ef94 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -66,6 +66,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 4921dc6b7761c246230591c01a7cb42560d6922f Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/7] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From b64a002698c6dddb1fe0a34f56b2bdd5d1fa20fa Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/7] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/C
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Men-cotton wrote: @Siya-05 Sorry, I didn't resolve the merge conflict as you intended. I'll fix it soon. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff origin/main HEAD --extensions cpp,h --
clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
clang/include/clang/CIR/MissingFeatures.h clang/lib/CIR/CodeGen/CIRGenTypes.cpp
clang/lib/CIR/CodeGen/TargetInfo.cpp clang/lib/CIR/CodeGen/TargetInfo.h
--diff_from_common_commit
``
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
View the diff from clang-format here.
``diff
diff --git a/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
index 34ff4f138..cb27a2199 100644
--- a/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
+++ b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp
@@ -29,7 +29,7 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
-
+
void setTargetAttributes(const clang::Decl *decl, mlir::Operation *global,
CIRGenModule &cgm) const override {
auto globalValue = mlir::dyn_cast(global);
``
https://github.com/llvm/llvm-project/pull/196079
___
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Men-cotton updated
https://github.com/llvm/llvm-project/pull/196079
>From a881019f9c4942ca96f0ea643bbc32586c8eb28a Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/7] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index fc939cd9605ab..a88f662e5a132 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -132,6 +132,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index ecdfb7cb42c0e..8c00ec186ef94 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -66,6 +66,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 4921dc6b7761c246230591c01a7cb42560d6922f Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/7] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From b64a002698c6dddb1fe0a34f56b2bdd5d1fa20fa Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/7] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/C
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: @Men-cotton , I've pushed the updated branch. Could you please rerun the premerge checks when you have a chance? https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From a881019f9c4942ca96f0ea643bbc32586c8eb28a Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/7] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index fc939cd9605ab..a88f662e5a132 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -132,6 +132,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index ecdfb7cb42c0e..8c00ec186ef94 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -66,6 +66,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 4921dc6b7761c246230591c01a7cb42560d6922f Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/7] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From b64a002698c6dddb1fe0a34f56b2bdd5d1fa20fa Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/7] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/CIRG
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Men-cotton wrote: These APIs are already present on current main. See #189345 and #195382. It seems like the original branch point is older than them, so you might need to update your local environment. Could you update your local branch and rebuild ClangIR? If the errors still reproduce after that, please share the log. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: @Men-cotton I investigated the failures under clang/test/CIR/CodeGenCUDA/ and noticed they seem related to the NVPTX CIR target implementation rather than the CUDA surface type change itself. Originally, the NVPTX code lived in TargetInfo.cpp. After the review suggestion to move the NVPTX-specific implementation into Targets/NVPTX.cpp, I tried that refactor, but the build failed due to references to CIR APIs that don't appear to exist in the current tree (e.g. cir::CallingConv::PTXKernel, FuncOp::setCallingConv, MissingFeatures::emitNVVMMetadata, and MissingFeatures::handleCUDALaunchBoundsAttr). I then moved the implementation back into TargetInfo.cpp to verify whether this was a file-placement issue, but the same errors remained, Can you clarify what exactly is happening? https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Men-cotton wrote: You're right that we have `premerge_advisor_explain.py` timeout at the end of the log. However, before this, some tests under `clang/test/CIR/CodeGenCUDA/` already failed. Please fix these errors. https://github.com/user-attachments/assets/50aeb355-b5e1-49c5-83ea-2505feefa81e"; /> https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: > Windows failure is #202255. LLDB TestRunLocker.py failure is #193787. > > @Siya-05, could you fix the other failures > (https://github.com/llvm/llvm-project/actions/runs/27130502014?pr=196079) > please? I checked the remaining failures. Aside from the known Windows failure (#202255) and LLDB TestRunLocker.py failure (#193787), both Linux jobs fail in premerge_advisor_explain.py due to a premerge-advisor timeout (requests.exceptions.ReadTimeout), not during compilation or test execution. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Men-cotton wrote: Windows failure is #202255. LLDB TestRunLocker.py failure is #193787. @Siya-05, could you fix the other failures please? https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: This was moved to clang/lib/CIR/CodeGen/Targets/NVPTX.cpp per the earlier review feedback. The conflict resolution preserves that refactoring. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/6] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/6] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From 628756a8f56cd27f93c8b4dccfeb02ce6271a60b Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/6] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/CIRG
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Men-cotton wrote: > Are there any other changes? Please resolve the merge conflict. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: Are there any other changes? https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/6] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/6] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From 628756a8f56cd27f93c8b4dccfeb02ce6271a60b Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/6] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/CIRG
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -0,0 +1,25 @@ +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-CIR-LLVM %s +// RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-OGCG %s Men-cotton wrote: nit: Could we match the prefix order used by tests like `attribute-visibility.cu`? ```suggestion // RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=CIR-DEVICE %s // RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=LLVM-DEVICE %s // RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=OGCG-DEVICE %s ``` https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Men-cotton approved this pull request. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -0,0 +1,25 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck
--check-prefix=DEVICE-CIR-LLVM %s
+// RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda
-emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-OGCG %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+
+// CIR lowers poison to LLVM poison, while OG CodeGen emits undef.
+// DEVICE-CIR-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global
i64 poison
+// DEVICE-OGCG: @surf ={{.*}} addrspace(1) externally_initialized global i64
undef
Men-cotton wrote:
nit: please add a trailing newline.
```suggestion
// DEVICE-OGCG: @surf ={{.*}} addrspace(1) externally_initialized global i64
undef
```
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -0,0 +1,25 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck
--check-prefix=DEVICE-CIR-LLVM %s
+// RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda
-emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-OGCG %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+
+// CIR lowers poison to LLVM poison, while OG CodeGen emits undef.
RiverDave wrote:
Yeah, that was intentional. I recall It came from the incubator's push to stop
introducing undef where we don't really need it; see llvm/clangir#1712.
also, afaik, [undef seems to be mostly deprecated at least on LLVM
IR.](https://llvm.org/docs/UndefinedBehavior.html#undef-values) is this a
divergence we can live with?
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -132,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
RiverDave wrote:
Thanks! Yes, this diverged as I upstreamed almost verbatim the structure we had
in the incubator. Separate files should be the right convention for all targets
from now on.
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/koparasy commented: Sorry for being late on this. Overall this looks good to me. Some NITs. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: @koparasy and @andykaylor Please let me know if any further changes are needed. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -132,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
koparasy wrote:
I find the OG side comment more informative:
```
// On the device side, surface reference is represented as an object handle
// in 64-bit integer.
```
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -132,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
Siya-05 wrote:
Moved the NVPTX-specific CIR target implementation into `Targets/NVPTX.cpp`
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/4] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/4] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From 628756a8f56cd27f93c8b4dccfeb02ce6271a60b Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/4] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/CIRG
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/5] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/5] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
>From 628756a8f56cd27f93c8b4dccfeb02ce6271a60b Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Mon, 18 May 2026 07:55:35 +0400
Subject: [PATCH 3/5] [CIR][CUDA] Mark texture type as missing
---
clang/include/clang/CIR/MissingFeatures.h | 1 +
clang/lib/CIR/CodeGen/CIRG
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -0,0 +1,21 @@ +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s andykaylor wrote: ```suggestion // RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s ``` We like to have tests without CIR to compare the output. If the LLVM IR is the same with and without CIR, you can use the same check prefix as I've suggested here. Otherwise, use DEVICE-OGCG and add comments explaining any differences. https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
Siya-05 wrote:
Thanks for the review!
Added an explicit `MissingFeatures` assert for CUDA texture types in the
device-side lowering path.
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/andykaylor edited https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
Siya-05 wrote: Hi @andykaylor , just following up on this PR whenever you have time. I’d appreciate any feedback or review. Thanks! https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 updated
https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH 1/2] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
>From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Fri, 8 May 2026 14:12:08 +0400
Subject: [PATCH 2/2] [CIR][CUDA] Add trailing newline to surface test
---
clang/test/CIR/CodeGenCUDA/surface.cu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
index d28f876080180..6044d63f85dd3 100644
--- a/clang/test/CIR/CodeGenCUDA/surface.cu
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type))
surface
surface surf;
// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
-// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
AbdallahRashed wrote:
file seems to be missing trailing newline.
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
llvmorg-github-actions[bot] wrote:
@llvm/pr-subscribers-clangir
Author: Orphic Dreamer (Siya-05)
Changes
Related: #179278
This patch adds initial support for CUDA built-in surface types in CIR for
device-side compilation.
CUDA surface references are lowered to the NVPTX device-handle representation
(`i64`), matching existing Clang CodeGen behavior.
Changes
* Add `getCUDADeviceBuiltinSurfaceDeviceType()` target hook to
`TargetCIRGenInfo`
* Implement NVPTX surface lowering in `NVPTXTargetCIRGenInfo`
* Handle CUDA built-in surface types in `CIRGenTypes::convertType`
* Add CIR CUDA test coverage for device-side surface lowering
Notes
* This patch only implements device-side surface type lowering support
* Texture types remain unsupported
* TBAA handling for surface/texture types is left for follow-up work
---
Full diff: https://github.com/llvm/llvm-project/pull/196079.diff
4 Files Affected:
- (modified) clang/lib/CIR/CodeGen/CIRGenTypes.cpp (+8)
- (modified) clang/lib/CIR/CodeGen/TargetInfo.cpp (+6)
- (modified) clang/lib/CIR/CodeGen/TargetInfo.h (+4)
- (added) clang/test/CIR/CodeGenCUDA/surface.cu (+21)
``diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
``
https://github.com/llvm/llvm-project/pull/196079
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[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
github-actions[bot] wrote: Thank you for submitting a Pull Request (PR) to the LLVM Project! This PR will be automatically labeled and the relevant teams will be notified. If you wish to, you can add reviewers by using the "Reviewers" section on this page. If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using `@` followed by their GitHub username. If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers. If you have further questions, they may be answered by the [LLVM GitHub User Guide](https://llvm.org/docs/GitHub.html). You can also ask questions in a comment on this PR, on the [LLVM Discord](https://discord.com/invite/xS7Z362) or on the [forums](https://discourse.llvm.org/). https://github.com/llvm/llvm-project/pull/196079 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR][CUDA] Support built-in CUDA surface type (PR #196079)
https://github.com/Siya-05 created
https://github.com/llvm/llvm-project/pull/196079
Related: #179278
This patch adds initial support for CUDA built-in surface types in CIR for
device-side compilation.
CUDA surface references are lowered to the NVPTX device-handle representation
(`i64`), matching existing Clang CodeGen behavior.
Changes
* Add `getCUDADeviceBuiltinSurfaceDeviceType()` target hook to
`TargetCIRGenInfo`
* Implement NVPTX surface lowering in `NVPTXTargetCIRGenInfo`
* Handle CUDA built-in surface types in `CIRGenTypes::convertType`
* Add CIR CUDA test coverage for device-side surface lowering
Notes
* This patch only implements device-side surface type lowering support
* Texture types remain unsupported
* TBAA handling for surface/texture types is left for follow-up work
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001
From: Sivapriya Venkateswarar
Date: Wed, 6 May 2026 17:36:31 +0400
Subject: [PATCH] [CIR][CUDA] Support built-in CUDA surface type
---
clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8
clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++
clang/lib/CIR/CodeGen/TargetInfo.h| 4
clang/test/CIR/CodeGenCUDA/surface.cu | 21 +
4 files changed, 39 insertions(+)
create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu
diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
index 85b7e854abb7f..308e1b44a6352 100644
--- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp
@@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
type = astContext.getCanonicalType(type);
const Type *ty = type.getTypePtr();
+ if (astContext.getLangOpts().CUDAIsDevice) {
+if (type->isCUDADeviceBuiltinSurfaceType()) {
+ if (mlir::Type ty =
+
cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType())
+return ty;
+}
+ }
+
// Process record types before the type cache lookup.
if (const auto *recordType = dyn_cast(type))
return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf());
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp
b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index f674299168960..658e46a2a9e4f 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo {
public:
NVPTXTargetCIRGenInfo(CIRGenTypes &cgt)
: TargetCIRGenInfo(std::make_unique(cgt)) {}
+
+ mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override {
+// CUDA surface is represented as a 64-bit handle on device
+return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64,
+ /*isSigned=*/true);
+ }
};
} // namespace
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h
b/clang/lib/CIR/CodeGen/TargetInfo.h
index 5e0103093827b..f64305df5bccf 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -63,6 +63,10 @@ class TargetCIRGenInfo {
cir::LangAddressSpace::Default);
}
+ virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const {
+return nullptr;
+ }
+
/// Determine whether a call to an unprototyped functions under
/// the given calling convention should use the variadic
/// convention or the non-variadic convention.
diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu
b/clang/test/CIR/CodeGenCUDA/surface.cu
new file mode 100644
index 0..d28f876080180
--- /dev/null
+++ b/clang/test/CIR/CodeGenCUDA/surface.cu
@@ -0,0 +1,21 @@
+// REQUIRES: x86-registered-target
+// REQUIRES: nvptx-registered-target
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s
+// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple
nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s
+
+struct surfaceReference {
+ int desc;
+};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+template
+struct __attribute__((device_builtin_surface_type)) surface
+: public surfaceReference {};
+
+surface surf;
+
+// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison
: !s64i
+// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64
poison
\ No newline at end of file
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