[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-18 Thread Amr Hesham via cfe-commits 

https://github.com/AmrDeveloper closed 
https://github.com/llvm/llvm-project/pull/139444
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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-15 Thread Amr Hesham via cfe-commits 

https://github.com/AmrDeveloper updated 
https://github.com/llvm/llvm-project/pull/139444

>From 46d3b466df954eee87a5e5e7df5cb03802d468c7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper 
Date: Sat, 10 May 2025 20:37:05 +0200
Subject: [PATCH 1/2] [CIR] Upstream unary operators for VectorType

---
 .../CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 48 +++-
 clang/test/CIR/CodeGen/vector-ext.cpp | 57 +++
 clang/test/CIR/CodeGen/vector.cpp | 57 +++
 3 files changed, 148 insertions(+), 14 deletions(-)

diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp 
b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
index a1066cfe67ef9..dc632867d863c 100644
--- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
+++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -1043,12 +1043,11 @@ mlir::LogicalResult 
CIRToLLVMUnaryOpLowering::matchAndRewrite(
 mlir::ConversionPatternRewriter &rewriter) const {
   assert(op.getType() == op.getInput().getType() &&
  "Unary operation's operand type and result type are different");
-  mlir::Type type = op.getType();
-  mlir::Type elementType = type;
-  bool isVector = false;
-  assert(!cir::MissingFeatures::vectorType());
-  mlir::Type llvmType = getTypeConverter()->convertType(type);
-  mlir::Location loc = op.getLoc();
+  const mlir::Type type = op.getType();
+  const mlir::Type elementType = elementTypeIfVector(type);
+  const bool isVector = mlir::isa(type);
+  const mlir::Type llvmType = getTypeConverter()->convertType(type);
+  const mlir::Location loc = op.getLoc();
 
   // Integer unary operations: + - ~ ++ --
   if (mlir::isa(elementType)) {
@@ -1076,20 +1075,41 @@ mlir::LogicalResult 
CIRToLLVMUnaryOpLowering::matchAndRewrite(
   rewriter.replaceOp(op, adaptor.getInput());
   return mlir::success();
 case cir::UnaryOpKind::Minus: {
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp zero = rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
+  mlir::Value zero;
+  if (isVector)
+zero = rewriter.create(loc, llvmType);
+  else
+zero = rewriter.create(
+loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
   rewriter.replaceOpWithNewOp(
   op, llvmType, zero, adaptor.getInput(), maybeNSW);
   return mlir::success();
 }
 case cir::UnaryOpKind::Not: {
   // bit-wise compliment operator, implemented as an XOR with -1.
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp minusOne = 
rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, -1));
+  mlir::Value minusOne;
+  if (isVector) {
+// Creating a vector object with all -1 values is easier said than
+// done. It requires a series of insertelement ops.
+const mlir::Type llvmElementType =
+getTypeConverter()->convertType(elementType);
+const mlir::Value minusOneInt = 
rewriter.create(
+loc, llvmElementType, mlir::IntegerAttr::get(llvmElementType, -1));
+minusOne = rewriter.create(loc, llvmType);
+
+const uint64_t numElements =
+mlir::dyn_cast(type).getSize();
+for (uint64_t i = 0; i < numElements; ++i) {
+  const mlir::Value indexValue =
+  rewriter.create(loc,
+  rewriter.getI64Type(), 
i);
+  minusOne = rewriter.create(
+  loc, minusOne, minusOneInt, indexValue);
+}
+  } else {
+minusOne = rewriter.create(
+loc, llvmType, mlir::IntegerAttr::get(llvmType, -1));
+  }
   rewriter.replaceOpWithNewOp(
   op, llvmType, adaptor.getInput(), minusOne);
   return mlir::success();
diff --git a/clang/test/CIR/CodeGen/vector-ext.cpp 
b/clang/test/CIR/CodeGen/vector-ext.cpp
index a16ef42f113df..504a13d9bb237 100644
--- a/clang/test/CIR/CodeGen/vector-ext.cpp
+++ b/clang/test/CIR/CodeGen/vector-ext.cpp
@@ -337,6 +337,63 @@ void foo7() {
 // OGCG: %[[NEW_VEC:.*]] = insertelement <4 x i32> %[[TMP2]], i32 %[[RES]], 
i32 2
 // OGCG: store <4 x i32> %[[NEW_VEC]], ptr %[[VEC]], align 16
 
+
+void foo8() {
+  vi4 a = { 1, 2, 3, 4 };
+  vi4 plus_res = +a;
+  vi4 minus_res = -a;
+  vi4 not_res = ~a;
+}
+
+// CIR: %[[VEC:.*]] = cir.alloca !cir.vector<4 x !s32i>, 
!cir.ptr>, ["a", init]
+// CIR: %[[PLUS_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, 
!cir.ptr>, ["plus_res", init]
+// CIR: %[[MINUS_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, 
!cir.ptr>, ["minus_res", init]
+// CIR: %[[NOT_RES:.*]] = cir.alloca !cir.vector<4 x !s32i>, 
!cir.ptr>, ["not_res", init]
+// CIR: %[[CONST_1:.*]] = cir.const #cir.int<1> : !s32i
+// CIR: %[[CONST_2:.*]] = cir.const #cir.int<2> : !s32i
+// CIR: %[[CONST_3:.*]] = cir.const #cir.int<3> : !s32i
+// CIR: %[[CONST_4:

[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-15 Thread Amr Hesham via cfe-commits 


@@ -1076,20 +1074,41 @@ mlir::LogicalResult 
CIRToLLVMUnaryOpLowering::matchAndRewrite(
   rewriter.replaceOp(op, adaptor.getInput());
   return mlir::success();
 case cir::UnaryOpKind::Minus: {
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp zero = rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
+  mlir::Value zero;
+  if (isVector)
+zero = rewriter.create(loc, llvmType);
+  else
+zero = rewriter.create(
+loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
   rewriter.replaceOpWithNewOp(
   op, llvmType, zero, adaptor.getInput(), maybeNSW);
   return mlir::success();
 }
 case cir::UnaryOpKind::Not: {
   // bit-wise compliment operator, implemented as an XOR with -1.
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp minusOne = 
rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, -1));
+  mlir::Value minusOne;
+  if (isVector) {
+// Creating a vector object with all -1 values is easier said than
+// done. It requires a series of insertelement ops.

AmrDeveloper wrote:

I think yes we can, i will try it

https://github.com/llvm/llvm-project/pull/139444
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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-15 Thread Andy Kaylor via cfe-commits 


@@ -1076,20 +1074,41 @@ mlir::LogicalResult 
CIRToLLVMUnaryOpLowering::matchAndRewrite(
   rewriter.replaceOp(op, adaptor.getInput());
   return mlir::success();
 case cir::UnaryOpKind::Minus: {
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp zero = rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
+  mlir::Value zero;
+  if (isVector)
+zero = rewriter.create(loc, llvmType);
+  else
+zero = rewriter.create(
+loc, llvmType, mlir::IntegerAttr::get(llvmType, 0));
   rewriter.replaceOpWithNewOp(
   op, llvmType, zero, adaptor.getInput(), maybeNSW);
   return mlir::success();
 }
 case cir::UnaryOpKind::Not: {
   // bit-wise compliment operator, implemented as an XOR with -1.
-  assert(!isVector &&
- "Add vector handling when vector types are supported");
-  mlir::LLVM::ConstantOp minusOne = 
rewriter.create(
-  loc, llvmType, mlir::IntegerAttr::get(llvmType, -1));
+  mlir::Value minusOne;
+  if (isVector) {
+// Creating a vector object with all -1 values is easier said than
+// done. It requires a series of insertelement ops.

andykaylor wrote:

Why can we create something like `llvm.mlir.constant(dense<-1> : vector<4xi32>) 
: vector<4xi32>`?

https://github.com/llvm/llvm-project/pull/139444
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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-15 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor edited 
https://github.com/llvm/llvm-project/pull/139444
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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-15 Thread Andy Kaylor via cfe-commits 

https://github.com/andykaylor approved this pull request.

This looks OK, but I have a question about vector splat.

https://github.com/llvm/llvm-project/pull/139444
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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-13 Thread Amr Hesham via cfe-commits 

https://github.com/AmrDeveloper updated 
https://github.com/llvm/llvm-project/pull/139444



  



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[clang] [CIR][LLVMLowering] Upstream unary operators for VectorType (PR #139444)

2025-05-13 Thread Bruno Cardoso Lopes via cfe-commits 

https://github.com/bcardosolopes edited 
https://github.com/llvm/llvm-project/pull/139444
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