[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-09 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm closed 
https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-08 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm updated 
https://github.com/llvm/llvm-project/pull/147086

>From 4efe257b27e6a76740a425ca93dd35cfac38919b Mon Sep 17 00:00:00 2001
From: Paul Walker 
Date: Thu, 26 Jun 2025 17:28:11 +0100
Subject: [PATCH] [Clang][AArch64] Fix feature guards for SVE2p1 builtins
 available in SME{2}.

Builtins that are enabled via +sve2p1 in non-streaming mode and
+sme{2} in streaming mode should also be enabled via +sve+sme{2} in
non-stremaing mode and +sme+sve2p1 in streaming mode.
---
 clang/include/clang/Basic/arm_sve.td  | 25 ++-
 .../AArch64/sve2-intrinsics/acle_sve2_revd.c  | 10 +---
 .../sve2p1-intrinsics/acle_sve2p1_bfmlsl.c|  6 -
 .../acle_sve2p1_create2_bool.c|  8 +-
 .../acle_sve2p1_create4_bool.c|  8 +-
 .../sve2p1-intrinsics/acle_sve2p1_dot.c   |  6 -
 .../sve2p1-intrinsics/acle_sve2p1_fclamp.c| 10 +++-
 .../sve2p1-intrinsics/acle_sve2p1_get2_bool.c |  8 +-
 .../sve2p1-intrinsics/acle_sve2p1_get4_bool.c |  8 +-
 .../sve2p1-intrinsics/acle_sve2p1_psel.c  | 10 
 .../sve2p1-intrinsics/acle_sve2p1_qcvtn.c |  8 --
 .../sve2p1-intrinsics/acle_sve2p1_qrshr.c |  8 --
 .../sve2p1-intrinsics/acle_sve2p1_sclamp.c| 12 ++---
 .../sve2p1-intrinsics/acle_sve2p1_set2_bool.c |  8 +-
 .../sve2p1-intrinsics/acle_sve2p1_set4_bool.c |  8 +-
 .../sve2p1-intrinsics/acle_sve2p1_uclamp.c| 12 ++---
 .../acle_sve2p1_undef_bool.c  |  6 -
 .../sve2p1-intrinsics/acle_sve2p1_while_x2.c  |  6 -
 ...reaming-sme-or-nonstreaming-sve-builtins.c | 25 +--
 19 files changed, 136 insertions(+), 56 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 7c0e5e7310527..ac6f89f9afdbc 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1325,7 +1325,7 @@ def SVCREATE_3_BF16 : SInst<"svcreate3[_{d}]", "3ddd",  
"b", MergeNone, "", [IsT
 def SVCREATE_4_BF16 : SInst<"svcreate4[_{d}]", "4", "b", MergeNone, "", 
[IsTupleCreate, VerifyRuntimeMode]>;
 }
 
-let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in {
+let SVETargetGuard = "sve2p1|sme2", SMETargetGuard = "sve2p1|sme2" in {
   def SVCREATE_2_B : SInst<"svcreate2[_b]", "2dd",   "Pc", MergeNone, "", 
[IsTupleCreate, VerifyRuntimeMode]>;
   def SVCREATE_4_B : SInst<"svcreate4[_b]", "4", "Pc", MergeNone, "", 
[IsTupleCreate, VerifyRuntimeMode]>;
 }
@@ -1350,18 +1350,17 @@ def SVSET_3_BF16 : SInst<"svset3[_{d}]", "33id", "b", 
MergeNone, "", [IsTupleSet
 def SVSET_4_BF16 : SInst<"svset4[_{d}]", "44id", "b", MergeNone, "", 
[IsTupleSet, VerifyRuntimeMode], [ImmCheck<1, ImmCheck0_3>]>;
 }
 
-let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in {
+let SVETargetGuard = "sve2p1|sme2", SMETargetGuard = "sve2p1|sme2" in {
   def SVGET_2_B : SInst<"svget2[_b]", "d2i", "Pc", MergeNone, "", [IsTupleGet, 
VerifyRuntimeMode], [ImmCheck<1, ImmCheck0_1>]>;
   def SVGET_4_B : SInst<"svget4[_b]", "d4i", "Pc", MergeNone, "", [IsTupleGet, 
VerifyRuntimeMode], [ImmCheck<1, ImmCheck0_3>]>;
 
   def SVSET_2_B : SInst<"svset2[_b]", "22id", "Pc", MergeNone, "", 
[IsTupleSet, VerifyRuntimeMode], [ImmCheck<1, ImmCheck0_1>]>;
   def SVSET_4_B : SInst<"svset4[_b]", "44id", "Pc", MergeNone, "", 
[IsTupleSet, VerifyRuntimeMode], [ImmCheck<1, ImmCheck0_3>]>;
-}
 
-let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2" in {
   def SVUNDEF_2_B: Inst<"svundef2_b", "2", "Pc", MergeNone, "", [IsUndef, 
VerifyRuntimeMode], []>;
   def SVUNDEF_4_B: Inst<"svundef4_b", "4", "Pc", MergeNone, "", [IsUndef, 
VerifyRuntimeMode], []>;
 }
+
 

 // SVE2 WhileGE/GT
 let SVETargetGuard = "sve2", SMETargetGuard = "sme" in {
@@ -1375,7 +1374,7 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm", 
"PcPsPiPl", MergeNone, "
 def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PcPsPiPl", MergeNone, 
"aarch64_sve_whilehs", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
 }
 
-let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2"  in {
+let SVETargetGuard = "sve2p1|sme2", SMETargetGuard = "sve2p1|sme2" in {
   def SVWHILEGE_S64_X2 : SInst<"svwhilege_{d}[_{1}]_x2", "2ll", "PcPsPiPl",
 MergeNone, "aarch64_sve_whilege_x2", [VerifyRuntimeMode]>;
   def SVWHILEGT_S64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2ll", "PcPsPiPl",
 MergeNone, "aarch64_sve_whilegt_x2", [VerifyRuntimeMode]>;
   def SVWHILEHI_U64_X2 : SInst<"svwhilegt_{d}[_{1}]_x2", "2nn", "PcPsPiPl",
 MergeNone, "aarch64_sve_whilehi_x2", [VerifyRuntimeMode]>;
@@ -1384,7 +1383,6 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2"  
in {
   def SVWHILELT_S64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2ll", "PcPsPiPl",
 MergeNone, "aarch64_sve_whilelt_x2", [VerifyRuntimeMode]>;
   def SVWHILELO_U64_X2 : SInst<"svwhilelt_{d}[_{1}]_x2", "2nn", "PcPsPiPl",
 MergeNone

[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-08 Thread Kerry McLaughlin via cfe-commits 

https://github.com/kmclaughlin-arm approved this pull request.


https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-08 Thread Kerry McLaughlin via cfe-commits 


@@ -569,34 +569,39 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
   // * When compiling for SVE only, the caller must be in non-streaming mode.
   // * When compiling for both SVE and SME, the caller can be in either mode.
   if (BuiltinType == SemaARM::VerifyRuntimeMode) {
-llvm::StringMap CallerFeatureMapWithoutSVE;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSVE, FD);
-CallerFeatureMapWithoutSVE["sve"] = false;
+llvm::StringMap CallerFeatures;
+S.Context.getFunctionFeatureMap(CallerFeatures, FD);
 
 // Avoid emitting diagnostics for a function that can never compile.
-if (FnType == SemaARM::ArmStreaming && !CallerFeatureMapWithoutSVE["sme"])
+if (FnType == SemaARM::ArmStreaming && !CallerFeatures["sme"])
   return false;
 
-llvm::StringMap CallerFeatureMapWithoutSME;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSME, FD);
-CallerFeatureMapWithoutSME["sme"] = false;
+const auto FindTopLevelPipe = [](const char *S) {
+  unsigned Depth = 0;
+  unsigned I = 0, E = strlen(S);
+  for (; I < E; ++I) {
+if (S[I] == '|' && Depth == 0)
+  break;
+if (S[I] == '(')
+  ++Depth;
+else if (S[I] == ')')
+  --Depth;
+  }
+  return I;
+};
+
+const char *RequiredFeatures =
+S.Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
+unsigned PipeIdx = FindTopLevelPipe(RequiredFeatures);
+assert(PipeIdx != 0 && PipeIdx != strlen(RequiredFeatures) &&
+   "Expected feature string of the form 'SVE-EXPR|SME-EXPR'");
+StringRef NonStreamingBuiltinGuard = StringRef(RequiredFeatures, PipeIdx);
+StringRef StreamingBuiltinGuard = StringRef(RequiredFeatures + PipeIdx + 
1);

kmclaughlin-arm wrote:

My mistake, I was only considering the simpler cases such as `sve2p1|sme2` so I 
don't think regex is going to help here. I've approved the other patch which 
added these changes :)

https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-07 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm edited 
https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-07 Thread Paul Walker via cfe-commits 


@@ -569,34 +569,39 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
   // * When compiling for SVE only, the caller must be in non-streaming mode.
   // * When compiling for both SVE and SME, the caller can be in either mode.
   if (BuiltinType == SemaARM::VerifyRuntimeMode) {
-llvm::StringMap CallerFeatureMapWithoutSVE;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSVE, FD);
-CallerFeatureMapWithoutSVE["sve"] = false;
+llvm::StringMap CallerFeatures;
+S.Context.getFunctionFeatureMap(CallerFeatures, FD);
 
 // Avoid emitting diagnostics for a function that can never compile.
-if (FnType == SemaARM::ArmStreaming && !CallerFeatureMapWithoutSVE["sme"])
+if (FnType == SemaARM::ArmStreaming && !CallerFeatures["sme"])
   return false;
 
-llvm::StringMap CallerFeatureMapWithoutSME;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSME, FD);
-CallerFeatureMapWithoutSME["sme"] = false;
+const auto FindTopLevelPipe = [](const char *S) {
+  unsigned Depth = 0;
+  unsigned I = 0, E = strlen(S);
+  for (; I < E; ++I) {
+if (S[I] == '|' && Depth == 0)
+  break;
+if (S[I] == '(')
+  ++Depth;
+else if (S[I] == ')')
+  --Depth;
+  }
+  return I;
+};
+
+const char *RequiredFeatures =
+S.Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
+unsigned PipeIdx = FindTopLevelPipe(RequiredFeatures);
+assert(PipeIdx != 0 && PipeIdx != strlen(RequiredFeatures) &&
+   "Expected feature string of the form 'SVE-EXPR|SME-EXPR'");
+StringRef NonStreamingBuiltinGuard = StringRef(RequiredFeatures, PipeIdx);
+StringRef StreamingBuiltinGuard = StringRef(RequiredFeatures + PipeIdx + 
1);

paulwalker-arm wrote:

This code comes from https://github.com/llvm/llvm-project/pull/145941, which 
I've now added you to.

I'm not too familiar with `std::regex` so please forgive my ignorance but it 
seems to only support simple cases and specifically cannot handle nested 
brackets?  The example given would fail when supplied with 
`sve(sve2|sve-hh)|sme(sve2|sme2)`?

https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-07 Thread Kerry McLaughlin via cfe-commits 


@@ -569,34 +569,39 @@ static bool checkArmStreamingBuiltin(Sema &S, CallExpr 
*TheCall,
   // * When compiling for SVE only, the caller must be in non-streaming mode.
   // * When compiling for both SVE and SME, the caller can be in either mode.
   if (BuiltinType == SemaARM::VerifyRuntimeMode) {
-llvm::StringMap CallerFeatureMapWithoutSVE;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSVE, FD);
-CallerFeatureMapWithoutSVE["sve"] = false;
+llvm::StringMap CallerFeatures;
+S.Context.getFunctionFeatureMap(CallerFeatures, FD);
 
 // Avoid emitting diagnostics for a function that can never compile.
-if (FnType == SemaARM::ArmStreaming && !CallerFeatureMapWithoutSVE["sme"])
+if (FnType == SemaARM::ArmStreaming && !CallerFeatures["sme"])
   return false;
 
-llvm::StringMap CallerFeatureMapWithoutSME;
-S.Context.getFunctionFeatureMap(CallerFeatureMapWithoutSME, FD);
-CallerFeatureMapWithoutSME["sme"] = false;
+const auto FindTopLevelPipe = [](const char *S) {
+  unsigned Depth = 0;
+  unsigned I = 0, E = strlen(S);
+  for (; I < E; ++I) {
+if (S[I] == '|' && Depth == 0)
+  break;
+if (S[I] == '(')
+  ++Depth;
+else if (S[I] == ')')
+  --Depth;
+  }
+  return I;
+};
+
+const char *RequiredFeatures =
+S.Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
+unsigned PipeIdx = FindTopLevelPipe(RequiredFeatures);
+assert(PipeIdx != 0 && PipeIdx != strlen(RequiredFeatures) &&
+   "Expected feature string of the form 'SVE-EXPR|SME-EXPR'");
+StringRef NonStreamingBuiltinGuard = StringRef(RequiredFeatures, PipeIdx);
+StringRef StreamingBuiltinGuard = StringRef(RequiredFeatures + PipeIdx + 
1);

kmclaughlin-arm wrote:

I'm not sure if this is going to change in one of the future patches, but could 
something like this work here instead?
```
std::string RequiredFeatures =
str(S.Context.BuiltinInfo.getRequiredFeatures(BuiltinID));
std::smatch match;
if (std::regex_match(str, match, std::regex("(s[^|]+)\\|(s.+)"))) {
  NonStreamingBuiltinGuard = StringRef(match[1].str());
  StreamingBuiltinGuard = StringRef(match[2].str());
}
```

https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-07 Thread Jonathan Thackray via cfe-commits 

https://github.com/jthackray approved this pull request.

Looks good.

https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm edited 
https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm edited 
https://github.com/llvm/llvm-project/pull/147086
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[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Paul Walker (paulwalker-arm)


Changes

Builtins that are enabled via +sve2p1 in non-streaming mode and +sme{2} in 
streaming mode should also be enabled via +sve+sme{2} in non-streaming mode and 
+sme+sve2p1 in streaming mode.

---

Patch is 55.40 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/147086.diff


21 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+31-30) 
- (modified) clang/lib/Sema/SemaARM.cpp (+26-21) 
- (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c (+7-3) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c 
(+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c 
(+5-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c 
(+9-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_psel.c 
(+5-5) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (+5-1) 
- (modified) 
clang/test/Sema/aarch64-streaming-sme-or-nonstreaming-sve-builtins.c (+12-13) 
- (modified) clang/utils/TableGen/SveEmitter.cpp (+3) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 76fd072a41d8b..ac6f89f9afdbc 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
   def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc",  "b", MergeNone, 
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
 }
 
-multiclass StructLoad {
-  def : SInst;
+multiclass StructLoad f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 
 // Load N-element structure into N vectors (scalar base)
-defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret">;
-defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret">;
-defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret">;
+defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret", 
[VerifyRuntimeMode]>;
+defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret", 
[VerifyRuntimeMode]>;
+defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret", 
[VerifyRuntimeMode]>;
 
 // Load N-element structure into N vectors (scalar base, VL displacement)
-defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret">;
-defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret">;
-defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret">;
+defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret", [VerifyRuntimeMode]>;
+defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret", [VerifyRuntimeMode]>;
+defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret", [VerifyRuntimeMode]>;
 
 // Load one octoword and replicate (scalar base)
 let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in {
@@ -434,21 +434,21 @@ def SVST1H_SCATTER_INDEX_S: 
MInst<"svst1h_scatter[_{2}base]_index[_{d}]", "v
 def SVST1W_SCATTER_INDEX_S: MInst<"svst1w_scatter[_{2}base]_index[_{d}]", 
"vPuld", "lUl",  [IsScatterStore], MemEltTyInt32,   
"aarch64_sve_st1_scatter_scalar_offset">;
 } // let SVETargetGuard = "sve"
 
-multiclass StructStore {
-  def : SInst;
+multiclass StructStore f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 // Store N vectors into N-element structure (scalar base)
-defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2">;
-defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3">;
-defm SVST4 : StructStore<"svst4[_{d}]", "vPp4", "aarch64_sve_st4">;
+defm SVST2 : StructStore<"svst2[_{d}]", "vPp

[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-arm

Author: Paul Walker (paulwalker-arm)


Changes

Builtins that are enabled via +sve2p1 in non-streaming mode and +sme{2} in 
streaming mode should also be enabled via +sve+sme{2} in non-streaming mode and 
+sme+sve2p1 in streaming mode.

---

Patch is 55.40 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/147086.diff


21 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+31-30) 
- (modified) clang/lib/Sema/SemaARM.cpp (+26-21) 
- (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c (+7-3) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c 
(+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c 
(+5-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c 
(+9-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_psel.c 
(+5-5) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (+5-1) 
- (modified) 
clang/test/Sema/aarch64-streaming-sme-or-nonstreaming-sve-builtins.c (+12-13) 
- (modified) clang/utils/TableGen/SveEmitter.cpp (+3) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 76fd072a41d8b..ac6f89f9afdbc 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
   def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc",  "b", MergeNone, 
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
 }
 
-multiclass StructLoad {
-  def : SInst;
+multiclass StructLoad f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 
 // Load N-element structure into N vectors (scalar base)
-defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret">;
-defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret">;
-defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret">;
+defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret", 
[VerifyRuntimeMode]>;
+defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret", 
[VerifyRuntimeMode]>;
+defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret", 
[VerifyRuntimeMode]>;
 
 // Load N-element structure into N vectors (scalar base, VL displacement)
-defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret">;
-defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret">;
-defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret">;
+defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret", [VerifyRuntimeMode]>;
+defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret", [VerifyRuntimeMode]>;
+defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret", [VerifyRuntimeMode]>;
 
 // Load one octoword and replicate (scalar base)
 let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in {
@@ -434,21 +434,21 @@ def SVST1H_SCATTER_INDEX_S: 
MInst<"svst1h_scatter[_{2}base]_index[_{d}]", "v
 def SVST1W_SCATTER_INDEX_S: MInst<"svst1w_scatter[_{2}base]_index[_{d}]", 
"vPuld", "lUl",  [IsScatterStore], MemEltTyInt32,   
"aarch64_sve_st1_scatter_scalar_offset">;
 } // let SVETargetGuard = "sve"
 
-multiclass StructStore {
-  def : SInst;
+multiclass StructStore f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 // Store N vectors into N-element structure (scalar base)
-defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2">;
-defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3">;
-defm SVST4 : StructStore<"svst4[_{d}]", "vPp4", "aarch64_sve_st4">;
+defm SVST2 : StructStore<"svst2[_{d}]"

[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-aarch64

Author: Paul Walker (paulwalker-arm)


Changes

Builtins that are enabled via +sve2p1 in non-streaming mode and +sme{2} in 
streaming mode should also be enabled via +sve+sme{2} in non-streaming mode and 
+sme+sve2p1 in streaming mode.

---

Patch is 55.40 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/147086.diff


21 Files Affected:

- (modified) clang/include/clang/Basic/arm_sve.td (+31-30) 
- (modified) clang/lib/Sema/SemaARM.cpp (+26-21) 
- (modified) clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_revd.c (+7-3) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_bfmlsl.c 
(+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_create4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_dot.c 
(+5-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_fclamp.c 
(+9-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_get4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_psel.c 
(+5-5) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qcvtn.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_qrshr.c 
(+6-2) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_sclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set2_bool.c (+7-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_set4_bool.c (+7-1) 
- (modified) clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_uclamp.c 
(+8-4) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_undef_bool.c (+5-1) 
- (modified) 
clang/test/CodeGen/AArch64/sve2p1-intrinsics/acle_sve2p1_while_x2.c (+5-1) 
- (modified) 
clang/test/Sema/aarch64-streaming-sme-or-nonstreaming-sve-builtins.c (+12-13) 
- (modified) clang/utils/TableGen/SveEmitter.cpp (+3) 


``diff
diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 76fd072a41d8b..ac6f89f9afdbc 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
   def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc",  "b", MergeNone, 
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
 }
 
-multiclass StructLoad {
-  def : SInst;
+multiclass StructLoad f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 
 // Load N-element structure into N vectors (scalar base)
-defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret">;
-defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret">;
-defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret">;
+defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret", 
[VerifyRuntimeMode]>;
+defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret", 
[VerifyRuntimeMode]>;
+defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret", 
[VerifyRuntimeMode]>;
 
 // Load N-element structure into N vectors (scalar base, VL displacement)
-defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret">;
-defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret">;
-defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret">;
+defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret", [VerifyRuntimeMode]>;
+defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret", [VerifyRuntimeMode]>;
+defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret", [VerifyRuntimeMode]>;
 
 // Load one octoword and replicate (scalar base)
 let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in {
@@ -434,21 +434,21 @@ def SVST1H_SCATTER_INDEX_S: 
MInst<"svst1h_scatter[_{2}base]_index[_{d}]", "v
 def SVST1W_SCATTER_INDEX_S: MInst<"svst1w_scatter[_{2}base]_index[_{d}]", 
"vPuld", "lUl",  [IsScatterStore], MemEltTyInt32,   
"aarch64_sve_st1_scatter_scalar_offset">;
 } // let SVETargetGuard = "sve"
 
-multiclass StructStore {
-  def : SInst;
+multiclass StructStore f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 // Store N vectors into N-element structure (scalar base)
-defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2">;
-defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3">;
-defm SVST4 : StructStore<"svst4[_{d}]", "vPp4", "aarch64_sve_st4">;
+defm SVST2 : StructStore<"svst2[_{

[clang] [Clang][AArch64] Fix feature guards for SVE2p1 builtins available in SME{2}. (PR #147086)

2025-07-04 Thread Paul Walker via cfe-commits 

https://github.com/paulwalker-arm created 
https://github.com/llvm/llvm-project/pull/147086

Builtins that are enabled via +sve2p1 in non-streaming mode and +sme{2} in 
streaming mode should also be enabled via +sve+sme{2} in non-streaming mode and 
+sme+sve2p1 in streaming mode.

>From ac5fe906926e6016497fcd923d2253fd83eb8733 Mon Sep 17 00:00:00 2001
From: Paul Walker 
Date: Thu, 26 Jun 2025 17:28:11 +0100
Subject: [PATCH 1/2] [Clang][SME] Refactor checkArmStreamingBuiltin.

Rather than filtering the calling function's features the PR splits
the builtin guard into distinct non-streaming and streaming guards
that are compared to the active features in full.

This has no affect on the current builtin definitions[1] but will
allow us in the future to reference SVE features within streaming
builtin guards and SME features within non-streaming builtin guards.

[1] The change uncovered an issue whereby a couple of builtins where
tagged with VerifyRuntimeMode but did not include both streaming and
non-streaming guards. Some of those builtins are available in SME2p1
but to keep the PR mostly NFC I've ensured they are only available in
non-streaming mode, thus matching the existing implementation.
---
 clang/include/clang/Basic/arm_sve.td | 36 ++---
 clang/lib/Sema/SemaARM.cpp   | 47 +++-
 clang/utils/TableGen/SveEmitter.cpp  |  3 ++
 3 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index 76fd072a41d8b..7c0e5e7310527 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -264,22 +264,22 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
   def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc",  "b", MergeNone, 
"aarch64_sve_ld1rq", [VerifyRuntimeMode]>;
 }
 
-multiclass StructLoad {
-  def : SInst;
+multiclass StructLoad f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 
 // Load N-element structure into N vectors (scalar base)
-defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret">;
-defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret">;
-defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret">;
+defm SVLD2 : StructLoad<"svld2[_{2}]", "2Pc", "aarch64_sve_ld2_sret", 
[VerifyRuntimeMode]>;
+defm SVLD3 : StructLoad<"svld3[_{2}]", "3Pc", "aarch64_sve_ld3_sret", 
[VerifyRuntimeMode]>;
+defm SVLD4 : StructLoad<"svld4[_{2}]", "4Pc", "aarch64_sve_ld4_sret", 
[VerifyRuntimeMode]>;
 
 // Load N-element structure into N vectors (scalar base, VL displacement)
-defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret">;
-defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret">;
-defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret">;
+defm SVLD2_VNUM : StructLoad<"svld2_vnum[_{2}]", "2Pcl", 
"aarch64_sve_ld2_sret", [VerifyRuntimeMode]>;
+defm SVLD3_VNUM : StructLoad<"svld3_vnum[_{2}]", "3Pcl", 
"aarch64_sve_ld3_sret", [VerifyRuntimeMode]>;
+defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", 
"aarch64_sve_ld4_sret", [VerifyRuntimeMode]>;
 
 // Load one octoword and replicate (scalar base)
 let SVETargetGuard = "sve,f64mm", SMETargetGuard = InvalidMode in {
@@ -434,21 +434,21 @@ def SVST1H_SCATTER_INDEX_S: 
MInst<"svst1h_scatter[_{2}base]_index[_{d}]", "v
 def SVST1W_SCATTER_INDEX_S: MInst<"svst1w_scatter[_{2}base]_index[_{d}]", 
"vPuld", "lUl",  [IsScatterStore], MemEltTyInt32,   
"aarch64_sve_st1_scatter_scalar_offset">;
 } // let SVETargetGuard = "sve"
 
-multiclass StructStore {
-  def : SInst;
+multiclass StructStore f = 
[]> {
+  def : SInst;
   let SVETargetGuard = "sve,bf16", SMETargetGuard = "sme,bf16" in {
-def: SInst;
+def: SInst;
   }
 }
 // Store N vectors into N-element structure (scalar base)
-defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2">;
-defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3">;
-defm SVST4 : StructStore<"svst4[_{d}]", "vPp4", "aarch64_sve_st4">;
+defm SVST2 : StructStore<"svst2[_{d}]", "vPp2", "aarch64_sve_st2", 
[VerifyRuntimeMode]>;
+defm SVST3 : StructStore<"svst3[_{d}]", "vPp3", "aarch64_sve_st3", 
[VerifyRuntimeMode]>;
+defm SVST4 : StructStore<"svst4[_{d}]", "vPp4", "aarch64_sve_st4", 
[VerifyRuntimeMode]>;
 
 // Store N vectors into N-element structure (scalar base, VL displacement)
-defm SVST2_VNUM : StructStore<"svst2_vnum[_{d}]", "vPpl2", "aarch64_sve_st2">;
-defm SVST3_VNUM : StructStore<"svst3_vnum[_{d}]", "vPpl3", "aarch64_sve_st3">;
-defm SVST4_VNUM : StructStore<"svst4_vnum[_{d}]", "vPpl4", "aarch64_sve_st4">;
+defm SVST2_VNUM : StructStore<"svst2_vnum[_{d}]", "vPpl2", "aarch64_sve_st2", 
[VerifyRuntimeMode]>;
+defm SVST3_VNUM : StructStore<"svst3_vnum[_{d}]", "vPpl3", "aarch64_sve_st3", 
[VerifyRuntimeMode]>;
+defm SVST4_VNUM :