[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread LLVM Continuous Integration via cfe-commits 

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder 
`openmp-offload-amdgpu-runtime` running on `omp-vega20-0` while building 
`clang` at step 7 "Add check check-offload".

Full details are available at: 
https://lab.llvm.org/buildbot/#/builders/30/builds/1


Here is the relevant piece of the build log for the reference

```
Step 7 (Add check check-offload) failure: test (failure)
 TEST 'libomptarget :: amdgcn-amd-amdhsa :: 
offloading/pgo1.c' FAILED 
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 1
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/clang 
-fopenmp-I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 -L /home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
  -nogpulib 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib 
 -fopenmp-targets=amdgcn-amd-amdhsa 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
 -o 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp
 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a
 -fprofile-instr-generate  -Xclang "-fprofile-instrument=clang"
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/clang 
-fopenmp -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 -L /home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -nogpulib 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib 
-fopenmp-targets=amdgcn-amd-amdhsa 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
 -o 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp
 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a
 -fprofile-instr-generate -Xclang -fprofile-instrument=clang
# note: command had no output on stdout or stderr
# RUN: at line 3
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp
 2>&1 | 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/FileCheck 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
  --check-prefix="CLANG-PGO"
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/pgo1.c.tmp
# note: command had no output on stdout or stderr
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/FileCheck 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
 --check-prefix=CLANG-PGO
# .---command stderr
# | 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c:32:20:
 error: CLANG-PGO-NEXT: expected string not found in input
# | // CLANG-PGO-NEXT: [ 0 11 20 ]
# |^
# | :3:28: note: scanning from here
# |  Counters =
# |^
# | :4:1: note: possible intended match here
# | [ 0 13 20 ]
# | ^
# | 
# | Input file: 
# | Check file: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/pgo1.c
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<
# |1: === GPU Profile === 
# |2: Target: amdgcn-amd-amdhsa 
# |3:  Counters = 
# | next:32'0X error: no match found
# |4: [ 0 13 20 ] 
# | next:32'0 
# | next:32'1 ?

[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread Alexandros Lamprineas via cfe-commits 

https://github.com/labrinea closed 
https://github.com/llvm/llvm-project/pull/124130
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[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread Pavel Iliin via cfe-commits 

https://github.com/ilinpv approved this pull request.

Thanks for updating `__builtin_cpu_supports `tests accordingly. 

https://github.com/llvm/llvm-project/pull/124130
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[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread Alexandros Lamprineas via cfe-commits 

https://github.com/labrinea updated 
https://github.com/llvm/llvm-project/pull/124130

>From 1611549295c5f6964839200b828243d0a33d1a37 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas 
Date: Thu, 23 Jan 2025 15:00:52 +
Subject: [PATCH 1/2] [NFC] Remove invalid features from test and autogenerate
 checks.

---
 .../CodeGen/AArch64/cpu-supports-target.c | 203 --
 1 file changed, 189 insertions(+), 14 deletions(-)

diff --git a/clang/test/CodeGen/AArch64/cpu-supports-target.c 
b/clang/test/CodeGen/AArch64/cpu-supports-target.c
index b185dda2881080..a39ffd4e4a74d4 100644
--- a/clang/test/CodeGen/AArch64/cpu-supports-target.c
+++ b/clang/test/CodeGen/AArch64/cpu-supports-target.c
@@ -1,27 +1,150 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-attributes --check-globals all --version 5
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | 
FileCheck %s
 
-int check_all_feature() {
+//.
+// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
+//.
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @check_all_features(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 66367
+// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66367
+// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
+// CHECK:   [[IF_THEN]]:
+// CHECK-NEXT:store i32 1, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN:.*]]
+// CHECK:   [[IF_ELSE]]:
+// CHECK-NEXT:[[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 14272
+// CHECK-NEXT:[[TMP6:%.*]] = icmp eq i64 [[TMP5]], 14272
+// CHECK-NEXT:[[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT:br i1 [[TMP7]], label %[[IF_THEN1:.*]], label 
%[[IF_ELSE2:.*]]
+// CHECK:   [[IF_THEN1]]:
+// CHECK-NEXT:store i32 2, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE2]]:
+// CHECK-NEXT:[[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP9:%.*]] = and i64 [[TMP8]], 2065152
+// CHECK-NEXT:[[TMP10:%.*]] = icmp eq i64 [[TMP9]], 2065152
+// CHECK-NEXT:[[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT:br i1 [[TMP11]], label %[[IF_THEN3:.*]], label 
%[[IF_ELSE4:.*]]
+// CHECK:   [[IF_THEN3]]:
+// CHECK-NEXT:store i32 3, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE4]]:
+// CHECK-NEXT:[[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP13:%.*]] = and i64 [[TMP12]], 288230376183169792
+// CHECK-NEXT:[[TMP14:%.*]] = icmp eq i64 [[TMP13]], 288230376183169792
+// CHECK-NEXT:[[TMP15:%.*]] = and i1 true, [[TMP14]]
+// CHECK-NEXT:br i1 [[TMP15]], label %[[IF_THEN5:.*]], label 
%[[IF_ELSE6:.*]]
+// CHECK:   [[IF_THEN5]]:
+// CHECK-NEXT:store i32 4, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE6]]:
+// CHECK-NEXT:[[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP17:%.*]] = and i64 [[TMP16]], 1275134720
+// CHECK-NEXT:[[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1275134720
+// CHECK-NEXT:[[TMP19:%.*]] = and i1 true, [[TMP18]]
+// CHECK-NEXT:br i1 [[TMP19]], label %[[IF_THEN7:.*]], label 
%[[IF_ELSE8:.*]]
+// CHECK:   [[IF_THEN7]]:
+// CHECK-NEXT:store i32 5, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE8]]:
+// CHECK-NEXT:[[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP21:%.*]] = and i64 [[TMP20]], 52814742272
+// CHECK-NEXT:[[TMP22:%.*]] = icmp eq i64 [[TMP21]], 52814742272
+// CHECK-NEXT:[[TMP23:%.*]] = and i1 true, [[TMP22]]
+// CHECK-NEXT:br i1 [[TMP23]], label %[[IF_THEN9:.*]], label 
%[[IF_ELSE10:.*]]
+// CHECK:   [[IF_THEN9]]:
+// CHECK-NEXT:store i32 6, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE10]]:
+// CHECK-NEXT:[[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP25:%.*]] = and i64 [[TMP24]], 344671224576
+// CHECK-NEXT:[[TMP26:%.*]] = icmp eq i64 [[TMP25]], 344671224576
+// CHECK-NEXT:[[TMP27:%.*]] = and i1 true, [[TMP26]]
+// CHECK-NEXT:br i1 [[TMP27]], label %[[IF_THEN11:.*]], label 
%[[IF_ELSE12:.*]]
+// CHECK:   [[IF_THEN11]]:
+// CHECK-NEXT:store i32 7, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE12]]:
+// CHECK-NEXT:[[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:

[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Alexandros Lamprineas (labrinea)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/124130.diff


1 Files Affected:

- (modified) clang/test/CodeGen/AArch64/cpu-supports-target.c (+189-14) 


``diff
diff --git a/clang/test/CodeGen/AArch64/cpu-supports-target.c 
b/clang/test/CodeGen/AArch64/cpu-supports-target.c
index b185dda2881080..a39ffd4e4a74d4 100644
--- a/clang/test/CodeGen/AArch64/cpu-supports-target.c
+++ b/clang/test/CodeGen/AArch64/cpu-supports-target.c
@@ -1,27 +1,150 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-attributes --check-globals all --version 5
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | 
FileCheck %s
 
-int check_all_feature() {
+//.
+// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
+//.
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @check_all_features(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 66367
+// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66367
+// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
+// CHECK:   [[IF_THEN]]:
+// CHECK-NEXT:store i32 1, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN:.*]]
+// CHECK:   [[IF_ELSE]]:
+// CHECK-NEXT:[[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 14272
+// CHECK-NEXT:[[TMP6:%.*]] = icmp eq i64 [[TMP5]], 14272
+// CHECK-NEXT:[[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT:br i1 [[TMP7]], label %[[IF_THEN1:.*]], label 
%[[IF_ELSE2:.*]]
+// CHECK:   [[IF_THEN1]]:
+// CHECK-NEXT:store i32 2, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE2]]:
+// CHECK-NEXT:[[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP9:%.*]] = and i64 [[TMP8]], 2065152
+// CHECK-NEXT:[[TMP10:%.*]] = icmp eq i64 [[TMP9]], 2065152
+// CHECK-NEXT:[[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT:br i1 [[TMP11]], label %[[IF_THEN3:.*]], label 
%[[IF_ELSE4:.*]]
+// CHECK:   [[IF_THEN3]]:
+// CHECK-NEXT:store i32 3, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE4]]:
+// CHECK-NEXT:[[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP13:%.*]] = and i64 [[TMP12]], 288230376183169792
+// CHECK-NEXT:[[TMP14:%.*]] = icmp eq i64 [[TMP13]], 288230376183169792
+// CHECK-NEXT:[[TMP15:%.*]] = and i1 true, [[TMP14]]
+// CHECK-NEXT:br i1 [[TMP15]], label %[[IF_THEN5:.*]], label 
%[[IF_ELSE6:.*]]
+// CHECK:   [[IF_THEN5]]:
+// CHECK-NEXT:store i32 4, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE6]]:
+// CHECK-NEXT:[[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP17:%.*]] = and i64 [[TMP16]], 1275134720
+// CHECK-NEXT:[[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1275134720
+// CHECK-NEXT:[[TMP19:%.*]] = and i1 true, [[TMP18]]
+// CHECK-NEXT:br i1 [[TMP19]], label %[[IF_THEN7:.*]], label 
%[[IF_ELSE8:.*]]
+// CHECK:   [[IF_THEN7]]:
+// CHECK-NEXT:store i32 5, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE8]]:
+// CHECK-NEXT:[[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP21:%.*]] = and i64 [[TMP20]], 52814742272
+// CHECK-NEXT:[[TMP22:%.*]] = icmp eq i64 [[TMP21]], 52814742272
+// CHECK-NEXT:[[TMP23:%.*]] = and i1 true, [[TMP22]]
+// CHECK-NEXT:br i1 [[TMP23]], label %[[IF_THEN9:.*]], label 
%[[IF_ELSE10:.*]]
+// CHECK:   [[IF_THEN9]]:
+// CHECK-NEXT:store i32 6, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE10]]:
+// CHECK-NEXT:[[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP25:%.*]] = and i64 [[TMP24]], 344671224576
+// CHECK-NEXT:[[TMP26:%.*]] = icmp eq i64 [[TMP25]], 344671224576
+// CHECK-NEXT:[[TMP27:%.*]] = and i1 true, [[TMP26]]
+// CHECK-NEXT:br i1 [[TMP27]], label %[[IF_THEN11:.*]], label 
%[[IF_ELSE12:.*]]
+// CHECK:   [[IF_THEN11]]:
+// CHECK-NEXT:store i32 7, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE12]]:
+// CHECK-NEXT:[[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP29:%.*]] = and i64 [[TMP28]], 3918083994400
+// CHECK-NEXT:[[TMP30:%.*]] = icmp eq i64 [[TMP29]], 3918083994400
+// CHECK-NEXT:[[TMP31:%.*]] = an

[clang] [NFC] Remove invalid features from test and autogenerate checks. (PR #124130)

2025-01-23 Thread Alexandros Lamprineas via cfe-commits 

https://github.com/labrinea created 
https://github.com/llvm/llvm-project/pull/124130

None

>From 1611549295c5f6964839200b828243d0a33d1a37 Mon Sep 17 00:00:00 2001
From: Alexandros Lamprineas 
Date: Thu, 23 Jan 2025 15:00:52 +
Subject: [PATCH] [NFC] Remove invalid features from test and autogenerate
 checks.

---
 .../CodeGen/AArch64/cpu-supports-target.c | 203 --
 1 file changed, 189 insertions(+), 14 deletions(-)

diff --git a/clang/test/CodeGen/AArch64/cpu-supports-target.c 
b/clang/test/CodeGen/AArch64/cpu-supports-target.c
index b185dda2881080..a39ffd4e4a74d4 100644
--- a/clang/test/CodeGen/AArch64/cpu-supports-target.c
+++ b/clang/test/CodeGen/AArch64/cpu-supports-target.c
@@ -1,27 +1,150 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py 
UTC_ARGS: --check-attributes --check-globals all --version 5
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | 
FileCheck %s
 
-int check_all_feature() {
+//.
+// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
+//.
+// CHECK: Function Attrs: noinline nounwind optnone
+// CHECK-LABEL: define dso_local i32 @check_all_features(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT:  [[ENTRY:.*:]]
+// CHECK-NEXT:[[RETVAL:%.*]] = alloca i32, align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP1:%.*]] = and i64 [[TMP0]], 66367
+// CHECK-NEXT:[[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66367
+// CHECK-NEXT:[[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT:br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
+// CHECK:   [[IF_THEN]]:
+// CHECK-NEXT:store i32 1, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN:.*]]
+// CHECK:   [[IF_ELSE]]:
+// CHECK-NEXT:[[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP5:%.*]] = and i64 [[TMP4]], 14272
+// CHECK-NEXT:[[TMP6:%.*]] = icmp eq i64 [[TMP5]], 14272
+// CHECK-NEXT:[[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT:br i1 [[TMP7]], label %[[IF_THEN1:.*]], label 
%[[IF_ELSE2:.*]]
+// CHECK:   [[IF_THEN1]]:
+// CHECK-NEXT:store i32 2, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE2]]:
+// CHECK-NEXT:[[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
+// CHECK-NEXT:[[TMP9:%.*]] = and i64 [[TMP8]], 2065152
+// CHECK-NEXT:[[TMP10:%.*]] = icmp eq i64 [[TMP9]], 2065152
+// CHECK-NEXT:[[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT:br i1 [[TMP11]], label %[[IF_THEN3:.*]], label 
%[[IF_ELSE4:.*]]
+// CHECK:   [[IF_THEN3]]:
+// CHECK-NEXT:store i32 3, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE4]]:
+// CHECK-NEXT:[[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP13:%.*]] = and i64 [[TMP12]], 288230376183169792
+// CHECK-NEXT:[[TMP14:%.*]] = icmp eq i64 [[TMP13]], 288230376183169792
+// CHECK-NEXT:[[TMP15:%.*]] = and i1 true, [[TMP14]]
+// CHECK-NEXT:br i1 [[TMP15]], label %[[IF_THEN5:.*]], label 
%[[IF_ELSE6:.*]]
+// CHECK:   [[IF_THEN5]]:
+// CHECK-NEXT:store i32 4, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE6]]:
+// CHECK-NEXT:[[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP17:%.*]] = and i64 [[TMP16]], 1275134720
+// CHECK-NEXT:[[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1275134720
+// CHECK-NEXT:[[TMP19:%.*]] = and i1 true, [[TMP18]]
+// CHECK-NEXT:br i1 [[TMP19]], label %[[IF_THEN7:.*]], label 
%[[IF_ELSE8:.*]]
+// CHECK:   [[IF_THEN7]]:
+// CHECK-NEXT:store i32 5, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE8]]:
+// CHECK-NEXT:[[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP21:%.*]] = and i64 [[TMP20]], 52814742272
+// CHECK-NEXT:[[TMP22:%.*]] = icmp eq i64 [[TMP21]], 52814742272
+// CHECK-NEXT:[[TMP23:%.*]] = and i1 true, [[TMP22]]
+// CHECK-NEXT:br i1 [[TMP23]], label %[[IF_THEN9:.*]], label 
%[[IF_ELSE10:.*]]
+// CHECK:   [[IF_THEN9]]:
+// CHECK-NEXT:store i32 6, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE10]]:
+// CHECK-NEXT:[[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEXT:[[TMP25:%.*]] = and i64 [[TMP24]], 344671224576
+// CHECK-NEXT:[[TMP26:%.*]] = icmp eq i64 [[TMP25]], 344671224576
+// CHECK-NEXT:[[TMP27:%.*]] = and i1 true, [[TMP26]]
+// CHECK-NEXT:br i1 [[TMP27]], label %[[IF_THEN11:.*]], label 
%[[IF_ELSE12:.*]]
+// CHECK:   [[IF_THEN11]]:
+// CHECK-NEXT:store i32 7, ptr [[RETVAL]], align 4
+// CHECK-NEXT:br label %[[RETURN]]
+// CHECK:   [[IF_ELSE12]]:
+// CHECK-NEXT:[[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 
8
+// CHECK-NEX