[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler closed https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler updated
https://github.com/llvm/llvm-project/pull/171124
>From 46e20c2c9465713fbfc33491f068d033f0609348 Mon Sep 17 00:00:00 2001
From: David Candler
Date: Mon, 8 Dec 2025 13:30:37 +
Subject: [PATCH 1/3] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++
.../aarch64-c1-premium.c | 71
.../print-enabled-extensions/aarch64-c1-pro.c | 71
.../aarch64-c1-ultra.c| 71
.../Misc/target-invalid-cpu-note/aarch64.c| 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp| 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 005e858821804..ce1b51c8b99e7 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -637,6 +637,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler updated
https://github.com/llvm/llvm-project/pull/171124
>From caec7fab5829b87c0c5cb4c8d63cae55be9906e7 Mon Sep 17 00:00:00 2001
From: David Candler
Date: Mon, 8 Dec 2025 13:30:37 +
Subject: [PATCH 1/3] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++
.../aarch64-c1-premium.c | 71
.../print-enabled-extensions/aarch64-c1-pro.c | 71
.../aarch64-c1-ultra.c| 71
.../Misc/target-invalid-cpu-note/aarch64.c| 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp| 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 690d2a389ef24..82ea1be3dc353 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -636,6 +636,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -1262,6 +1367,8 @@ def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE, [TuneA720AE]>; def : ProcessorModel<"cortex-a725", NeoverseN3Model, ProcessorFeatures.A725, [TuneA725]>; +def : ProcessorModel<"c1-pro", NeoverseN2Model, davemgreen wrote: And this one can be NeoverseN3Model? https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -1228,6 +1331,8 @@ def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520, [TuneA520]>; def : ProcessorModel<"cortex-a520ae", CortexA510Model, ProcessorFeatures.A520AE, [TuneA520AE]>; +def : ProcessorModel<"c1-nano", NeoverseN2Model, davemgreen wrote: This should be CortexA510Model. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -1278,6 +1385,10 @@ def : ProcessorModel<"cortex-x4", NeoverseV3Model, ProcessorFeatures.X4, [TuneX4]>; def : ProcessorModel<"cortex-x925", NeoverseV3Model, ProcessorFeatures.X925, [TuneX925]>; +def : ProcessorModel<"c1-ultra", NeoverseV3Model, + ProcessorFeatures.C1Ultra, [TuneC1Ultra]>; +def : ProcessorModel<"c1-premium", NeoverseV3Model, davemgreen wrote: Same here. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -300,6 +320,32 @@ def TuneX925 : SubtargetFeature<"cortex-x925", "ARMProcFamily", FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Ultra : SubtargetFeature<"c1-ultra", "ARMProcFamily", + "C1Ultra", "C1-Ultra ARM Processors",[ + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureFuseCmpCSel, + FeatureFuseCmpCSet, + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeatureUseFixedOverScalableIfEqualCost, + FeatureAvoidLDAPUR, + FeaturePredictableSelectIsExpensive]>; + +def TuneC1Premium : SubtargetFeature<"c1-premium", "ARMProcFamily", davemgreen wrote: Premium before Ultra. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -973,6 +1046,36 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureFullFP16, FeatureMatMulInt8,
FeatureJS, FeatureLSE, FeatureNEON,
FeaturePAuth, FeatureRAS,
FeatureRCPC, FeatureRDM, FeatureFPAC];
+ list C1Ultra = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
+FeatureCHK, FeatureFPARMv8, FeaturePerfMon,
+FeatureSPECRES2, FeatureSSBS, FeatureRDM,
+FeatureVH, FeatureBF16, FeatureDotProd,
+FeatureFP16FML, FeatureFullFP16,
+FeatureMPAM, FeatureSPE, FeatureSVE,
+FeatureCCIDX, FeatureComplxNum,
FeatureFPAC,
+FeatureJS, FeatureAM, FeatureRAS,
+FeatureSEL2, FeatureTRACEV8_4,
+FeatureAltFPCmp, FeatureFRInt3264,
+FeatureMTE, FeatureFineGrainedTraps,
+FeatureHCX, FeatureSPE_EEF, FeatureRCPC3,
+FeatureETE, FeatureSVEBitPerm, FeatureSVE2,
+FeatureTRBE, FeatureSME, FeatureSME2];
+ list C1Premium = [HasV9_3aOps, FeatureNEON, FeatureCLRBHB,
davemgreen wrote:
C1Premium < C1Ultra. (Although you could just reuse the same list for both).
https://github.com/llvm/llvm-project/pull/171124
___
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/davemgreen commented: I went through the features and they look OK to me, using a comparison to the previous generation. RPRFM should be added to these cpus too, but that is only being added in #170490. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
Andarwinux wrote: > > As for MOPS, I'm just concerned that -mcpu=c1-* will result in memcpy and > > memset to be inlined unconditionally, which according to Arm's errata will > > result in performance degradation, > > On the other hand, if someone explicitly writes a MOPS instruction in > assembly language, it shouldn't fail to assemble. The questions of "does the > CPU understand this instruction?" and "is it a good idea to use it in code > generation?" are conceptually separate. But at the moment llvm doesn't seem to be able to distinguish between the two. I think a tune option could be added to avoid preferring MOPS in code generation, similar to x86's “FeatureFSRM”. > We do have a convention for CPUs, agreed with the Arm GNU team as we want CPU > features to be consistent as possible across toolchains, that for each Arm > CPU we enable all optional features (like SME), with crypto being the > exception of always being opt-in. This is partly historical as GCC has always > modelled it that way and crypto extensions are subject to export control. > > I understand that a lot of this will look inconsistent externally. > > As statham-arm mentions we want to separate what features the CPU supports > from whether it is the right thing to do to make use of them. Well, that makes sense. And it seems unlikely that there will be actual products that indeed don't have C1-SME2. But I'm still concerned that this will cause people to avoid using `-mcpu=c1-*`, just as Qualcomm's SoCs with Armv9 Cortex disabled SVE, so that `-mcpu=cortex-*` binaries can't be executed on `cortex-*`. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
smithp35 wrote: We do have a convention for CPUs, agreed with the Arm GNU team as we want CPU features to be consistent as possible across toolchains, that for each Arm CPU we enable all optional features (like SME), with crypto being the exception of always being opt-in. This is partly historical as GCC has always modelled it that way and crypto extensions are subject to export control. I understand that a lot of this will look inconsistent externally. As statham-arm mentions we want to separate what features the CPU supports from whether it is the right thing to do to make use of them. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
statham-arm wrote: > As for MOPS, I'm just concerned that -mcpu=c1-* will result in memcpy and > memset to be inlined unconditionally, which according to Arm's errata will > result in performance degradation, On the other hand, if someone explicitly writes a MOPS instruction in assembly language, it shouldn't fail to assemble. The questions of "does the CPU understand this instruction?" and "is it a good idea to use it in code generation?" are conceptually separate. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler updated
https://github.com/llvm/llvm-project/pull/171124
>From 6558a3cb452b64c1f314350372a97cb030c694fb Mon Sep 17 00:00:00 2001
From: David Candler
Date: Mon, 8 Dec 2025 13:30:37 +
Subject: [PATCH 1/2] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++
.../aarch64-c1-premium.c | 71
.../print-enabled-extensions/aarch64-c1-pro.c | 71
.../aarch64-c1-ultra.c| 71
.../Misc/target-invalid-cpu-note/aarch64.c| 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp| 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1cd465e25947a..6408791422c07 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -635,6 +635,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/jthackray approved this pull request. Thanks for the fixes. LGTM now. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
dcandler wrote: > It looks like all C1 series enabled SME and MOPS unconditionally. But > according to Arm, only C1-Ultra/Premium are forced with SME support, and MOPS > may cause performance degradation. My understanding is that the convention of the `-mcpu` option is to enable all optional and mandatory features. The C1-Nano and Pro can be configured with SME, so the compiler should be able to support it, while MOPS is mandatory from v8.8. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler edited https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", dcandler wrote: Done. I've also adjusted the placements of the occurances to match. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", + "C1Nano", "C1-Nano ARM Processors",[ + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureUseWzrToVecMove, + FeatureUseFixedOverScalableIfEqualCost]>; + +def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily", + "C1Pro", "C1-Pro ARM Processors",[ + FeatureFuseAES, + FeaturePostRAScheduler, dcandler wrote: For the Pro, I used the same tuning features as the A725. It was the Premium I got wrong somehow: it should have used the same as the Ultra. Fixed now. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -1301,6 +1400,14 @@ def : ProcessorModel<"neoverse-v3", NeoverseV3Model, ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; def : ProcessorModel<"neoverse-v3ae", NeoverseV3AEModel, ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; +def : ProcessorModel<"c1-nano", CortexA510Model, + ProcessorFeatures.C1Nano, [TuneC1Nano]>; +def : ProcessorModel<"c1-pro", NeoverseN2Model, dcandler wrote: Done https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler updated
https://github.com/llvm/llvm-project/pull/171124
>From 01c2164e60a957e251ab568241e8414fd5fd9ee3 Mon Sep 17 00:00:00 2001
From: David Candler
Date: Mon, 8 Dec 2025 13:30:37 +
Subject: [PATCH 1/2] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++
.../aarch64-c1-premium.c | 71
.../print-enabled-extensions/aarch64-c1-pro.c | 71
.../aarch64-c1-ultra.c| 71
.../Misc/target-invalid-cpu-note/aarch64.c| 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp| 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index acca997e0ff64..e36a4c64965cb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -631,6 +631,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", + "C1Nano", "C1-Nano ARM Processors",[ + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureUseWzrToVecMove, + FeatureUseFixedOverScalableIfEqualCost]>; + +def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily", + "C1Pro", "C1-Pro ARM Processors",[ + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureCmpBccFusion, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureFuseCmpCSel, + FeatureFuseCmpCSet, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + +def TuneC1Premium : SubtargetFeature<"c1-premium", "ARMProcFamily", + "C1Premium", "C1-Premium ARM Processors",[ + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + +def TuneC1Ultra : SubtargetFeature<"c1-ultra", "ARMProcFamily", davemgreen wrote: And following on after the TuneC1Premium, I believe. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -1301,6 +1400,14 @@ def : ProcessorModel<"neoverse-v3", NeoverseV3Model, ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; def : ProcessorModel<"neoverse-v3ae", NeoverseV3AEModel, ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; +def : ProcessorModel<"c1-nano", CortexA510Model, + ProcessorFeatures.C1Nano, [TuneC1Nano]>; +def : ProcessorModel<"c1-pro", NeoverseN2Model, davemgreen wrote: I think this can use the NeoverseN2Model model, now that we have it. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", + "C1Nano", "C1-Nano ARM Processors",[ + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureUseWzrToVecMove, + FeatureUseFixedOverScalableIfEqualCost]>; + +def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily", + "C1Pro", "C1-Pro ARM Processors",[ + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureCmpBccFusion, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureFuseCmpCSel, + FeatureFuseCmpCSet, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + +def TuneC1Premium : SubtargetFeature<"c1-premium", "ARMProcFamily", davemgreen wrote: After the cortex-x925 I think. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", davemgreen wrote: I would move this to follow the TuneA520AE, so as to help keep them in order. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", + "C1Nano", "C1-Nano ARM Processors",[ + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureUseWzrToVecMove, + FeatureUseFixedOverScalableIfEqualCost]>; + +def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily", + "C1Pro", "C1-Pro ARM Processors",[ + FeatureFuseAES, + FeaturePostRAScheduler, davemgreen wrote: It looks like this and the Premium tuning features are the wrong way around. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
@@ -669,6 +669,48 @@ def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "Neover FeatureAvoidLDAPUR, FeaturePredictableSelectIsExpensive]>; +def TuneC1Nano : SubtargetFeature<"c1-nano", "ARMProcFamily", + "C1Nano", "C1-Nano ARM Processors",[ + FeatureFuseAES, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureUseWzrToVecMove, + FeatureUseFixedOverScalableIfEqualCost]>; + +def TuneC1Pro : SubtargetFeature<"c1-pro", "ARMProcFamily", davemgreen wrote: After the A725 https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
Andarwinux wrote: It looks like all C1 series enabled SME and MOPS unconditionally. But according to Arm, only C1-Ultra/Premium are forced with SME support, and MOPS may cause performance degradation. https://developer.arm.com/documentation/111076/0100 https://developer.arm.com/documentation/107753/0001/The-C1-Nano--core/C1-Nano--core-features >The C1-SME2unit is optional, unless the cluster includes an >ultimate-performance core. If the C1-SME2unit is not implemented, SME and SME2 >are not supported. For more information about configuring the C1-SME2 unit, >see the Arm® C1-Scalable Matrix Extension 2 Configuration and Integration >Manual and the RTL configuration process section in the Arm® C1-DynamIQ™ >Shared Unit Configuration and Integration Manual. https://developer.arm.com/documentation/111077/8-0 > Under certain micro-architectural conditions, when the Processing Element > (PE) is executing FEAT_MOPS instructions, performance might be degraded. This is due to micro-architectural flushes that occur due to read-after-write hazards or hardware prefetch ineffectively caching contiguous accesses. https://github.com/llvm/llvm-project/pull/171124 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
llvmbot wrote:
@llvm/pr-subscribers-backend-aarch64
Author: None (dcandler)
Changes
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
Patch is 49.71 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/171124.diff
13 Files Affected:
- (modified) clang/docs/ReleaseNotes.rst (+5)
- (modified) clang/test/Driver/aarch64-mcpu.c (+8)
- (added) clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c (+69)
- (added) clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c (+71)
- (added) clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c (+71)
- (added) clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c (+71)
- (modified) clang/test/Misc/target-invalid-cpu-note/aarch64.c (+4)
- (modified) llvm/docs/ReleaseNotes.md (+2)
- (modified) llvm/lib/Target/AArch64/AArch64Processors.td (+107)
- (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+4)
- (modified) llvm/lib/TargetParser/Host.cpp (+4)
- (modified) llvm/unittests/TargetParser/Host.cpp (+12)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+5-1)
``diff
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index acca997e0ff64..e36a4c64965cb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -631,6 +631,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
new file mode 100644
index 0..33112527c9add
--- /dev/null
+++ b/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
@@ -0,0 +1,69 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=c1-nano |
FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
+
+// CHECK: Extensions enabled for the given AArch64 target
+// CHECK-EMPTY:
+// CHECK-NEXT: Architecture Feature(s)
Description
+// CHECK-NEXT: FEAT_AMUv1
Enable Armv8.4-A Activity Monitors extension
+// CHECK-NEXT: FEAT_AMUv1p1
Enable Armv8.6-A Activity Monitors Virtualization support
+// CHECK-NEXT: FEAT_AdvSIMD
Enable Advanced SIMD instructions
+// CHECK-NEXT: FEAT_BF16
Enable BFloat16 Extension
+// CHECK-NEXT: FEAT_BTI
[clang] [llvm] [AArch64] Add support for C1 CPUs (PR #171124)
https://github.com/dcandler created
https://github.com/llvm/llvm-project/pull/171124
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
>From 01c2164e60a957e251ab568241e8414fd5fd9ee3 Mon Sep 17 00:00:00 2001
From: David Candler
Date: Mon, 8 Dec 2025 13:30:37 +
Subject: [PATCH] [AArch64] Add support for C1 CPUs
This patch adds initial support for the Arm v9.3 C1 processors:
* C1-Nano
* C1-Pro
* C1-Premium
* C1-Ultra
For more information on each, see:
https://developer.arm.com/Processors/C1-Nano
https://developer.arm.com/Processors/C1-Pro
https://developer.arm.com/Processors/C1-Premium
https://developer.arm.com/Processors/C1-Ultra
Technical Reference Manual for C1-Nano:
https://developer.arm.com/documentation/107753/latest/
Technical Reference Manual for C1-Pro:
https://developer.arm.com/documentation/107771/latest/
Technical Reference Manual for C1-Premium:
https://developer.arm.com/documentation/109416/latest/
Technical Reference Manual for C1-Ultra:
https://developer.arm.com/documentation/108014/latest/
---
clang/docs/ReleaseNotes.rst | 5 +
clang/test/Driver/aarch64-mcpu.c | 8 ++
.../aarch64-c1-nano.c | 69 +++
.../aarch64-c1-premium.c | 71
.../print-enabled-extensions/aarch64-c1-pro.c | 71
.../aarch64-c1-ultra.c| 71
.../Misc/target-invalid-cpu-note/aarch64.c| 4 +
llvm/docs/ReleaseNotes.md | 2 +
llvm/lib/Target/AArch64/AArch64Processors.td | 107 ++
llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 4 +
llvm/lib/TargetParser/Host.cpp| 4 +
llvm/unittests/TargetParser/Host.cpp | 12 ++
.../TargetParser/TargetParserTest.cpp | 6 +-
13 files changed, 433 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-premium.c
create mode 100644 clang/test/Driver/print-enabled-extensions/aarch64-c1-pro.c
create mode 100644
clang/test/Driver/print-enabled-extensions/aarch64-c1-ultra.c
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index acca997e0ff64..e36a4c64965cb 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -631,6 +631,11 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support has been added for the following processors (command-line
identifiers in parentheses):
+ - Arm C1-Nano (``c1-nano``)
+ - Arm C1-Pro (``c1-pro``)
+ - Arm C1-Premium (``c1-premium``)
+ - Arm C1-Ultra (``c1-ultra``)
- More intrinsics for the following AArch64 instructions:
FCVTZ[US], FCVTN[US], FCVTM[US], FCVTP[US], FCVTA[US]
diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c
index 447ee4bd3a6f9..fdf2e4011487a 100644
--- a/clang/test/Driver/aarch64-mcpu.c
+++ b/clang/test/Driver/aarch64-mcpu.c
@@ -84,6 +84,14 @@
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520"
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 |
FileCheck -check-prefix=CORTEX-A520AE %s
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"cortex-a520ae"
+// RUN: %clang --target=aarch64 -mcpu=c1-nano -### -c %s 2>&1 | FileCheck
-check-prefix=C1-NANO %s
+// C1-NANO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-nano"
+// RUN: %clang --target=aarch64 -mcpu=c1-pro -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PRO %s
+// C1-PRO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-pro"
+// RUN: %clang --target=aarch64 -mcpu=c1-premium -### -c %s 2>&1 | FileCheck
-check-prefix=C1-PREMIUM %s
+// C1-PREMIUM: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"c1-premium"
+// RUN: %clang --target=aarch64 -mcpu=c1-ultra -### -c %s 2>&1 | FileCheck
-check-prefix=C1-ULTRA %s
+// C1-ULTRA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "c1-ultra"
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-c1-nano.c
b/clang/test/Driver/print-enable
