[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `sanitizer-aarch64-linux-bootstrap-hwasan` running on `sanitizer-buildbot11` while building `clang,llvm` at step 2 "annotate". Full details are available at: https://lab.llvm.org/buildbot/#/builders/55/builds/9905 Here is the relevant piece of the build log for the reference ``` Step 2 (annotate) failure: 'python ../sanitizer_buildbot/sanitizers/zorg/buildbot/builders/sanitizers/buildbot_selector.py' (failure) ... llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using lld-link: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/lld-link llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using ld64.lld: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/ld64.lld llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using wasm-ld: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/wasm-ld llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using ld.lld: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/ld.lld llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using lld-link: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/lld-link llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using ld64.lld: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/ld64.lld llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/llvm/config.py:520: note: using wasm-ld: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/wasm-ld llvm-lit: /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/utils/lit/lit/main.py:72: note: The test suite configuration requested an individual test timeout of 0 seconds but a timeout of 900 seconds was requested on the command line. Forcing timeout to be 900 seconds. -- Testing: 87743 tests, 72 workers -- Testing: 0.. 10.. 20.. 30.. 40.. 50.. FAIL: LLVM :: ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s (53457 of 87743) TEST 'LLVM :: ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s' FAILED Exit Code: 1 Command Output (stderr): -- /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/llvm-mc -filetype=obj -triple=x86_64-windows-msvc /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/test/ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s -o /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/test/ExecutionEngine/JITLink/x86-64/Output/COFF_directive_alternatename_fail.s.tmp # RUN: at line 1 + /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/llvm-mc -filetype=obj -triple=x86_64-windows-msvc /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/test/ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s -o /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/test/ExecutionEngine/JITLink/x86-64/Output/COFF_directive_alternatename_fail.s.tmp not /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/llvm-jitlink -noexec /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/test/ExecutionEngine/JITLink/x86-64/Output/COFF_directive_alternatename_fail.s.tmp 2>&1 | /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/FileCheck /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/test/ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s # RUN: at line 2 + not /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/llvm-jitlink -noexec /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/test/ExecutionEngine/JITLink/x86-64/Output/COFF_directive_alternatename_fail.s.tmp + /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm_build_hwasan/bin/FileCheck /home/b/sanitizer-aarch64-linux-bootstrap-hwasan/build/llvm-project/llvm/test/ExecutionEngine/JITLink/x86-64/COFF_directive_alternatename_fail.s -- Testing: 0.. 10.. 20.. 30.. 40.. 50.. 60.. 70.. 80.. 90.. Slowest Tests: -- 56.53s: Clang :: Driver/fsanitize.c 40.75s: Clang :: Preprocessor/riscv-target-features.c 38.17s: Clang :: Driver/arm-cortex-cpus-2.c 37.66s: Clang :: Driver/arm-cortex-cpus-1
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 closed https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/davemgreen approved this pull request. Thanks. LGTM https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 978d9a153f9c5a98f6c20b94281f1acd02ecae4e Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/9] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 456c3b5396fc9..956fc9680ee33 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12970,7 +12970,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -419,6 +419,9 @@ Bug Fixes to Attribute Support - No longer crashing on ``__attribute__((align_value(N)))`` during template instantiation when the function parameter type is not a pointer or reference. (#GH26612) +- The ``+nosimd`` attribute is now fully supported for AArch32. Previously, this had no effect when being used with davemgreen wrote: Can a comment be added to the arm section too / instead? https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 commented: Thanks @davemgreen for the review. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -419,6 +419,9 @@ Bug Fixes to Attribute Support - No longer crashing on ``__attribute__((align_value(N)))`` during template instantiation when the function parameter type is not a pointer or reference. (#GH26612) +- The ``+nosimd`` attribute is now fully supported for AArch32. Previously, this had no effect when being used with Stylie777 wrote: I have moved it to the ARM section. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
Stylie777 wrote: I have rebased this now after #134612 has been merged. This PR is only now looking at enabling +nosimd for ARM targets. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 978d9a153f9c5a98f6c20b94281f1acd02ecae4e Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/8] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 456c3b5396fc9..956fc9680ee33 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12970,7 +12970,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -0,0 +1,31 @@ +// Ensures that when targeting an ARM target with an Asm file, clang +// collects the features from the FPU. This is critical in the +// activation of NEON for supported targets. The Cortex-R52 will be +// used and tested for VFP and NEON Support + +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null | count 0 +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null -### 2> %t | FileCheck --check-prefix=CHECK-TARGET-FEATURES < %t %s Stylie777 wrote: Done https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/davemgreen commented: Thanks - this looks good. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 commented: Thanks @davemgreen for the re-review. I have made some updated based on your comments. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -0,0 +1,31 @@ +// Ensures that when targeting an ARM target with an Asm file, clang +// collects the features from the FPU. This is critical in the +// activation of NEON for supported targets. The Cortex-R52 will be +// used and tested for VFP and NEON Support + +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null | count 0 Stylie777 wrote: Done https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 01/10] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 456c3b5396fc9..956fc9680ee33 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12970,7 +12970,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -0,0 +1,31 @@ +// Ensures that when targeting an ARM target with an Asm file, clang +// collects the features from the FPU. This is critical in the +// activation of NEON for supported targets. The Cortex-R52 will be +// used and tested for VFP and NEON Support + +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null | count 0 mstorsjo wrote: This requires a `// REQUIRES: arm-registered-target` (like `armv8.1.m.main.s` has), as this actually does try to compile the code. Actually compiling code in Clang driver tests would ideally not be done (we should ideally only inspect the generated command lines), but we do seem to have some precedent for it already in `armv8.1.m.main.s`, and especially for the implicit behaviours that aren't necessarily visible in the command line, I guess there's no other good alternative. So I guess this kind of test is fine, but add the `REQUIRES` line. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
- std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (CPU != "generic")
-Generic = false;
- llvm::ARM::ArchKind ArchKind =
- arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
- FPUKind = llvm::ARM::getDefaultFPU(CPU, ArchKind);
- (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
-}
+std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
+bool Generic = CPU == "generic";
if (Generic && (Triple.isOSWindows() || Triple.isOSDarwin()) &&
getARMSubArchVersionNumber(Triple) >= 7) {
FPUKind = llvm::ARM::parseFPU("neon");
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
+} else if ((!Generic) ||
davemgreen wrote:
Can this now be `else if (!ForAS || !Generic) {`. I wasn't sure why armv7 is
special? This should mean that `-march=armv8-m.main` for example works as it
did before, and as far as I can tell the versions with cpus remain the same
too. (i.e. clang/test/Driver/armv8.1m.main.s should no longer change).
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/9] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 456c3b5396fc9..956fc9680ee33 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12970,7 +12970,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -38,6 +38,9 @@ Potentially Breaking Changes - Fix missing diagnostics for uses of declarations when performing typename access, such as when performing member access on a '[[deprecated]]' type alias. (#GH58547) +- For ARM targets, when using cc1as, the features included in the selected CPU or + Arch's FPU are now loaded and utilized. If you wish not to use a specific feature, + this will need appending to the command line used. Stylie777 wrote: I think there were some cases such as NEON which now are detected when using `cc1as` that were not before as I am still not 100% sure if cc1as got the features from the FPU once inside `cc1as`. I could not find anywhere that this was done anyway. This change _could_ lead to a user needing to disable features if they wish to do so. However, with assembler I don't think that is as important as if this was `cc1` as the assembly instructions will already be defined. This entry was more to ensure people were aware incase there was some confusion as to what this change was and its potential impact. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
- std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (CPU != "generic")
-Generic = false;
- llvm::ARM::ArchKind ArchKind =
- arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
- FPUKind = llvm::ARM::getDefaultFPU(CPU, ArchKind);
- (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
-}
+std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
+bool Generic = CPU == "generic";
if (Generic && (Triple.isOSWindows() || Triple.isOSDarwin()) &&
getARMSubArchVersionNumber(Triple) >= 7) {
FPUKind = llvm::ARM::parseFPU("neon");
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
+} else if ((!Generic) ||
Stylie777 wrote:
There was a change made in #122095 that ensured NEON was enabled for generic
CPU's on those Triple's as this was not the case previously. Originally I had
it as `else if (!Generic)` as having `!ForAS` is what was stopping the Driver
from collecting the features from the FPU but I found it was not collecting all
expected features for specific targets and tests were failing. Let me go back
and try a different approach here to get it to be just (!Generic)
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
- std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
- if (CPU != "generic")
-Generic = false;
- llvm::ARM::ArchKind ArchKind =
- arm::getLLVMArchKindForARM(CPU, ArchName, Triple);
- FPUKind = llvm::ARM::getDefaultFPU(CPU, ArchKind);
- (void)llvm::ARM::getFPUFeatures(FPUKind, Features);
-}
+std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);
+bool Generic = CPU == "generic";
if (Generic && (Triple.isOSWindows() || Triple.isOSDarwin()) &&
getARMSubArchVersionNumber(Triple) >= 7) {
FPUKind = llvm::ARM::parseFPU("neon");
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
+} else if ((!Generic) ||
Stylie777 wrote:
On reflection, this should have been an else block as the FPU was always
handled so this did change behaviour.
cc1as previously never handled the FPU at all, either in the Driver stage or
once it had been called, so this is why `clang/test/Driver/armv8.1m.main.s` has
changed, as previously the FPU's features were missed completely. They would be
used in cc1 as that considers the FPU.
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/davemgreen edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -38,6 +38,9 @@ Potentially Breaking Changes - Fix missing diagnostics for uses of declarations when performing typename access, such as when performing member access on a '[[deprecated]]' type alias. (#GH58547) +- For ARM targets, when using cc1as, the features included in the selected CPU or + Arch's FPU are now loaded and utilized. If you wish not to use a specific feature, + this will need appending to the command line used. davemgreen wrote: What, from a user facing point of view, changes with the new patch? My understanding is that we pass the fpu features from the driver->cc1as now as opposed to calulcating them in cc1as, but it doesn't alter the behaviour otherwise? The examples I tried all work as before, but there are a lot of different possibilities so I might be missing one again. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -0,0 +1,31 @@ +// Ensures that when targeting an ARM target with an Asm file, clang +// collects the features from the FPU. This is critical in the +// activation of NEON for supported targets. The Cortex-R52 will be +// used and tested for VFP and NEON Support + +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null | count 0 +// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52 -c %s -o /dev/null -### 2> %t | FileCheck --check-prefix=CHECK-TARGET-FEATURES < %t %s davemgreen wrote: I think this might need to either pipe &2 into stdout, or `cat %t | FileCheck..` https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/8] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 456c3b5396fc9..956fc9680ee33 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12970,7 +12970,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however will now disable NEON instructions being generated. The `simd` is also now +printed when the `--print-supported-extensions` option is used.. jthackray wrote: nit: extra trailing period character. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however this will now disable NEON instructions being generated. The `simd` option is +also now printed when the `--print-supported-extensions` option is used. Stylie777 wrote: Thanks, I must have put it here as the change has to be made in LLVM but you are correct, `+nosimd` is a clang option rather than LLVM. I have updated this. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
-ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
+ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
davemgreen wrote:
I think I would have expected neon vs non-neon to come from the fpu option /
default, under Arm. We (essentially) default to -mfpu=auto but it can get quite
complex with all the different ways of specifying it.
https://github.com/llvm/llvm-project/pull/130623
___
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however will now disable NEON instructions being generated. The `simd` is also now jthackray wrote: ```suggestion AArch32 targets, however this will now disable NEON instructions being generated. The `simd` option is also now ``` https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/130623
`+simd` and `+nosimd` are used to emable or disable NEON Instructions
when compiling for AArch32 Targets. However, up until now, using these
has not been possible. To enable this, these options are mapped to the
relevant LLVM backend option (`+neon` and `-neon`) so it can be both
enabled and disabled successfully by the user.
Tests have been added to ensure this behaviour is maintained in the future,
along with updates to existing tests as behaviour has now changed relating
to the use of `+simd` and `+nosimd`.
As `simd` has been mapped within the ARMTargetParser.def, support for this
extension is also added for the `--print-support-extensions` command when
the target is AArch32. This will print the `simd` option, along with the
description that relates to the Neon feature. This previously was not
possible as `simd` did not have a related Feature or Negative Feature.
To make this functional as intended, MVE and MVE.FP now rely on their own
Enum identifier, rather than `AEK_SIMD`. While SIMD does refer to both
Neon and Helium technologies, in terms of command line options, SIMD relates
to Neon. Helium relates to MVE and MVE.FP. The Enum now reflects this too.
>From d6772d64ff6fd515621c073b6545c40e918893b5 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/2] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
Stylie777 wrote: No worries 😀 If we remove `ARM::AEK_SIMD` is removed, the target will not be able to process or generate NEON instructions. I have added it to all ArmV8-a (and beyond) architectures and the Cortex-R52 CPU. This should cover all the Cortex-A and Cortex-R targets that support it. As ArmV7-A has NEON as an optional feature, I have not added it here. The only thing I may have missed is if Arm V7-A CPU's Support NEON as a mandatory feature, I would need to check this. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
davemgreen wrote: Sorry for the delay, my computer got very slow at building things. - What goes wrong if ARM::AEK_SIMD is removed from the CPU and architecture definitions? If it is needed then there are some other cpu's where it might need to be added too. But I'm not sure what needs it. (Target parsing gets quite complex and isn't nearly as well documented as it needs to be. We could do with something that explains how it is meant to work, at a high level so we can have a coherent design). https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
davemgreen wrote: NEON is never mandatory AFAIU in the architecture (FP too). We might assume it to be present though, as I believe it comes from the default -mfpu. (For example FK_CRYPTO_NEON_FP_ARMV8 from armv8-a). Using something like this: https://godbolt.org/z/EKEMsaMdW. If I take this patch and remove the ARM::AEK_SIMD from the ARM_ARCH and ARM_CPU_NAME definitions it still seems to do OK. Is there some other reason that AEK_SIMD needs to be added to them? I tried some combinations of -march=..[+[no]fp] and -mfpu=... but they seemed OK and the tests passed. ARM::getFPUFeatures gets used in quite a few places though so something else might be going wrong. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
Stylie777 wrote: I have just pushed an update for the Unit Tests that should turn the CI green. This is now ready for re-review @davemgreen https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/7] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d6a586e1f247b..79b54e6b04330 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12971,7 +12971,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/4] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d6a586e1f247b..79b54e6b04330 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12971,7 +12971,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/6] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d6a586e1f247b..79b54e6b04330 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12971,7 +12971,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
-ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
+ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
Stylie777 wrote:
I am posing this a question rather than a statement as I am not sure of the
answer, but could LLVM be taking the target features defined as a
`-target-feature` option over the features that come from the fpu? Reason I ask
is before this change, `-target-feature +neon` never appeared for targets when
I added `-###` to the command, but now they are. If neon is not defined for
that target, it passes `-target-feature -neon` because the ID of
`ARM::AEK_SIMD` is not included in the features from the
`ARMTargetFeatures.def` file.
That could explain why we need this change.
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
-ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
+ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
Stylie777 wrote:
So, yes this is needed. Because `simd` is now linked to `neon`, if it is not
explicitly defined for each Architecture/CPU that supports NEON,
`-target-feature -neon` is passed by the compiler, disabling the feature. This
is because when it parses the `.def` file, that CPU/Architecture is told SIMD
is not supported as it is not included. I think it was a fluke it worked
before, and it picked it up from the FPU in the backend, but the responsibility
for determining if Neon is supported now lies with the front end with this
change, so we need to explicitly define it. I will provide an update in due
course that defines it for the Architecture's and CPU's that support NEON and
tests to support it. I will also update the description of the PR to state this.
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
-ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
+ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
Stylie777 wrote:
We support NEON on Cortex-R52 by default, rather than as an optional feature.
When `+simd`/`+nosimd` was linked to `+neon` and `-neon`, I found that once the
link between `simd` and `neon` was made, it was not passing `-target-feature
+neon` as part of the cc1 command.
Let me investigate and see if we need this change or if it can determine
`+neon` from the FPU, if not we may need to add `AEK_SIMD` to everything that
should support it as it may not just be cortex-r52 that is affected here.
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 commented: Thanks for the comments @davemgreen. I need to do some more investigation here as I think there is more going wrong than I initially thought after this change is introduced. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
-ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
+ARM_CPU_NAME("cortex-r52plus", ARMV8R, FK_NEON_FP_ARMV8, false, ARM::AEK_SIMD)
davemgreen wrote:
Why are these two special-cased to include AEK_SIMD, unlike all the other cpus
where it comes from FK_NEON_FP_ARMV8? Am I right in saying that removing it
would not affect how the command line for -mcpu=cortex-r52 behaves? Or does it
change the defaults in some way?
https://github.com/llvm/llvm-project/pull/130623
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[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however this will now disable NEON instructions being generated. The `simd` option is +also now printed when the `--print-supported-extensions` option is used. davemgreen wrote: This looks like it should be in the clang release notes, not the llvm part? It looks like it is talking about altering the clang interface via +nosimd and print-supported-extensions. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jack Styles (Stylie777)
Changes
`+simd` and `+nosimd` are used to emable or disable NEON Instructions
when compiling for AArch32 Targets. However, up until now, using these
has not been possible. To enable this, these options are mapped to the
relevant LLVM backend option (`+neon` and `-neon`) so it can be both
enabled and disabled successfully by the user.
Tests have been added to ensure this behaviour is maintained in the future,
along with updates to existing tests as behaviour has now changed relating
to the use of `+simd` and `+nosimd`.
As `simd` has been mapped within the ARMTargetParser.def, support for this
extension is also added for the `--print-support-extensions` command when
the target is AArch32. This will print the `simd` option, along with the
description that relates to the Neon feature. This previously was not
possible as `simd` did not have a related Feature or Negative Feature.
To make this functional as intended, MVE and MVE.FP now rely on their own
Enum identifier, rather than `AEK_SIMD`. While SIMD does refer to both
Neon and Helium technologies, in terms of command line options, SIMD relates
to Neon. Helium relates to MVE and MVE.FP. The Enum now reflects this too.
---
Full diff: https://github.com/llvm/llvm-project/pull/130623.diff
9 Files Affected:
- (modified) clang/test/Driver/print-supported-extensions-arm.c (+1)
- (modified) clang/test/Preprocessor/arm-target-features.c (+8)
- (modified) llvm/docs/ReleaseNotes.md (+3)
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+8-8)
- (modified) llvm/include/llvm/TargetParser/ARMTargetParser.h (+1)
- (modified) llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp (+1-1)
- (modified) llvm/lib/TargetParser/ARMTargetParser.cpp (+4)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+10-11)
``diff
diff --git a/clang/test/Driver/print-supported-extensions-arm.c
b/clang/test/Driver/print-supported-extensions-arm.c
index 0dc2e9fc69738..407adc5e9c384 100644
--- a/clang/test/Driver/print-supported-extensions-arm.c
+++ b/clang/test/Driver/print-supported-extensions-arm.c
@@ -12,6 +12,7 @@
// CHECK-NEXT: dsp Supports DSP instructions in ARM and/or
Thumb2
// CHECK-NEXT: mve Support M-Class Vector Extension with
integer ops
// CHECK-NEXT: mve.fp Support M-Class Vector Extension with
integer and floating ops
+// CHECK-NEXT: simdEnable NEON instructions
// CHECK-NEXT: fp16Enable half-precision floating point
// CHECK-NEXT: ras Enable Reliability, Availability and
Serviceability extensions
// CHECK-NEXT: fp16fml Enable full half-precision floating
point fml instructions
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 94dcfc2424bb1..b36dd1765b6de 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1027,3 +1027,11 @@
// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
// CHECK-R52-NOT: #define __ARM_NEON 1
// CHECK-R52-NOT: #define __ARM_NEON__
+
+// Check that on AArch32 appropriate targets, +nosimd correctly disables NEON
instructions.
+// RUN: %clang -target arm-none-eabi -march=armv8-a+nosimd -mfloat-abi=hard
-x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-NOSIMD %s
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd -mfloat-abi=hard
-x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-NOSIMD %s
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-a57+nosimd -mfloat-abi=hard
-x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-NOSIMD %s
+// CHECK-NOSIMD-NOT: #define __ARM_NEON 1
+// CHECK-NOSIMD-NOT: #define __ARM_NEON_FP 0x6
+// CHECK-NOSIMD-NOT: #define __ARM_NEON__ 1
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index d7a80ae93aa34..43ed754183be7 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however will now disable NEON instructions being generated.
The `simd` is also now
+printed when the `--print-supported-extensions` option is used..
Changes to the AVR Backend
--
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e8837cb89ed29 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,12 +224,12 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD,
"+dotprod", "-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
jthackray wrote: typo in commit message: s/emable/enable/ https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
DavidSpickett wrote: > used to emable or disable enable https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
Stylie777 wrote: The description is fixed. Thanks @DavidSpickett and @jthackray (I will publish a commit to your improvements once I have a green CI so I know all is good). https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
Stylie777 wrote: Thanks @jthackray. The CI Failure seems to be unrelated. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/jthackray approved this pull request. Thanks for the fixes. LGTM now. https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however will now disable NEON instructions being generated. The `simd` is also now +printed when the `--print-supported-extensions` option is used.. Stylie777 wrote: Done https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend Changes to the ARM Backend -- +* The `+nosimd` attribute is now fully supported. Previously, this had no effect when being used with +AArch32 targets, however will now disable NEON instructions being generated. The `simd` is also now Stylie777 wrote: Done https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From d6772d64ff6fd515621c073b6545c40e918893b5 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/3] [NFC][ARM] Split SIMD identifier away from MVE
Previously, the use of MVE or MVE.FP would be defined
by using the `ARM::AEK_SIMD` identifier. SIMD relates to
the Cortex-A and Cortex-R extension that enables NEON
instructions, which is called MVE for Cortex-M. To enable the
linking of `+simd` and `+nosimd` to `+neon` and `-neon`
when using clang, MVE and MVE.FP can now be defined
using a unique enum identifier, rather than using the existing
identifier for SIMD.
This was originally planned to be merged as part of #130296 but
the changes made `+nosimd` an invalid argument, which, while not
having any functionality, was allowed in previous versions of
LLVM. To avoid regressions being introduced, this has been
combined with the fix for `+nosimd` on AArch32.
---
llvm/include/llvm/TargetParser/ARMTargetParser.def | 10 +-
llvm/include/llvm/TargetParser/ARMTargetParser.h | 1 +
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 +-
llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp | 2 +-
llvm/unittests/TargetParser/TargetParserTest.cpp | 6 +++---
5 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def
b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index 6b96c3e83c8c4..e515ab665d117 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -224,8 +224,8 @@ ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod",
"-dotprod")
ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp")
ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {})
ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {})
-ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve")
-ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_MVE), "+mve", "-mve")
+ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
"+mve.fp", "-mve.fp")
ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {})
ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {})
@@ -345,12 +345,12 @@ ARM_CPU_NAME("cortex-m33", ARMV8MMainline,
FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false,
ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16))
ARM_CPU_NAME("cortex-m85", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-m52", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
- (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16 |
+ (ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP | ARM::AEK_FP16 |
ARM::AEK_RAS | ARM::AEK_PACBTI))
ARM_CPU_NAME("cortex-a32", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
ARM_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
ARM::AEK_CRC)
diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.h
b/llvm/include/llvm/TargetParser/ARMTargetParser.h
index 5dbcfd3d2d693..b2403f42f1b79 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.h
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.h
@@ -61,6 +61,7 @@ enum ArchExtKind : uint64_t {
AEK_CDECP6 = 1 << 28,
AEK_CDECP7 = 1 << 29,
AEK_PACBTI = 1 << 30,
+ AEK_MVE = 1ULL << 31,
// Unsupported extensions.
AEK_OS = 1ULL << 59,
AEK_IWMMXT = 1ULL << 60,
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index d6a586e1f247b..79b54e6b04330 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -12971,7 +12971,7 @@ bool ARMAsmParser::enableArchExtFeature(StringRef Name,
SMLoc &ExtLoc) {
{ARM::AEK_CRYPTO,
{Feature_HasV8Bit},
{ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8}},
- {(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP),
+ {(ARM::AEK_DSP | ARM::AEK_MVE | ARM::AEK_FP),
{Feature_HasV8_1MMainlineBit},
{ARM::HasMVEFloatOps}},
{ARM::AEK_FP,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
b/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
index b0fa03a35ec04..632dbebf58f04 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp
+++ b/
[clang] [llvm] [ARM][Clang] Make `+nosimd` functional for AArch32 Targets (PR #130623)
https://github.com/Stylie777 edited https://github.com/llvm/llvm-project/pull/130623 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
