[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-02-04 Thread Jack Styles via cfe-commits 

Stylie777 wrote:

I don't believe the above CI test failure to be related. This change targets 
ARM. This is an unchanged architecture.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-02-04 Thread LLVM Continuous Integration via cfe-commits 

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder 
`openmp-offload-amdgpu-runtime` running on `omp-vega20-0` while building 
`clang,llvm` at step 7 "Add check check-offload".

Full details are available at: 
https://lab.llvm.org/buildbot/#/builders/30/builds/15201


Here is the relevant piece of the build log for the reference

```
Step 7 (Add check check-offload) failure: test (failure)
...
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: offloading/bug50022.cpp 
(999 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: offloading/bug53727.cpp 
(1000 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: offloading/test_libc.cpp 
(1001 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: offloading/wtime.c (1002 
of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu :: offloading/bug49021.cpp (1003 
of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu :: 
offloading/std_complex_arithmetic.cpp (1004 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: 
offloading/complex_reduction.cpp (1005 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: 
offloading/std_complex_arithmetic.cpp (1006 of 1008)
PASS: libomptarget :: x86_64-unknown-linux-gnu-LTO :: offloading/bug49021.cpp 
(1007 of 1008)
TIMEOUT: libomptarget :: amdgcn-amd-amdhsa :: 
offloading/parallel_offloading_map.cpp (1008 of 1008)
 TEST 'libomptarget :: amdgcn-amd-amdhsa :: 
offloading/parallel_offloading_map.cpp' FAILED 
Exit Code: -9
Timeout: Reached timeout of 100 seconds

Command Output (stdout):
--
# RUN: at line 1
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/clang++ 
-fopenmp-I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 -L /home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
  -nogpulib 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib 
 -fopenmp-targets=amdgcn-amd-amdhsa 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/parallel_offloading_map.cpp
 -o 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/parallel_offloading_map.cpp.tmp
 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a
 && 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/parallel_offloading_map.cpp.tmp
 | 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/FileCheck 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/parallel_offloading_map.cpp
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./bin/clang++ 
-fopenmp -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test -I 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 -L /home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib -L 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -nogpulib 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload
 
-Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/openmp/runtime/src
 -Wl,-rpath,/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib 
-fopenmp-targets=amdgcn-amd-amdhsa 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.src/offload/test/offloading/parallel_offloading_map.cpp
 -o 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/parallel_offloading_map.cpp.tmp
 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/./lib/libomptarget.devicertl.a
# note: command had no output on stdout or stderr
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-runtime/llvm.build/runtimes/runtimes-bins/offload/test/amdgcn-amd-amdhsa/offloading/Output/parallel_offloading_map.cpp.tmp
# note: command had no output on stdout or stderr
# error: command failed with exit status: -9
# error: command reached timeout: True
# executed command: 
/home/ompworker/bbot/openmp-offload-amdgpu-

[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-02-03 Thread Jack Styles via cfe-commits 


@@ -1013,3 +1013,41 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// CHECK-R52-NOT: #define __ARM_NEON 1
+// CHECK-R52-NOT: #define __ARM_NEON__
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
+// CHECK-R52PLUS-NOT: #define __ARM_NEON 1
+// CHECK-R52PLUS-NOT: #define __ARM_NEON__
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nofp.dp -mfloat-abi=hard 
-x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52-ONLY-NO-FP-DP %s
+// CHECK-R52-ONLY-NO-FP-DP: #define __ARM_FEATURE_FMA 1

Stylie777 wrote:

I have updated the tests to use the same check lines. Will merge after a Green 
CI run. Thanks for the review.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-02-03 Thread Jack Styles via cfe-commits 

https://github.com/Stylie777 updated 
https://github.com/llvm/llvm-project/pull/124935

>From 8da3a78692c4c0c4d4a47610d7b705f1a55f6f14 Mon Sep 17 00:00:00 2001
From: Jack Styles 
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/4] [ARM] Ensure FPU Selection can select mode correctly

Previously, when selecting a Single Precision FPU, LLVM would
ensure all elements of the Candidate FPU matched the InputFPU
that was given. However, for cases such as Cortex-R52, there
are FPU options where not all fields match exactly, for example
NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly,
removing the requirement for Neon Support and Restrictions
for the Candidate FPU to be the same as the InputFPU. For
instances where a Single Precision FPU is used, SIMD will
be disabled regardless of if `+nosimd` is passed as an option.
This is because there is no Single Precision FPU that can
support this feature.
---
 clang/test/Preprocessor/arm-target-features.c | 16 
 llvm/lib/TargetParser/ARMTargetParser.cpp |  9 +++
 llvm/test/MC/ARM/cortex-r52-nofp.s|  9 +++
 .../TargetParser/TargetParserTest.cpp | 26 +++
 4 files changed, 55 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/ARM/cortex-r52-nofp.s

diff --git a/clang/test/Preprocessor/arm-target-features.c 
b/clang/test/Preprocessor/arm-target-features.c
index ecf9d7eb5c19c9d..7395ed8b57f845b 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp 
b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6ca62c97f6..8f9753775c204a6 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind 
InputFPUKind) {
   if (!ARM::isDoublePrecision(InputFPU.Restriction))
 return InputFPUKind;
 
-  // Otherwise, look for an FPU entry with all the same fields, except
-  // that it does not support double precision.
+  // Otherwise, look for an FPU entry that has the same FPUVer
+  // and is not Double Precision. We want to allow for changing of
+  // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+  // select between SP Only and Full DP modes.
   for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
-CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
-ARM::has32Regs(CandidateFPU.Restriction) ==
-ARM::has32Regs(InputFPU.Restriction) &&
 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
   return CandidateFPU.ID;
 }
diff --git a/llvm/test/MC/ARM/cortex-r52-nofp.s 
b/llvm/test/MC/ARM/cortex-r52-nofp.s
new file mode 100644
index 000..cc72cecd1311523
--- /dev/null
+++ b/llvm/test/MC/ARM/cortex-r52-nofp.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=+nosimd+nofp.dp 
%s -o - | FileCheck %s -check-prefix=CHECK-NO-FP
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s 
-check-prefix=CHECK-FP
+
+.text
+vadd.f32 s0, s1, s2
+@ CHECK-NO-FP: vadd.f32 s0, s1, s2
+@ CHECK-FP: vadd.f32 s0, s1, s2
+@ CHECK-NOT-NO-FP: error: instruction requires: VPF2
+@ CHECK-NOT-FP: error: instruction requires: VPF2
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index c594d38b50b22ed..48730578692539a 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h

[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Oliver Stannard via cfe-commits 

https://github.com/ostannard edited 
https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Oliver Stannard via cfe-commits 


@@ -1013,3 +1013,41 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// CHECK-R52-NOT: #define __ARM_NEON 1
+// CHECK-R52-NOT: #define __ARM_NEON__
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
+// CHECK-R52PLUS-NOT: #define __ARM_NEON 1
+// CHECK-R52PLUS-NOT: #define __ARM_NEON__
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nofp.dp -mfloat-abi=hard 
-x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52-ONLY-NO-FP-DP %s
+// CHECK-R52-ONLY-NO-FP-DP: #define __ARM_FEATURE_FMA 1

ostannard wrote:

If the expected output is the same (it looks like it is), you can use the same 
`--check-prefix` option, instead of duplicating the `CHECK` lines.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Oliver Stannard via cfe-commits 

https://github.com/ostannard approved this pull request.

LGTM with one change to the tests, no need for re-review.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Jack Styles via cfe-commits 


@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s

Stylie777 wrote:

I have updated the tests and added lines into each one to ensure that SIMD is 
disabled.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Jack Styles via cfe-commits 

https://github.com/Stylie777 updated 
https://github.com/llvm/llvm-project/pull/124935

>From 8da3a78692c4c0c4d4a47610d7b705f1a55f6f14 Mon Sep 17 00:00:00 2001
From: Jack Styles 
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/3] [ARM] Ensure FPU Selection can select mode correctly

Previously, when selecting a Single Precision FPU, LLVM would
ensure all elements of the Candidate FPU matched the InputFPU
that was given. However, for cases such as Cortex-R52, there
are FPU options where not all fields match exactly, for example
NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly,
removing the requirement for Neon Support and Restrictions
for the Candidate FPU to be the same as the InputFPU. For
instances where a Single Precision FPU is used, SIMD will
be disabled regardless of if `+nosimd` is passed as an option.
This is because there is no Single Precision FPU that can
support this feature.
---
 clang/test/Preprocessor/arm-target-features.c | 16 
 llvm/lib/TargetParser/ARMTargetParser.cpp |  9 +++
 llvm/test/MC/ARM/cortex-r52-nofp.s|  9 +++
 .../TargetParser/TargetParserTest.cpp | 26 +++
 4 files changed, 55 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/ARM/cortex-r52-nofp.s

diff --git a/clang/test/Preprocessor/arm-target-features.c 
b/clang/test/Preprocessor/arm-target-features.c
index ecf9d7eb5c19c9..7395ed8b57f845 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp 
b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6ca62c97f..8f9753775c204a 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind 
InputFPUKind) {
   if (!ARM::isDoublePrecision(InputFPU.Restriction))
 return InputFPUKind;
 
-  // Otherwise, look for an FPU entry with all the same fields, except
-  // that it does not support double precision.
+  // Otherwise, look for an FPU entry that has the same FPUVer
+  // and is not Double Precision. We want to allow for changing of
+  // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+  // select between SP Only and Full DP modes.
   for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
-CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
-ARM::has32Regs(CandidateFPU.Restriction) ==
-ARM::has32Regs(InputFPU.Restriction) &&
 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
   return CandidateFPU.ID;
 }
diff --git a/llvm/test/MC/ARM/cortex-r52-nofp.s 
b/llvm/test/MC/ARM/cortex-r52-nofp.s
new file mode 100644
index 00..cc72cecd131152
--- /dev/null
+++ b/llvm/test/MC/ARM/cortex-r52-nofp.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=+nosimd+nofp.dp 
%s -o - | FileCheck %s -check-prefix=CHECK-NO-FP
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s 
-check-prefix=CHECK-FP
+
+.text
+vadd.f32 s0, s1, s2
+@ CHECK-NO-FP: vadd.f32 s0, s1, s2
+@ CHECK-FP: vadd.f32 s0, s1, s2
+@ CHECK-NOT-NO-FP: error: instruction requires: VPF2
+@ CHECK-NOT-FP: error: instruction requires: VPF2
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index c594d38b50b22e..48730578692539 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
+#incl

[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-30 Thread Oliver Stannard via cfe-commits 


@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s

ostannard wrote:

We should also test `-mcpu=cortex-r52+nofp.dp` (without `+nosimd`), this patch 
looks like it will also cause AdvSIMD to be disabled there, which I think is 
the right thing to do because there is no SP-only FPU with SIMD.

https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-29 Thread Jack Styles via cfe-commits 

https://github.com/Stylie777 updated 
https://github.com/llvm/llvm-project/pull/124935

>From 1b12ad277c63e707c1b4268fc46f942349bbb1d9 Mon Sep 17 00:00:00 2001
From: Jack Styles 
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/2] [ARM] Ensure FPU Selection can select mode correctly

Previously, when selecting a Single Precision FPU, LLVM would
ensure all elements of the Candidate FPU matched the InputFPU
that was given. However, for cases such as Cortex-R52, there
are FPU options where not all fields match exactly, for example
NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly,
removing the requirement for Neon Support and Restrictions
for the Candidate FPU to be the same as the InputFPU.
---
 clang/test/Preprocessor/arm-target-features.c | 16 
 llvm/lib/TargetParser/ARMTargetParser.cpp |  9 +++
 llvm/test/MC/ARM/cortex-r52-nofp.s|  9 +++
 .../TargetParser/TargetParserTest.cpp | 26 +++
 4 files changed, 55 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/ARM/cortex-r52-nofp.s

diff --git a/clang/test/Preprocessor/arm-target-features.c 
b/clang/test/Preprocessor/arm-target-features.c
index ecf9d7eb5c19c9..7395ed8b57f845 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp 
b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6ca62c97f..8f9753775c204a 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind 
InputFPUKind) {
   if (!ARM::isDoublePrecision(InputFPU.Restriction))
 return InputFPUKind;
 
-  // Otherwise, look for an FPU entry with all the same fields, except
-  // that it does not support double precision.
+  // Otherwise, look for an FPU entry that has the same FPUVer
+  // and is not Double Precision. We want to allow for changing of
+  // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+  // select between SP Only and Full DP modes.
   for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
-CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
-ARM::has32Regs(CandidateFPU.Restriction) ==
-ARM::has32Regs(InputFPU.Restriction) &&
 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
   return CandidateFPU.ID;
 }
diff --git a/llvm/test/MC/ARM/cortex-r52-nofp.s 
b/llvm/test/MC/ARM/cortex-r52-nofp.s
new file mode 100644
index 00..cc72cecd131152
--- /dev/null
+++ b/llvm/test/MC/ARM/cortex-r52-nofp.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=+nosimd+nofp.dp 
%s -o - | FileCheck %s -check-prefix=CHECK-NO-FP
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s 
-check-prefix=CHECK-FP
+
+.text
+vadd.f32 s0, s1, s2
+@ CHECK-NO-FP: vadd.f32 s0, s1, s2
+@ CHECK-FP: vadd.f32 s0, s1, s2
+@ CHECK-NOT-NO-FP: error: instruction requires: VPF2
+@ CHECK-NOT-FP: error: instruction requires: VPF2
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index c594d38b50b22e..48730578692539 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FormatVariadic.h"
@@ -2085,4 +2086,29 @@ INSTANTIATE_TEST_SUITE_P(
 AAr

[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-29 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 12cdf4330d32ce073f88dfaa1ab9a32327b9ef38 
1b12ad277c63e707c1b4268fc46f942349bbb1d9 --extensions c,cpp -- 
clang/test/Preprocessor/arm-target-features.c 
llvm/lib/TargetParser/ARMTargetParser.cpp 
llvm/unittests/TargetParser/TargetParserTest.cpp
``





View the diff from clang-format here.


``diff
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 4873057869..1f346c9a84 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -2097,16 +2097,41 @@ struct CheckFindSinglePrecisionFpuTest {
 
 TEST(TargetParserTest, checkFindSinglePrecisionFPU) {
   CheckFindSinglePrecisionFpuTest tests[] = {
-{"cortex-r4f", ARM::ArchKind::ARMV7R, "nofp.dp", {}, ARM::FK_INVALID, 
ARM::FK_VFPV3XD},
-{"cortex-r7", ARM::ArchKind::ARMV7R, "nofp.dp", {}, ARM::FK_INVALID, 
ARM::FK_VFPV3XD_FP16},
-{"cortex-a7", ARM::ArchKind::ARMV7A, "nofp.dp", {}, ARM::FK_INVALID, 
ARM::FK_FPV4_SP_D16},
-{"cortex-r52", ARM::ArchKind::ARMV8R, "nofp.dp", {}, ARM::FK_INVALID, 
ARM::FK_FPV5_SP_D16},
-{"cortex-m55", ARM::ArchKind::ARMV8_1MMainline, "nofp.dp", {}, 
ARM::FK_INVALID, ARM::FK_FP_ARMV8_FULLFP16_SP_D16}
-  };
+  {"cortex-r4f",
+   ARM::ArchKind::ARMV7R,
+   "nofp.dp",
+   {},
+   ARM::FK_INVALID,
+   ARM::FK_VFPV3XD},
+  {"cortex-r7",
+   ARM::ArchKind::ARMV7R,
+   "nofp.dp",
+   {},
+   ARM::FK_INVALID,
+   ARM::FK_VFPV3XD_FP16},
+  {"cortex-a7",
+   ARM::ArchKind::ARMV7A,
+   "nofp.dp",
+   {},
+   ARM::FK_INVALID,
+   ARM::FK_FPV4_SP_D16},
+  {"cortex-r52",
+   ARM::ArchKind::ARMV8R,
+   "nofp.dp",
+   {},
+   ARM::FK_INVALID,
+   ARM::FK_FPV5_SP_D16},
+  {"cortex-m55",
+   ARM::ArchKind::ARMV8_1MMainline,
+   "nofp.dp",
+   {},
+   ARM::FK_INVALID,
+   ARM::FK_FP_ARMV8_FULLFP16_SP_D16}};
 
   for (auto X : tests) {
 ARM::FPUKind FPU = X.Fpu;
-EXPECT_TRUE(ARM::appendArchExtFeatures(X.Cpu, X.Arch, X.Archext, 
X.Features, FPU));
+EXPECT_TRUE(
+ARM::appendArchExtFeatures(X.Cpu, X.Arch, X.Archext, X.Features, FPU));
 EXPECT_EQ(FPU, X.Output);
   }
 }

``




https://github.com/llvm/llvm-project/pull/124935
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[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-29 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-arm

Author: Jack Styles (Stylie777)


Changes

Previously, when selecting a Single Precision FPU, LLVM would ensure all 
elements of the Candidate FPU matched the InputFPU that was given. However, for 
cases such as Cortex-R52, there are FPU options where not all fields match 
exactly, for example NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly, removing the 
requirement for Neon Support and Restrictions for the Candidate FPU to be the 
same as the InputFPU.

---
Full diff: https://github.com/llvm/llvm-project/pull/124935.diff


4 Files Affected:

- (modified) clang/test/Preprocessor/arm-target-features.c (+16) 
- (modified) llvm/lib/TargetParser/ARMTargetParser.cpp (+4-5) 
- (added) llvm/test/MC/ARM/cortex-r52-nofp.s (+9) 
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+26) 


``diff
diff --git a/clang/test/Preprocessor/arm-target-features.c 
b/clang/test/Preprocessor/arm-target-features.c
index ecf9d7eb5c19c9..7395ed8b57f845 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp 
b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6ca62c97f..8f9753775c204a 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind 
InputFPUKind) {
   if (!ARM::isDoublePrecision(InputFPU.Restriction))
 return InputFPUKind;
 
-  // Otherwise, look for an FPU entry with all the same fields, except
-  // that it does not support double precision.
+  // Otherwise, look for an FPU entry that has the same FPUVer
+  // and is not Double Precision. We want to allow for changing of
+  // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+  // select between SP Only and Full DP modes.
   for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
-CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
-ARM::has32Regs(CandidateFPU.Restriction) ==
-ARM::has32Regs(InputFPU.Restriction) &&
 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
   return CandidateFPU.ID;
 }
diff --git a/llvm/test/MC/ARM/cortex-r52-nofp.s 
b/llvm/test/MC/ARM/cortex-r52-nofp.s
new file mode 100644
index 00..cc72cecd131152
--- /dev/null
+++ b/llvm/test/MC/ARM/cortex-r52-nofp.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=+nosimd+nofp.dp 
%s -o - | FileCheck %s -check-prefix=CHECK-NO-FP
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s 
-check-prefix=CHECK-FP
+
+.text
+vadd.f32 s0, s1, s2
+@ CHECK-NO-FP: vadd.f32 s0, s1, s2
+@ CHECK-FP: vadd.f32 s0, s1, s2
+@ CHECK-NOT-NO-FP: error: instruction requires: VPF2
+@ CHECK-NOT-FP: error: instruction requires: VPF2
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index c594d38b50b22e..48730578692539 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/Support/ARMBuildAttributes.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FormatVariadic.h"
@@ -2085,4 +2086,29 @@ INSTANTIATE_TEST_SUITE_P(
 AArch64ExtensionDependenciesBaseCPUTestFixture,
 ::testing::ValuesIn(AArch64ExtensionDependenciesCPUData));
 
+struct CheckFindSinglePrecisionFpuTest {
+  StringRef Cpu;
+  ARM::ArchKind Arch;
+  Strin

[clang] [llvm] [ARM] Ensure FPU Selection can select mode correctly (PR #124935)

2025-01-29 Thread Jack Styles via cfe-commits 

https://github.com/Stylie777 created 
https://github.com/llvm/llvm-project/pull/124935

Previously, when selecting a Single Precision FPU, LLVM would ensure all 
elements of the Candidate FPU matched the InputFPU that was given. However, for 
cases such as Cortex-R52, there are FPU options where not all fields match 
exactly, for example NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly, removing the 
requirement for Neon Support and Restrictions for the Candidate FPU to be the 
same as the InputFPU.

>From 1b12ad277c63e707c1b4268fc46f942349bbb1d9 Mon Sep 17 00:00:00 2001
From: Jack Styles 
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH] [ARM] Ensure FPU Selection can select mode correctly

Previously, when selecting a Single Precision FPU, LLVM would
ensure all elements of the Candidate FPU matched the InputFPU
that was given. However, for cases such as Cortex-R52, there
are FPU options where not all fields match exactly, for example
NEON Support or Restrictions on the Registers available.

This change ensures that LLVM can select the FPU correctly,
removing the requirement for Neon Support and Restrictions
for the Candidate FPU to be the same as the InputFPU.
---
 clang/test/Preprocessor/arm-target-features.c | 16 
 llvm/lib/TargetParser/ARMTargetParser.cpp |  9 +++
 llvm/test/MC/ARM/cortex-r52-nofp.s|  9 +++
 .../TargetParser/TargetParserTest.cpp | 26 +++
 4 files changed, 55 insertions(+), 5 deletions(-)
 create mode 100644 llvm/test/MC/ARM/cortex-r52-nofp.s

diff --git a/clang/test/Preprocessor/arm-target-features.c 
b/clang/test/Preprocessor/arm-target-features.c
index ecf9d7eb5c19c9..7395ed8b57f845 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -1013,3 +1013,19 @@
 // CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E 
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
 // CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus correctly enable the `fpv5-sp-d16` FPU when 
compiling for the SP only version of the CPU.
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52 %s
+// CHECK-R52: #define __ARM_FEATURE_FMA 1
+// CHECK-R52: #define __ARM_FP 0x6
+// CHECK-R52: #define __ARM_FPV5__ 1
+// CHECK-R52: #define __ARM_VFPV2__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52-NEXT: #define __ARM_VFPV4__ 1
+// RUN: %clang -target arm-none-eabi -mcpu=cortex-r52plus+nosimd+nofp.dp 
-mfloat-abi=hard -x c -E -dM -o - %s | FileCheck -check-prefix=CHECK-R52PLUS %s
+// CHECK-R52PLUS: #define __ARM_FEATURE_FMA 1
+// CHECK-R52PLUS: #define __ARM_FP 0x6
+// CHECK-R52PLUS: #define __ARM_FPV5__ 1
+// CHECK-R52PLUS: #define __ARM_VFPV2__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV3__ 1
+// CHECK-R52PLUS-NEXT: #define __ARM_VFPV4__ 1
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp 
b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 9bcfa6ca62c97f..8f9753775c204a 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -403,13 +403,12 @@ static ARM::FPUKind findSinglePrecisionFPU(ARM::FPUKind 
InputFPUKind) {
   if (!ARM::isDoublePrecision(InputFPU.Restriction))
 return InputFPUKind;
 
-  // Otherwise, look for an FPU entry with all the same fields, except
-  // that it does not support double precision.
+  // Otherwise, look for an FPU entry that has the same FPUVer
+  // and is not Double Precision. We want to allow for changing of
+  // NEON Support and Restrictions so CPU's such as Cortex-R52 can
+  // select between SP Only and Full DP modes.
   for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
 if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
-CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
-ARM::has32Regs(CandidateFPU.Restriction) ==
-ARM::has32Regs(InputFPU.Restriction) &&
 !ARM::isDoublePrecision(CandidateFPU.Restriction)) {
   return CandidateFPU.ID;
 }
diff --git a/llvm/test/MC/ARM/cortex-r52-nofp.s 
b/llvm/test/MC/ARM/cortex-r52-nofp.s
new file mode 100644
index 00..cc72cecd131152
--- /dev/null
+++ b/llvm/test/MC/ARM/cortex-r52-nofp.s
@@ -0,0 +1,9 @@
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=+nosimd+nofp.dp 
%s -o - | FileCheck %s -check-prefix=CHECK-NO-FP
+@ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s 
-check-prefix=CHECK-FP
+
+.text
+vadd.f32 s0, s1, s2
+@ CHECK-NO-FP: vadd.f32 s0, s1, s2
+@ CHECK-FP: vadd.f32 s0, s1, s2
+@ CHECK-NOT-NO-FP: error: instruction requires: VPF2
+@ CHECK-NOT-FP: error: instruction requires: VPF2
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp 
b/llvm/unittests/TargetParser/TargetParserTest.cpp
ind