[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-23 Thread Phoebe Wang via cfe-commits 

https://github.com/phoebewang approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-23 Thread Phoebe Wang via cfe-commits 

https://github.com/phoebewang closed 
https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Mikołaj Piróg via cfe-commits 

https://github.com/mikolaj-pirog edited 
https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -203,180 +203,180 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U, 
__m256i __A, __m256h __B
   return _mm256_maskz_cvtbiassph_phf8(__U, __A, __B);
 }
 
-__m128i test_mm_cvtne2ph_pbf8(__m128h __A, __m128h __B) {
-  // CHECK-LABEL: @test_mm_cvtne2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8128(
-  return _mm_cvtne2ph_pbf8(__A, __B);
+__m128i test_mm_cvt2ph_bf8(__m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_cvt2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8128(
+  return _mm_cvt2ph_bf8(__A, __B);
 }
 
-__m128i test_mm_mask_cvtne2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, 
__m128h __B) {
-  // CHECK-LABEL: @test_mm_mask_cvtne2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8128(
+__m128i test_mm_mask_cvt2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, 
__m128h __B) {
+  // CHECK-LABEL: @test_mm_mask_cvt2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8128(
   // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
   // CHECK: ret <2 x i64> %{{.*}}
-  return _mm_mask_cvtne2ph_pbf8(__W, __U, __A, __B);
+  return _mm_mask_cvt2ph_bf8(__W, __U, __A, __B);
 }
 
-__m128i test_mm_maskz_cvtne2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
-  // CHECK-LABEL: @test_mm_maskz_cvtne2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8128(
+__m128i test_mm_maskz_cvt2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_maskz_cvt2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8128(
   // CHECK: zeroinitializer
   // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
-  return _mm_maskz_cvtne2ph_pbf8(__U, __A, __B);
+  return _mm_maskz_cvt2ph_bf8(__U, __A, __B);
 }
 
-__m256i test_mm256_cvtne2ph_pbf8(__m256h __A, __m256h __B) {
-  // CHECK-LABEL: @test_mm256_cvtne2ph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtne2ph2bf8256(
-  return _mm256_cvtne2ph_pbf8(__A, __B);
+__m256i test_mm256_cvt2ph_bf8(__m256h __A, __m256h __B) {
+  // CHECK-LABEL: @test_mm256_cvt2ph_bf8(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvt2ph2bf8256(
+  return _mm256_cvt2ph_bf8(__A, __B);
 }
 
-__m256i test_mm256_mask_cvtne2ph_pbf8(__m256i __W, __mmask16 __U, __m256h __A, 
__m256h __B) {
-  // CHECK-LABEL: @test_mm256_mask_cvtne2ph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtne2ph2bf8256(
+__m256i test_mm256_mask_cvt2ph_bf8(__m256i __W, __mmask16 __U, __m256h __A, 
__m256h __B) {
+  // CHECK-LABEL: @test_mm256_mask_cvt2ph_bf8(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvt2ph2bf8256(
   // CHECK: select <32 x i1> %{{.*}}, <32 x i8> %{{.*}}, <32 x i8> %{{.*}}
   // CHECK: ret <4 x i64> %{{.*}}
-  return _mm256_mask_cvtne2ph_pbf8(__W, __U, __A, __B);
+  return _mm256_mask_cvt2ph_bf8(__W, __U, __A, __B);
 }
 
-__m256i test_mm256_maskz_cvtne2ph_pbf8(__mmask16 __U, __m256h __A, __m256h 
__B) {
-  // CHECK-LABEL: @test_mm256_maskz_cvtne2ph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvtne2ph2bf8256(
+__m256i test_mm256_maskz_cvt2ph_bf8(__mmask16 __U, __m256h __A, __m256h __B) {
+  // CHECK-LABEL: @test_mm256_maskz_cvt2ph_bf8(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.vcvt2ph2bf8256(
   // CHECK: zeroinitializer
   // CHECK: select <32 x i1> %{{.*}}, <32 x i8> %{{.*}}, <32 x i8> %{{.*}}
-  return _mm256_maskz_cvtne2ph_pbf8(__U, __A, __B);
+  return _mm256_maskz_cvt2ph_bf8(__U, __A, __B);
 }
 
-__m128i test_mm_cvtnes2ph_pbf8(__m128h __A, __m128h __B) {
-  // CHECK-LABEL: @test_mm_cvtnes2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8s128(
-  return _mm_cvtnes2ph_pbf8(__A, __B);
+__m128i test_mm_cvts2ph_bf8(__m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_cvts2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8s128(
+  return _mm_cvts2ph_bf8(__A, __B);
 }
 
-__m128i test_mm_mask_cvtnes2ph_pbf8(__m128i __W, __mmask16 __U, __m128h __A, 
__m128h __B) {
-  // CHECK-LABEL: @test_mm_mask_cvtnes2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8s128(
+__m128i test_mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, 
__m128h __B) {
+  // CHECK-LABEL: @test_mm_mask_cvts2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8s128(
   // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
   // CHECK: ret <2 x i64> %{{.*}}
-  return _mm_mask_cvtnes2ph_pbf8(__W, __U, __A, __B);
+  return _mm_mask_cvts2ph_bf8(__W, __U, __A, __B);
 }
 
-__m128i test_mm_maskz_cvtnes2ph_pbf8(__mmask16 __U, __m128h __A, __m128h __B) {
-  // CHECK-LABEL: @test_mm_maskz_cvtnes2ph_pbf8(
-  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvtne2ph2bf8s128(
+__m128i test_mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
+  // CHECK-LABEL: @test_mm_maskz_cvts2ph_bf8(
+  // CHECK: call <16 x i8> @llvm.x86.avx10.vcvt2ph2bf8s128(
   // CHECK: zeroinitializer
   // CHECK: select <16 x i1> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> %{{.*}}
-  return _mm_maskz_cvtnes2ph_pbf8(__U,

[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -203,180 +203,180 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U, 
__m256i __A, __m256h __B
   return _mm256_maskz_cvtbiassph_phf8(__U, __A, __B);

phoebewang wrote:

ditto.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -113,92 +113,92 @@ __m256i test_mm512_maskz_cvtbiassph_phf8(__mmask32 __U, 
__m512i __A, __m512h __B
   return _mm512_maskz_cvtbiassph_phf8(__U, __A, __B);
 }

phoebewang wrote:

The tests above are still using `p`.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -205,175 +205,175 @@ __m128i test_mm256_maskz_cvtbiassph_phf8(__mmask16 __U, 
__m256i __A, __m256h __B
 
 __m128i test_mm_cvtne2ph_pbf8(__m128h __A, __m128h __B) {

phoebewang wrote:

Why the test cases are still using ne and p. The same below.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -420,143 +416,139 @@ _mm256_maskz_cvtnehf8_ph(__mmask16 __U, __m128i __A) {
   (__v16qi)__A, (__v16hf)(__m256h)_mm256_setzero_ph(), (__mmask16)__U);
 }
 
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_pbf8(__m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_bf8(__m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_mask_cvtneph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
+_mm_mask_cvtph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_maskz_cvtneph_pbf8(__mmask8 __U, __m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_128_mask(
+_mm_maskz_cvtph_bf8(__mmask8 __U, __m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
 }
 
-static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_cvtneph_pbf8(__m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
+static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtph_bf8(__m256h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtneph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
+_mm256_mask_cvtph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_maskz_cvtneph_pbf8(__mmask16 __U, __m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8_256_mask(
+_mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
 }
 
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtnesph_pbf8(__m128h __A) 
{
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_mask_cvtnesph_pbf8(__m128i __W, __mmask8 __U, __m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
+_mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_maskz_cvtnesph_pbf8(__mmask8 __U, __m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_128_mask(
+_mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
 }
 
-static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_cvtnesph_pbf8(__m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
+static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_bf8(__m256h __A) 
{
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtnesph_pbf8(__m128i __W, __mmask16 __U, __m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
+_mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS256
-_mm256_maskz_cvtnesph_pbf8(__mmask16 __U, __m256h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2bf8s_256_mask(
+_mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
   (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
 }
 
-static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtneph_phf8(__m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
+static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtph_hf8(__m128h __A) {
+  return (__m128i)__builtin_ia32_vcvtph2hf8_128_mask(
   (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
 }
 
 static __inline__ __m128i __DEFAULT_FN_ATTRS128
-_mm_mask_cvtneph_phf8(__m128i __W, __mmask8 __U, __m128h __A) {
-  return (__m128i)__builtin_ia32_vcvtneph2hf8_128_mask(
+_mm_mask_cvtph_hf8(_

[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -115,87 +115,87 @@ __m256i test_mm512_maskz_cvtbiassph_phf8(__mmask32 __U, 
__m512i __A, __m512h __B
 
 __m512i test_mm512_cvtne2ph_pbf8(__m512h __A, __m512h __B) {

phoebewang wrote:

Why the test cases are still using `ne` and `p`. The same below.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -221,73 +221,73 @@ __m512h test_mm512_maskz_cvtnehf8_ph(__mmask32 __A, 
__m256i __B) {
 
 __m256i test_mm512_cvtneph_pbf8(__m512h __A) {
   // CHECK-LABEL: @test_mm512_cvtneph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8512(
   return _mm512_cvtneph_pbf8(__A);
 }
 
 __m256i test_mm512_mask_cvtneph_pbf8(__m256i __A, __mmask32 __B, __m512h __C) {
   // CHECK-LABEL: @test_mm512_mask_cvtneph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8512(
   return _mm512_mask_cvtneph_pbf8(__A, __B, __C);
 }
 
 __m256i test_mm512_maskz_cvtneph_pbf8(__mmask32 __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_maskz_cvtneph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8512(
   return _mm512_maskz_cvtneph_pbf8(__A, __B);
 }
 
 __m256i test_mm512_cvtnesph_pbf8(__m512h __A) {
   // CHECK-LABEL: @test_mm512_cvtnesph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8s512(
   return _mm512_cvtnesph_pbf8(__A);
 }
 
 __m256i test_mm512_mask_cvtnesph_pbf8(__m256i __A, __mmask32 __B, __m512h __C) 
{
   // CHECK-LABEL: @test_mm512_mask_cvtnesph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8s512(
   return _mm512_mask_cvtnesph_pbf8(__A, __B, __C);
 }
 
 __m256i test_mm512_maskz_cvtnesph_pbf8(__mmask32 __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_maskz_cvtnesph_pbf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2bf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2bf8s512(
   return _mm512_maskz_cvtnesph_pbf8(__A, __B);
 }
 
 __m256i test_mm512_cvtneph_phf8(__m512h __A) {
   // CHECK-LABEL: @test_mm512_cvtneph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8512(
   return _mm512_cvtneph_phf8(__A);
 }
 
 __m256i test_mm512_mask_cvtneph_phf8(__m256i __A, __mmask32 __B, __m512h __C) {
   // CHECK-LABEL: @test_mm512_mask_cvtneph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8512(
   return _mm512_mask_cvtneph_phf8(__A, __B, __C);
 }
 
 __m256i test_mm512_maskz_cvtneph_phf8(__mmask32 __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_maskz_cvtneph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8512(
   return _mm512_maskz_cvtneph_phf8(__A, __B);
 }
 
 __m256i test_mm512_cvtnesph_phf8(__m512h __A) {
   // CHECK-LABEL: @test_mm512_cvtnesph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8s512(
   return _mm512_cvtnesph_phf8(__A);
 }
 
 __m256i test_mm512_mask_cvtnesph_phf8(__m256i __A, __mmask32 __B, __m512h __C) 
{
   // CHECK-LABEL: @test_mm512_mask_cvtnesph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8s512(
   return _mm512_mask_cvtnesph_phf8(__A, __B, __C);
 }
 
 __m256i test_mm512_maskz_cvtnesph_phf8(__mmask32 __A, __m512h __B) {
   // CHECK-LABEL: @test_mm512_maskz_cvtnesph_phf8(
-  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtneph2hf8s512(
+  // CHECK: call <32 x i8> @llvm.x86.avx10.mask.vcvtph2hf8s512(
   return _mm512_maskz_cvtnesph_phf8(__A, __B);
 }
 

phoebewang wrote:

ditto.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-21 Thread Phoebe Wang via cfe-commits 


@@ -231,75 +231,71 @@ _mm512_maskz_cvtnehf8_ph(__mmask32 __U, __m256i __A) {
   (__v32qi)__A, (__v32hf)(__m512h)_mm512_setzero_ph(), (__mmask32)__U);
 }
 
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtneph_pbf8(__m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
+static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_cvtph_bf8(__m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtneph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
+_mm512_mask_cvtph_bf8(__m256i __W, __mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_maskz_cvtneph_pbf8(__mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8_512_mask(
+_mm512_maskz_cvtph_bf8(__mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
 }
 
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtnesph_pbf8(__m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
+static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_cvtsph_bf8(__m512h __A) 
{
+  return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtnesph_pbf8(__m256i __W, __mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
+_mm512_mask_cvtsph_bf8(__m256i __W, __mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_maskz_cvtnesph_pbf8(__mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2bf8s_512_mask(
+_mm512_maskz_cvtsph_bf8(__mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2bf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
 }
 
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtneph_phf8(__m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
+static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_cvtph_hf8(__m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtneph_phf8(__m256i __W, __mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
+_mm512_mask_cvtph_hf8(__m256i __W, __mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_maskz_cvtneph_phf8(__mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8_512_mask(
+_mm512_maskz_cvtph_hf8(__mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2hf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
 }
 
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtnesph_phf8(__m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
+static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_cvtsph_hf8(__m512h __A) 
{
+  return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)-1);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtnesph_phf8(__m256i __W, __mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
+_mm512_mask_cvtsph_hf8(__m256i __W, __mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)__W, (__mmask32)__U);
 }
 
 static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_maskz_cvtnesph_phf8(__mmask32 __U, __m512h __A) {
-  return (__m256i)__builtin_ia32_vcvtneph2hf8s_512_mask(
+_mm512_maskz_cvtsph_hf8(__mmask32 __U, __m512h __A) {
+  return (__m256i)__builtin_ia32_vcvtph2hf8s_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_setzero_si256(), (__mmask32)__U);
 }
 

phoebewang wrote:

Remove `p` from below intrinsics.

https://github.com/llvm/llvm-project/pull/123656
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[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-20 Thread via cfe-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff 5139c90dfcacfba3d6ddc16ccb377a086abac7aa 
215174faae70da536e2f1ac6588daa97409c5b19 --extensions cpp,inc,h,c -- 
clang/lib/Headers/avx10_2_512convertintrin.h 
clang/lib/Headers/avx10_2convertintrin.h 
clang/test/CodeGen/X86/avx10_2_512convert-builtins.c 
clang/test/CodeGen/X86/avx10_2convert-builtins.c 
llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.h 
llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/TableGen/x86-fold-tables.inc
``





View the diff from clang-format here.


``diff
diff --git a/clang/lib/Headers/avx10_2_512convertintrin.h 
b/clang/lib/Headers/avx10_2_512convertintrin.h
index 2726a31dba..657330e110 100644
--- a/clang/lib/Headers/avx10_2_512convertintrin.h
+++ b/clang/lib/Headers/avx10_2_512convertintrin.h
@@ -137,14 +137,14 @@ _mm512_maskz_cvtbiassph_phf8(__mmask32 __U, __m512i __A, 
__m512h __B) {
   (__mmask32)__U);
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512
-_mm512_cvt2ph_bf8(__m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_cvt2ph_bf8(__m512h __A,
+  __m512h __B) 
{
   return (__m512i)__builtin_ia32_vcvt2ph2bf8_512((__v32hf)(__A),
-   (__v32hf)(__B));
+ (__v32hf)(__B));
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvt2ph_bf8(
-__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvt2ph_bf8(__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_selectb_512(
   (__mmask64)__U, (__v64qi)_mm512_cvt2ph_bf8(__A, __B), (__v64qi)__W);
 }
@@ -159,11 +159,11 @@ _mm512_maskz_cvt2ph_bf8(__mmask64 __U, __m512h __A, 
__m512h __B) {
 static __inline__ __m512i __DEFAULT_FN_ATTRS512
 _mm512_cvts2ph_bf8(__m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_vcvt2ph2bf8s_512((__v32hf)(__A),
-(__v32hf)(__B));
+  (__v32hf)(__B));
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvts2ph_bf8(
-__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts2ph_bf8(__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_selectb_512(
   (__mmask64)__U, (__v64qi)_mm512_cvts2ph_bf8(__A, __B), (__v64qi)__W);
 }
@@ -175,14 +175,14 @@ _mm512_maskz_cvts2ph_bf8(__mmask64 __U, __m512h __A, 
__m512h __B) {
   (__v64qi)(__m512i)_mm512_setzero_si512());
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512
-_mm512_cvt2ph_hf8(__m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_cvt2ph_hf8(__m512h __A,
+  __m512h __B) 
{
   return (__m512i)__builtin_ia32_vcvt2ph2hf8_512((__v32hf)(__A),
-   (__v32hf)(__B));
+ (__v32hf)(__B));
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvt2ph_hf8(
-__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvt2ph_hf8(__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_selectb_512(
   (__mmask64)__U, (__v64qi)_mm512_cvt2ph_hf8(__A, __B), (__v64qi)__W);
 }
@@ -197,11 +197,11 @@ _mm512_maskz_cvt2ph_hf8(__mmask64 __U, __m512h __A, 
__m512h __B) {
 static __inline__ __m512i __DEFAULT_FN_ATTRS512
 _mm512_cvts2ph_hf8(__m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_vcvt2ph2hf8s_512((__v32hf)(__A),
-(__v32hf)(__B));
+  (__v32hf)(__B));
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_mask_cvts2ph_hf8(
-__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvts2ph_hf8(__m512i __W, __mmask64 __U, __m512h __A, __m512h __B) {
   return (__m512i)__builtin_ia32_selectb_512(
   (__mmask64)__U, (__v64qi)_mm512_cvts2ph_hf8(__A, __B), (__v64qi)__W);
 }
@@ -231,8 +231,7 @@ _mm512_maskz_cvtnehf8_ph(__mmask32 __U, __m256i __A) {
   (__v32qi)__A, (__v32hf)(__m512h)_mm512_setzero_ph(), (__mmask32)__U);
 }
 
-static __inline__ __m256i __DEFAULT_FN_ATTRS512
-_mm512_cvtph_bf8(__m512h __A) {
+static __inline__ __m256i __DEFAULT_FN_ATTRS512 _mm512_cvtph_bf8(__m512h __A) {
   return (__m256i)__builtin_ia32_vcvtph2bf8_512_mask(
   (__v32hf)__A, (__v32qi)(__m256i)_mm256_undefined_si256(), (__mmask32)

[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-20 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-x86

Author: Mikołaj Piróg (mikolaj-pirog)


Changes

Intel spec for avx10.2 (https://cdrdv2.intel.com/v1/dl/getContent/828965) has 
been updated. This PR changes relevant names from the "SATURATING CONVERT 
INSTRUCTIONS" chapter .

---

Patch is 552.72 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/123656.diff


20 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsX86.td (+24-24) 
- (modified) clang/lib/Headers/avx10_2_512convertintrin.h (+48-48) 
- (modified) clang/lib/Headers/avx10_2convertintrin.h (+96-96) 
- (modified) clang/test/CodeGen/X86/avx10_2_512convert-builtins.c (+24-24) 
- (modified) clang/test/CodeGen/X86/avx10_2convert-builtins.c (+48-48) 
- (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+24-24) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+12-12) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.h (+12-12) 
- (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+21-21) 
- (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+12-12) 
- (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+49-49) 
- (modified) llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll (+136-136) 
- (modified) llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll (+272-272) 
- (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt (+416-416) 
- (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-32-att.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-32-intel.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-64-att.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-64-intel.s (+416-416) 
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+144-144) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsX86.td 
b/clang/include/clang/Basic/BuiltinsX86.td
index 18fc10eb85c027..001fc44890dd5c 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -5191,51 +5191,51 @@ let Features = "avx10.2-512", Attributes = [NoThrow, 
RequiredVectorWidth<512>] i
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
+  def vcvt2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
+  def vcvt2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, 
_Float16>, _Vector<16, _Float16>)">;
+  def vcvt2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, 
_Float16>, _Vector<32, _Float16>)">;
+  def vcvt2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
+  def vcvt2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
+  def vcvt2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2hf8s_128 : X86Builti

[clang] [llvm] [AVX10.2] Update convert chapter intrinsic and mnemonics names (PR #123656)

2025-01-20 Thread via cfe-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang

Author: Mikołaj Piróg (mikolaj-pirog)


Changes

Intel spec for avx10.2 (https://cdrdv2.intel.com/v1/dl/getContent/828965) has 
been updated. This PR changes relevant names from the "SATURATING CONVERT 
INSTRUCTIONS" chapter .

---

Patch is 552.72 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/123656.diff


20 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsX86.td (+24-24) 
- (modified) clang/lib/Headers/avx10_2_512convertintrin.h (+48-48) 
- (modified) clang/lib/Headers/avx10_2convertintrin.h (+96-96) 
- (modified) clang/test/CodeGen/X86/avx10_2_512convert-builtins.c (+24-24) 
- (modified) clang/test/CodeGen/X86/avx10_2convert-builtins.c (+48-48) 
- (modified) llvm/include/llvm/IR/IntrinsicsX86.td (+24-24) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+12-12) 
- (modified) llvm/lib/Target/X86/X86ISelLowering.h (+12-12) 
- (modified) llvm/lib/Target/X86/X86InstrAVX10.td (+21-21) 
- (modified) llvm/lib/Target/X86/X86InstrFragmentsSIMD.td (+12-12) 
- (modified) llvm/lib/Target/X86/X86IntrinsicsInfo.h (+49-49) 
- (modified) llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll (+136-136) 
- (modified) llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll (+272-272) 
- (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-32.txt (+416-416) 
- (modified) llvm/test/MC/Disassembler/X86/avx10.2convert-64.txt (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-32-att.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-32-intel.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-64-att.s (+416-416) 
- (modified) llvm/test/MC/X86/avx10.2convert-64-intel.s (+416-416) 
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+144-144) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsX86.td 
b/clang/include/clang/Basic/BuiltinsX86.td
index 18fc10eb85c027..001fc44890dd5c 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -5191,51 +5191,51 @@ let Features = "avx10.2-512", Attributes = [NoThrow, 
RequiredVectorWidth<512>] i
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
+  def vcvt2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
+  def vcvt2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, 
_Float16>, _Vector<16, _Float16>)">;
+  def vcvt2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, 
_Float16>, _Vector<32, _Float16>)">;
+  def vcvt2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
+  def vcvt2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, 
_Vector<8, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] 
in {
-  def vcvtne2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
+  def vcvt2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, 
_Vector<16, _Float16>)">;
 }
 
 let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] 
in {
-  def vcvtne2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
+  def vcvt2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, 
_Vector<32, _Float16>)">;
 }
 
 let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] 
in {
-  def vcvtne2ph2hf8s_128 : X86Builtin<"_Ve