[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

2025-07-06 Thread Jim Lin via cfe-commits 

https://github.com/tclin914 closed 
https://github.com/llvm/llvm-project/pull/147005
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[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

2025-07-04 Thread Pengcheng Wang via cfe-commits 

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/147005
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[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

2025-07-04 Thread Jim Lin via cfe-commits 

https://github.com/tclin914 updated 
https://github.com/llvm/llvm-project/pull/147005

>From a8b04339f8056e868fe2347d3af421f48c2d8308 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Thu, 3 Jul 2025 09:22:48 +0800
Subject: [PATCH 1/2] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4
 Load) extension

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

Co-authored-by: Lino Hsing-Yu Peng 
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 .../riscv-target-features-andes.c |  9 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  1 +
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  3 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 32 +++
 llvm/test/CodeGen/RISCV/attributes.ll |  4 ++
 llvm/test/CodeGen/RISCV/features-info.ll  |  1 +
 llvm/test/MC/RISCV/xandesvsintload-valid.s| 39 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  1 +
 11 files changed, 101 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/xandesvsintload-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 2a9d4f3f9d1ba..b87f0cb568e00 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -162,6 +162,7 @@
 // CHECK-NEXT: xandesvbfhcvt5.0   'XAndesVBFHCvt' (Andes 
Vector BFLOAT16 Conversion Extension)
 // CHECK-NEXT: xandesvdot   5.0   'XAndesVDot' (Andes Vector 
Dot Product Extension)
 // CHECK-NEXT: xandesvpackfph   5.0   'XAndesVPackFPH' (Andes 
Vector Packed FP16 Extension)
+// CHECK-NEXT: xandesvsintload  5.0   'XAndesVSIntLoad' (Andes 
Vector INT4 Load Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c 
b/clang/test/Preprocessor/riscv-target-features-andes.c
index e2b783f200766..083deb02a2679 100644
--- a/clang/test/Preprocessor/riscv-target-features-andes.c
+++ b/clang/test/Preprocessor/riscv-target-features-andes.c
@@ -5,6 +5,7 @@
 
 // CHECK-NOT: __riscv_xandesperf {{.*$}}
 // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
+// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
 // CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
 // CHECK-NOT: __riscv_xandesvdot {{.*$}}
 
@@ -24,6 +25,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
 // CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt  500{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// CHECK-XANDESVSINTLOAD: __riscv_xandesvsintload  500{{$}}
+
 // RUN: %clang --target=riscv32 \
 // RUN:   -march=rv32i_xandesvpackfph -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 82114791b3c0c..158a20cce7f85 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -519,6 +519,9 @@ The current vendor extensions supported are:
 ``XAndesVBFHCvt``
   LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion 
Extension specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
+``XAndesVSINTLoad``
+  LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 ``XAndesVPackFPH``
   LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 26384d94d04fc..daf822388a2ff 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -213,6 +213,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

2025-07-04 Thread via cfe-commits 

llvmbot wrote:



@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang-driver

Author: Jim Lin (tclin914)


Changes

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

---
Full diff: https://github.com/llvm/llvm-project/pull/147005.diff


11 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) clang/test/Preprocessor/riscv-target-features-andes.c (+9) 
- (modified) llvm/docs/RISCVUsage.rst (+3) 
- (modified) llvm/docs/ReleaseNotes.md (+1) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2-1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td (+32) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4) 
- (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1) 
- (added) llvm/test/MC/RISCV/xandesvsintload-valid.s (+39) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 2a9d4f3f9d1ba..b87f0cb568e00 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -162,6 +162,7 @@
 // CHECK-NEXT: xandesvbfhcvt5.0   'XAndesVBFHCvt' (Andes 
Vector BFLOAT16 Conversion Extension)
 // CHECK-NEXT: xandesvdot   5.0   'XAndesVDot' (Andes Vector 
Dot Product Extension)
 // CHECK-NEXT: xandesvpackfph   5.0   'XAndesVPackFPH' (Andes 
Vector Packed FP16 Extension)
+// CHECK-NEXT: xandesvsintload  5.0   'XAndesVSIntLoad' (Andes 
Vector INT4 Load Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c 
b/clang/test/Preprocessor/riscv-target-features-andes.c
index e2b783f200766..083deb02a2679 100644
--- a/clang/test/Preprocessor/riscv-target-features-andes.c
+++ b/clang/test/Preprocessor/riscv-target-features-andes.c
@@ -5,6 +5,7 @@
 
 // CHECK-NOT: __riscv_xandesperf {{.*$}}
 // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
+// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
 // CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
 // CHECK-NOT: __riscv_xandesvdot {{.*$}}
 
@@ -24,6 +25,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
 // CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt  500{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// CHECK-XANDESVSINTLOAD: __riscv_xandesvsintload  500{{$}}
+
 // RUN: %clang --target=riscv32 \
 // RUN:   -march=rv32i_xandesvpackfph -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 82114791b3c0c..158a20cce7f85 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -519,6 +519,9 @@ The current vendor extensions supported are:
 ``XAndesVBFHCvt``
   LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion 
Extension specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
+``XAndesVSINTLoad``
+  LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 ``XAndesVPackFPH``
   LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 26384d94d04fc..daf822388a2ff 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -213,6 +213,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes `XAndesvbfhcvt` (Andes Vector BFLOAT16 
Conversion extension).
 * `-mcpu=andes-ax45mpv` was added.
 * Removed -mattr=+no-rvc-hints that could be used to disable parsing and 
gene

[clang] [llvm] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (PR #147005)

2025-07-04 Thread Jim Lin via cfe-commits 

https://github.com/tclin914 created 
https://github.com/llvm/llvm-project/pull/147005

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

>From a8b04339f8056e868fe2347d3af421f48c2d8308 Mon Sep 17 00:00:00 2001
From: Jim Lin 
Date: Thu, 3 Jul 2025 09:22:48 +0800
Subject: [PATCH] [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load)
 extension

The spec can be found at:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

This patch only implements MC support for XAndesVSIntLoad.

Co-authored-by: Lino Hsing-Yu Peng 
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 .../riscv-target-features-andes.c |  9 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  1 +
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  3 +-
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 32 +++
 llvm/test/CodeGen/RISCV/attributes.ll |  4 ++
 llvm/test/CodeGen/RISCV/features-info.ll  |  1 +
 llvm/test/MC/RISCV/xandesvsintload-valid.s| 39 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  1 +
 11 files changed, 101 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/xandesvsintload-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 2a9d4f3f9d1ba..b87f0cb568e00 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -162,6 +162,7 @@
 // CHECK-NEXT: xandesvbfhcvt5.0   'XAndesVBFHCvt' (Andes 
Vector BFLOAT16 Conversion Extension)
 // CHECK-NEXT: xandesvdot   5.0   'XAndesVDot' (Andes Vector 
Dot Product Extension)
 // CHECK-NEXT: xandesvpackfph   5.0   'XAndesVPackFPH' (Andes 
Vector Packed FP16 Extension)
+// CHECK-NEXT: xandesvsintload  5.0   'XAndesVSIntLoad' (Andes 
Vector INT4 Load Extension)
 // CHECK-NEXT: xcvalu   1.0   'XCValu' (CORE-V ALU 
Operations)
 // CHECK-NEXT: xcvbi1.0   'XCVbi' (CORE-V Immediate 
Branching)
 // CHECK-NEXT: xcvbitmanip  1.0   'XCVbitmanip' (CORE-V Bit 
Manipulation)
diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c 
b/clang/test/Preprocessor/riscv-target-features-andes.c
index e2b783f200766..083deb02a2679 100644
--- a/clang/test/Preprocessor/riscv-target-features-andes.c
+++ b/clang/test/Preprocessor/riscv-target-features-andes.c
@@ -5,6 +5,7 @@
 
 // CHECK-NOT: __riscv_xandesperf {{.*$}}
 // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}}
+// CHECK-NOT: __riscv_xandesvsintload {{.*$}}
 // CHECK-NOT: __riscv_xandesvpackfph {{.*$}}
 // CHECK-NOT: __riscv_xandesvdot {{.*$}}
 
@@ -24,6 +25,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s
 // CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt  500{{$}}
 
+// RUN: %clang --target=riscv32 \
+// RUN:   -march=rv32i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_xandesvsintload -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s
+// CHECK-XANDESVSINTLOAD: __riscv_xandesvsintload  500{{$}}
+
 // RUN: %clang --target=riscv32 \
 // RUN:   -march=rv32i_xandesvpackfph -E -dM %s \
 // RUN:   -o - | FileCheck --check-prefix=CHECK-XANDESVPACKFPH %s
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 82114791b3c0c..158a20cce7f85 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -519,6 +519,9 @@ The current vendor extensions supported are:
 ``XAndesVBFHCvt``
   LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion 
Extension specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
+``XAndesVSINTLoad``
+  LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
+
 ``XAndesVPackFPH``
   LLVM implements `version 5.0.0 of the Andes Vector Packed FP16 Extension 
specification 
`__
 by Andes Technology. All instructions are prefixed with `nds.` as described in 
the specification.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 26384d94d04fc..daf822388a2ff 100