[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/djtodoro closed https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
djtodoro wrote:
Aha ok. I understand.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
topperc wrote:
I think I meant to write `hasVendorXMIPSLSP()`. I think I didn't want it to be
`useLoadStorePairs()`.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
djtodoro wrote:
https://github.com/llvm/llvm-project/pull/121394#discussion_r1918794675
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
djtodoro wrote:
IIUC, I think you proposed we use `hasVendorXMIPSCMove` for both.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1228,6 +1228,21 @@ def HasVendorXCVbi
: Predicate<"Subtarget->hasVendorXCVbi()">,
AssemblerPredicate<(all_of FeatureVendorXCVbi),
"'XCVbi' (CORE-V Immediate Branching)">;
+// MIPS Extensions
+
+def FeatureVendorXMIPSCMove
+: RISCVExtension<1, 0, "MIPS conditional move instruction(s) (ccmov)">;
+def HasVendorXMIPSCMove
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSCMove),
+ "'Xmipscmove' ('mips.ccmov' instruction)">;
+def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+def FeatureVendorXMIPSLSP
+: RISCVExtension<1, 0, "MIPS optimization for hardware load-store
bonding">;
+def HasVendorXMIPSLSP
+: Predicate<"Subtarget->hasVendorXMIPSCMove()">,
topperc wrote:
hasVendorXMIPSCMove -> hasVendorXMIPSLSP?
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
djtodoro wrote: @topperc Is it ok now? :) https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
djolertrk wrote: @topperc looks ok now? https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/djolertrk deleted https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,80 @@ class RVInstJhttps://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,95 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+// Operand definitions.
+//===--===//
+
+// A 7-bit unsigned immediate where the least significant three bits are zero.
+def uimm7_lsb000 : RISCVOp,
+ ImmLeaf(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<7, "Lsb000">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeUImmOperand<7>";
+ let OperandType = "OPERAND_UIMM7_LSB000";
+ let MCOperandPredicate = [{
+int64_t Imm;
+if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+return isShiftedUInt<4, 3>(Imm);
+ }];
+}
+
+//===--===//
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorXMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0,
+ DecoderNamespace = "Xmipscmove" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
topperc wrote:
need to indent 1 more space
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
djtodoro wrote: @lenary thanks! >You still have a whitespace change to this file? No, the whitespaces are there on `main` branch. I applied `clang-format` initially, and that is why it was included in one of my previous patches. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/lenary approved this pull request. Two tiny issues, but I think I'm happy for this to land. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
lenary wrote: You still have a whitespace change to this file? https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -238,3 +247,11 @@ void
RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
Policy.OnlyBottomUp = false;
}
}
+
+bool RISCVSubtarget::useLoadStorePairs() const {
+ return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
+}
lenary wrote:
Nit: I'm not sure this is used any more.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
djtodoro wrote:
Hmm, you are right. I will add `mips-` to remove confusion. Thanks @jrtc27!
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
djtodoro wrote:
thanks!
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Load word pair format.
+class LWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-22} = imm7{6-2};
+ let Inst{21-20} = 0b01;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Store double pair format.
+class SDPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-10} = imm7{4-3};
+ let Inst{9-0} = 0b001011;
+}
+
+// Store word pair format.
+class SWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-9} = imm7{4-2};
+ let Inst{8-0} = 0b010001011;
topperc wrote:
> @topperc you meant `let Inst{6-0} = OPC_CUSTOM_0.Value;` I think :)
That's what I meant. Thanks.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Load word pair format.
+class LWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-22} = imm7{6-2};
+ let Inst{21-20} = 0b01;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Store double pair format.
+class SDPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-10} = imm7{4-3};
+ let Inst{9-0} = 0b001011;
+}
+
+// Store word pair format.
+class SWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-9} = imm7{4-2};
+ let Inst{8-0} = 0b010001011;
djtodoro wrote:
@topperc you meant `let Inst{6-0} = OPC_CUSTOM_0.Value;` I think :)
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
djtodoro wrote:
I see, it makes sense! :D
Initially, I created it against an older LLVM, so I have missed this...Thanks!
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; + +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", + "true", "Using CCMov", + [Feature64Bit]>; djtodoro wrote: >It would be better if this and def FeatureVendorMIPSLoadStorePairs both used >RISCVExtension. I think this means some changes to the functions on >riscvsubtarget too, it should be clear to follow from the other vendor >extensions. This will also have a knock-on effect on some other tests, >especially relating to RISCVISAInfo (and also some in clang iirc), but this is >for the better - it means the compiler can show it supports your extensions 😄 Good point. Yes, I have added it, and resolved test failures (there is one unit test as well). Thanks :) >Please may you also put these definitions beside the other vendor extensions, >rather than at the end with these codegen options? The section starts >somewhere around line 1020, and you'll see each vendor's extensions are with >each other. Sure. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
topperc wrote:
I don't think setuge, setge, setle, setule will make it to isel so any patterns
that use them can't be tested.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@ +//===-- RISCVInstrInfoXMips.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file describes the vendor extensions defined by MIPS. +// +//===--===// + +//===--===// + topperc wrote: Extra blank line? https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
topperc wrote:
line exceeds 80 characters
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -109,6 +109,21 @@ def uimm7_lsb00 : RISCVOp, }]; } +// A 7-bit unsigned immediate where the least significant three bits are zero. topperc wrote: This should be defned in Mips specific file if that's the only place it is used. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
+def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
+let mayLoad = 1;
+let mayStore = 0;
+}
+def LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb000:$imm7),
+"mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
+let mayLoad = 1;
+let mayStore = 0;
+}
+def SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
+Sched<[WriteSTW, ReadStoreData, ReadStoreData,
ReadMemBase]> {
+let mayLoad = 0;
+let mayStore = 1;
+}
+def SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1,
uimm7_lsb000:$imm7),
+"mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
+Sched<[WriteSTD, ReadStoreData, ReadStoreData,
ReadMemBase]> {
+let mayLoad = 0;
topperc wrote:
Body should be indented 2 spaces
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; + +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", topperc wrote: FeatureVendorMIPSCMove -> FeatureVendorXMIPSCMove so it matches the name of the extension https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; + +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", + "true", "Using CCMov", + [Feature64Bit]>; +def HasVendorMIPSCMove topperc wrote: I think I would rather see this split into `HasVendorMIPSCMove` for assembler, and `UseCCMovInsn` for isel patterns. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
+def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
+let mayLoad = 1;
+let mayStore = 0;
+}
+def LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb000:$imm7),
+"mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
+let mayLoad = 1;
+let mayStore = 0;
+}
+def SWP : SWPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.swp", "$rs2, $rs3, ${imm7}(${rs1})">,
+Sched<[WriteSTW, ReadStoreData, ReadStoreData,
ReadMemBase]> {
+let mayLoad = 0;
topperc wrote:
Body should be indentede 2 spaces
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Load word pair format.
+class LWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-22} = imm7{6-2};
+ let Inst{21-20} = 0b01;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Store double pair format.
+class SDPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-10} = imm7{4-3};
+ let Inst{9-0} = 0b001011;
+}
+
+// Store word pair format.
+class SWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-9} = imm7{4-2};
+ let Inst{8-0} = 0b010001011;
topperc wrote:
```
let Inst{8-7} = 0b01;
let Inst{6-0} = 0b001011;
```
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
topperc wrote:
Xmipscomve -> Xmipscmove?
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
+def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
+let mayLoad = 1;
+let mayStore = 0;
+}
+def LDP : LDPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb000:$imm7),
+"mips.ldp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDD, WriteLDD, ReadMemBase]> {
+let mayLoad = 1;
topperc wrote:
Body should be indented 2 spaces
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
+def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
topperc wrote:
`Sched` should be aligned to the same column as `LWPFormat`
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
+def LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1,
uimm7_lsb00:$imm7),
+"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
+Sched<[WriteLDW, WriteLDW, ReadMemBase]> {
+let mayLoad = 1;
topperc wrote:
Body should be indented 2 spaces
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Load word pair format.
+class LWPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-22} = imm7{6-2};
+ let Inst{21-20} = 0b01;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = OPC_CUSTOM_0.Value;
+}
+
+// Store double pair format.
+class SDPFormat
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs3;
+ bits<5> rs2;
+ bits<5> rs1;
+
+ let Inst{31-27} = rs3;
+ let Inst{26-25} = imm7{6-5};
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b101;
+ let Inst{11-10} = imm7{4-3};
+ let Inst{9-0} = 0b001011;
topperc wrote:
```
let Inst{9-7} = 0b000;
let Inst{6-0} = OPC_CUSTOM_0.Value;
```
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
+ Sched<[]>;
+}
+
+let Predicates = [HasVendorMIPSCMove] in {
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setne (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$rs2), (XLenVT 0))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT simm12_plus1:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
+def : Pat<(select (XLenVT (seteq (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setuge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setge (XLenVT GPR:$x), (XLenVT GPR:$y))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT (setle (XLenVT GPR:$y), (XLenVT GPR:$x))),
+ (XLenVT GPR:$rs3), (XLenVT GPR:$rs1)),
+ (CCMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
+ (CCMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
+}
+
+let Predicates = [HasVendorMIPSLoadStorePairs], hasSideEffects = 0,
DecoderNamespace = "Xmipslsp" in {
topperc wrote:
line exceeds 80 characters
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
jrtc27 wrote:
I worry that this name is going to get confused with Zilsd
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
lenary wrote: Please can you undo these whitespace changes, given you're not really making changes to this file https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1448,3 +1448,18 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", "AllowTaggedGlobals", "true", "Use an instruction sequence for taking the address of a global " "that allows a memory tag in the upper address bits">; + +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", + "true", "Using CCMov", + [Feature64Bit]>; lenary wrote: It would be better if this and `def FeatureVendorMIPSLoadStorePairs` both used `RISCVExtension`. I think this means some changes to the functions on riscvsubtarget too, it should be clear to follow from the other vendor extensions. This will also have a knock-on effect on some other tests, especially relating to RISCVISAInfo (and also some in clang iirc), but this is for the better - it means the compiler can show it supports your extensions 😄 Please may you also put these definitions beside the other vendor extensions, rather than at the end with these codegen options? The section starts somewhere around line 1020, and you'll see each vendor's extensions are with each other. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/lenary commented: Some small notes, the one about using RISCVExtension will probably have the most knock-on work (run both the llvm and the clang test suites after that change, to see where that info gets to) https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/lenary edited https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
djtodoro wrote:
Well, we have not seen benefits on some important applications/benchmarks for
us when using this extension with `p8700` CPU, so that is why we keep it `OFF`
by default for now.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
djtodoro wrote: @topperc Thanks for the comments! > This still isn't broken down enough. We usually like to see assembler support > in separate patches from code generation. I have removed `RISCVLoadStoreOptimizer` Pass, and will add it in a separate PR/commit. > Missing tests in test/MC/RISCV for the assembler and disassembler Added. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"ccmov", "$rd, $rs2, $rs1, $rs3">,
djtodoro wrote:
Yep, I have added it. The PR for `mips.` prefix is here
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/69.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,370 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+ // Find and pair load/store instructions.
+ bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+ // Convert load/store pairs to single instructions.
+ bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+ // Scan the instructions looking for a load/store that can be combined
+ // with the current instruction into a load/store pair.
+ // Return the matching instruction if one is found, else MBB->end().
+ MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+ bool &MergeForward);
+
+ MachineBasicBlock::iterator
+ mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+ AliasAnalysis *AA;
+ MachineRegisterInfo *MRI;
+ const RISCVInstrInfo *TII;
+ const RISCVRegisterInfo *TRI;
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+ bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME,
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(Fn.getFunction()))
+return false;
+ const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+ if (!Subtarget.useLoadStorePairs())
+return false;
+
+ bool MadeChange = false;
+ TII = Subtarget.getInstrInfo();
+ TRI = Subtarget.getRegisterInfo();
+ MRI = &Fn.getRegInfo();
+ AA = &getAnalysis().getAAResults();
+ ModifiedRegUnits.init(*TRI);
+ UsedRegUnits.init(*TRI);
+ UseLoadStorePair = Subtarget.useLoadStorePairs();
djtodoro wrote:
No need any more, thanks
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusions().empty() && ST.useLoadStorePairs()) {
djtodoro wrote:
Hm, I agree
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
}];
}
+// A 7-bit unsigned immediate where the least significant two bits are zero.
djtodoro wrote:
No need any more, thanks
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, Group, def mno_save_restore : Flag<["-"], "mno-save-restore">, Group, HelpText<"Disable using library calls for save and restore">; } // let Flags = [TargetSpecific] +def mload_store_pairs : Flag<["-"], "mload-store-pairs">, Group; +def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, Group; +def mccmov : Flag<["-"], "mccmov">, Group; +def mno_ccmov : Flag<["-"], "mno-ccmov">, Group; djtodoro wrote: Well, you are right. We have used those for testing purposes, and I will remove it. Thank you for the point. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, Group, def mno_save_restore : Flag<["-"], "mno-save-restore">, Group, HelpText<"Disable using library calls for save and restore">; } // let Flags = [TargetSpecific] +def mload_store_pairs : Flag<["-"], "mload-store-pairs">, Group; +def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, Group; +def mccmov : Flag<["-"], "mccmov">, Group; +def mno_ccmov : Flag<["-"], "mno-ccmov">, Group; lenary wrote: The RISC-V backend has not added additional options (i.e. those not in the list `-march=`/`-mcpu=`/`-mabi=`) that change the target architecture extensions, and my understanding is this is on purpose (unlike in other targets). I think these would need more discussion before they are added. I could understand gating optimisations to introduce these instructions behind additional arguments, but these seem to control whether specific instructions are or are not legal. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"ccmov", "$rd, $rs2, $rs1, $rs3">,
jrtc27 wrote:
For upstreaming such a prefix must be registered:
https://github.com/riscv-non-isa/riscv-toolchain-conventions/blob/08ae8fe66141c12ba436678c60a05da9ac08c4e6/src/toolchain-conventions.adoc#assembly-mnemonic
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
topperc wrote: Missing tests in test/MC/RISCV for the assembler and disassembler https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -1395,6 +1395,19 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion() def TuneMIPSP8700 : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", "MIPS p8700 processor">; +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", topperc wrote: FeatureVendor* should be in the vendor extension section of this file not the tuning section. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,370 @@
+//===- RISCVLoadStoreOptimizer.cpp
===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Bundle loads and stores that operate on consecutive memory locations to take
+// the advantage of hardware load/store bonding.
+//
+//===--===//
+
+#include "RISCV.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Target/TargetOptions.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-load-store-opt"
+#define RISCV_LOAD_STORE_OPT_NAME "RISCV Load / Store Optimizer"
+namespace {
+
+struct RISCVLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ RISCVLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ MachineFunctionProperties getRequiredProperties() const override {
+return MachineFunctionProperties().set(
+MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+AU.addRequired();
+MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_LOAD_STORE_OPT_NAME; }
+
+ // Find and pair load/store instructions.
+ bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
+
+ // Convert load/store pairs to single instructions.
+ bool tryConvertToLdStPair(MachineBasicBlock::iterator First,
+MachineBasicBlock::iterator Second);
+
+ // Scan the instructions looking for a load/store that can be combined
+ // with the current instruction into a load/store pair.
+ // Return the matching instruction if one is found, else MBB->end().
+ MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
+ bool &MergeForward);
+
+ MachineBasicBlock::iterator
+ mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired, bool MergeForward);
+
+private:
+ AliasAnalysis *AA;
+ MachineRegisterInfo *MRI;
+ const RISCVInstrInfo *TII;
+ const RISCVRegisterInfo *TRI;
+ LiveRegUnits ModifiedRegUnits, UsedRegUnits;
+ bool UseLoadStorePair = false;
+};
+} // end anonymous namespace
+
+char RISCVLoadStoreOpt::ID = 0;
+INITIALIZE_PASS(RISCVLoadStoreOpt, DEBUG_TYPE, RISCV_LOAD_STORE_OPT_NAME,
false,
+false)
+
+bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
+ if (skipFunction(Fn.getFunction()))
+return false;
+ const RISCVSubtarget &Subtarget = Fn.getSubtarget();
+
+ if (!Subtarget.useLoadStorePairs())
+return false;
+
+ bool MadeChange = false;
+ TII = Subtarget.getInstrInfo();
+ TRI = Subtarget.getRegisterInfo();
+ MRI = &Fn.getRegInfo();
+ AA = &getAnalysis().getAAResults();
+ ModifiedRegUnits.init(*TRI);
+ UsedRegUnits.init(*TRI);
+ UseLoadStorePair = Subtarget.useLoadStorePairs();
topperc wrote:
This is already checked to be true on line 82. Why do we need a member variable
for it?
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -389,6 +390,13 @@ class RISCVPassConfig : public TargetPassConfig {
DAG->addMutation(createStoreClusterDAGMutation(
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
}
+
+const RISCVSubtarget &ST = C->MF->getSubtarget();
+if (!ST.getMacroFusions().empty() && ST.useLoadStorePairs()) {
topperc wrote:
This needs to be integrated with the `EnablePostMISchedLoadStoreClustering` on
line 386. Otherwise we will have multiple load/store cluster mutations.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -62,6 +62,15 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
topperc wrote:
Why is this off by default?
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
}];
}
+// A 7-bit unsigned immediate where the least significant two bits are zero.
topperc wrote:
Why do these need to move? RISCVInstrInfoXMips.td is included after
RISCVInstrInfoC.td
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -514,6 +514,78 @@ class RVInstJ
+: RVInst {
+ bits<7> imm7;
+ bits<5> rs1;
+ bits<5> rd1;
+ bits<5> rd2;
+
+ let Inst{31-27} = rd2;
+ let Inst{26-23} = imm7{6-3};
+ let Inst{22-20} = 0b000;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd1;
+ let Inst{6-0} = 0b0001011;
topperc wrote:
This use the `OPC_CUSTOM_0.Value` for readability
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
@@ -0,0 +1,82 @@
+//===-- RISCVInstrInfoXMips.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the vendor extensions defined by MIPS.
+//
+//===--===//
+
+//===--===//
+
+// MIPS extensions
+//===--===//
+
+let Predicates = [HasVendorMIPSCMove], hasSideEffects = 0, mayLoad = 0,
mayStore = 0, DecoderNamespace = "Xmipscomve" in {
+def CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
+(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
+"ccmov", "$rd, $rs2, $rs1, $rs3">,
topperc wrote:
Vendor instructions should have a prefix like `mips.` to avoid collisions with
other vendors or future standard instruction names.
https://github.com/llvm/llvm-project/pull/121394
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
topperc wrote: This still isn't broken down enough. We usually like to see assembler support in separate patches from code generation. https://github.com/llvm/llvm-project/pull/121394 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/121394
>From 29d22560f2987e81ea66e4c7dea42f594bda709f Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
clang/include/clang/Driver/Options.td | 4 +
clang/lib/Driver/ToolChains/Clang.cpp | 15 +
llvm/docs/RISCVUsage.rst | 6 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 +
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCV.h | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 13 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVInstrFormats.td| 72 +++
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 43 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.h| 6 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 145 +
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 125 -
llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td | 82 +++
.../Target/RISCV/RISCVLoadStoreOptimizer.cpp | 370 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +-
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 17 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 2 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 15 +
llvm/test/CodeGen/RISCV/O0-pipeline.ll| 1 +
llvm/test/CodeGen/RISCV/O3-pipeline.ll| 2 +
llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
llvm/test/CodeGen/RISCV/select-and.ll | 25 +
llvm/test/CodeGen/RISCV/select-bare.ll| 14 +
llvm/test/CodeGen/RISCV/select-cc.ll | 86 +++
llvm/test/CodeGen/RISCV/select-or.ll | 25 +
27 files changed, 1472 insertions(+), 127 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..ef708c85718e4b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
+
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/djtodoro updated
https://github.com/llvm/llvm-project/pull/121394
>From f833498eb48595cc6b2bd5dd0c1b05d941313877 Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
clang/include/clang/Driver/Options.td | 4 +
clang/lib/Driver/ToolChains/Clang.cpp | 15 +
llvm/docs/RISCVUsage.rst | 6 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 +
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCV.h | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 13 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVInstrFormats.td| 72 +++
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 43 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.h| 6 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 145 +
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 125 -
llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td | 82 +++
.../Target/RISCV/RISCVLoadStoreOptimizer.cpp | 370 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +-
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 17 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 2 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 15 +
llvm/test/CodeGen/RISCV/O0-pipeline.ll| 1 +
llvm/test/CodeGen/RISCV/O3-pipeline.ll| 2 +
llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
llvm/test/CodeGen/RISCV/select-and.ll | 25 +
llvm/test/CodeGen/RISCV/select-bare.ll| 14 +
llvm/test/CodeGen/RISCV/select-cc.ll | 86 +++
llvm/test/CodeGen/RISCV/select-or.ll | 25 +
27 files changed, 1472 insertions(+), 127 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..ef708c85718e4b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
+
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 1d5154663509b6200038a2f0b0ac958ea556fa9e
a2e1fd5ffab4fe64a160571a9dffaacc3f22c32d --extensions cpp,h --
llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
clang/lib/Driver/ToolChains/Clang.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCV.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVSubtarget.cpp llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
``
View the diff from clang-format here.
``diff
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index e91df88380..3b97378f8b 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2175,8 +2175,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
}
}
- if (Arg *A = Args.getLastArg(options::OPT_mccmov,
- options::OPT_mno_ccmov)) {
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov, options::OPT_mno_ccmov)) {
if (A->getOption().matches(options::OPT_mno_ccmov)) {
CmdArgs.push_back("-mllvm");
CmdArgs.push_back("-riscv-ccmov=0");
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index e6307086d9..fca7584e46 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -62,15 +62,14 @@ static cl::opt RISCVMinimumJumpTableEntries(
"riscv-min-jump-table-entries", cl::Hidden,
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
-static cl::opt UseLoadStorePairsOpt(
-"riscv-load-store-pairs",
-cl::desc("RISCV: Optimize for load-store bonding"),
-cl::init(false), cl::Hidden);
-
-static cl::opt UseCCMovInsn(
-"riscv-ccmov",
-cl::desc("RISCV: Use 'ccmov' instruction"),
-cl::init(true), cl::Hidden);
+static cl::opt
+UseLoadStorePairsOpt("riscv-load-store-pairs",
+ cl::desc("RISCV: Optimize for load-store bonding"),
+ cl::init(false), cl::Hidden);
+
+static cl::opt UseCCMovInsn("riscv-ccmov",
+ cl::desc("RISCV: Use 'ccmov' instruction"),
+ cl::init(true), cl::Hidden);
void RISCVSubtarget::anchor() {}
``
https://github.com/llvm/llvm-project/pull/121394
___
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cfe-commits@lists.llvm.org
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[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
llvmbot wrote:
@llvm/pr-subscribers-clang-driver
Author: Djordje Todorovic (djtodoro)
Changes
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
Patch is 75.96 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/121394.diff
27 Files Affected:
- (modified) clang/include/clang/Driver/Options.td (+4)
- (modified) clang/lib/Driver/ToolChains/Clang.cpp (+15)
- (modified) llvm/docs/RISCVUsage.rst (+6)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+10)
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1)
- (modified) llvm/lib/Target/RISCV/RISCV.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+13)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+72)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+43)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+6)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+145)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (-125)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+82)
- (added) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+370)
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+18)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+15)
- (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+1)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+2)
- (added) llvm/test/CodeGen/RISCV/load-store-pair.ll (+509)
- (modified) llvm/test/CodeGen/RISCV/select-and.ll (+25)
- (modified) llvm/test/CodeGen/RISCV/select-bare.ll (+14)
- (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+86)
- (modified) llvm/test/CodeGen/RISCV/select-or.ll (+25)
``diff
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..e91df8838032cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov,
+ options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Djordje Todorovic (djtodoro)
Changes
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
Patch is 75.96 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/121394.diff
27 Files Affected:
- (modified) clang/include/clang/Driver/Options.td (+4)
- (modified) clang/lib/Driver/ToolChains/Clang.cpp (+15)
- (modified) llvm/docs/RISCVUsage.rst (+6)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+10)
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1)
- (modified) llvm/lib/Target/RISCV/RISCV.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+13)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+72)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+43)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+6)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+145)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (-125)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+82)
- (added) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+370)
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+18)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+15)
- (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+1)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+2)
- (added) llvm/test/CodeGen/RISCV/load-store-pair.ll (+509)
- (modified) llvm/test/CodeGen/RISCV/select-and.ll (+25)
- (modified) llvm/test/CodeGen/RISCV/select-bare.ll (+14)
- (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+86)
- (modified) llvm/test/CodeGen/RISCV/select-or.ll (+25)
``diff
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..e91df8838032cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov,
+ options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Djordje Todorovic (djtodoro)
Changes
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
Patch is 75.96 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/121394.diff
27 Files Affected:
- (modified) clang/include/clang/Driver/Options.td (+4)
- (modified) clang/lib/Driver/ToolChains/Clang.cpp (+15)
- (modified) llvm/docs/RISCVUsage.rst (+6)
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+10)
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+1)
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1)
- (modified) llvm/lib/Target/RISCV/RISCV.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+13)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+72)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+43)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+6)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+145)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (-125)
- (added) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+82)
- (added) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+370)
- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+3-1)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+18)
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+15)
- (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+1)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+2)
- (added) llvm/test/CodeGen/RISCV/load-store-pair.ll (+509)
- (modified) llvm/test/CodeGen/RISCV/select-and.ll (+25)
- (modified) llvm/test/CodeGen/RISCV/select-bare.ll (+14)
- (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+86)
- (modified) llvm/test/CodeGen/RISCV/select-or.ll (+25)
``diff
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..e91df8838032cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov,
+ options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
[clang] [llvm] [RISCV] Add MIPS extensions (PR #121394)
https://github.com/djtodoro created
https://github.com/llvm/llvm-project/pull/121394
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
>From a2e1fd5ffab4fe64a160571a9dffaacc3f22c32d Mon Sep 17 00:00:00 2001
From: Djordje Todorovic
Date: Thu, 26 Dec 2024 09:09:24 +0100
Subject: [PATCH] [RISCV] Add MIPS extensions
Adding two extensions for MIPS p8700 CPU:
1. cmove (conditional move)
2. lsp (load/store pair)
The official product page here:
https://mips.com/products/hardware/p8700
---
clang/include/clang/Driver/Options.td | 4 +
clang/lib/Driver/ToolChains/Clang.cpp | 15 +
llvm/docs/RISCVUsage.rst | 6 +
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 10 +
llvm/lib/Target/RISCV/CMakeLists.txt | 1 +
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCV.h | 2 +
llvm/lib/Target/RISCV/RISCVFeatures.td| 13 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVInstrFormats.td| 72 +++
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 43 ++
llvm/lib/Target/RISCV/RISCVInstrInfo.h| 6 +
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 145 +
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 125 -
llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td | 82 +++
.../Target/RISCV/RISCVLoadStoreOptimizer.cpp | 370 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 4 +-
llvm/lib/Target/RISCV/RISCVSubtarget.cpp | 18 +
llvm/lib/Target/RISCV/RISCVSubtarget.h| 2 +
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 15 +
llvm/test/CodeGen/RISCV/O0-pipeline.ll| 1 +
llvm/test/CodeGen/RISCV/O3-pipeline.ll| 2 +
llvm/test/CodeGen/RISCV/load-store-pair.ll| 509 ++
llvm/test/CodeGen/RISCV/select-and.ll | 25 +
llvm/test/CodeGen/RISCV/select-bare.ll| 14 +
llvm/test/CodeGen/RISCV/select-cc.ll | 86 +++
llvm/test/CodeGen/RISCV/select-or.ll | 25 +
27 files changed, 1473 insertions(+), 127 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
create mode 100644 llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
create mode 100644 llvm/test/CodeGen/RISCV/load-store-pair.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index d922709db17786..28b7d70f77d4a2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">,
Group,
def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
HelpText<"Disable using library calls for save and restore">;
} // let Flags = [TargetSpecific]
+def mload_store_pairs : Flag<["-"], "mload-store-pairs">,
Group;
+def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">,
Group;
+def mccmov : Flag<["-"], "mccmov">, Group;
+def mno_ccmov : Flag<["-"], "mno-ccmov">, Group;
let Flags = [TargetSpecific] in {
def menable_experimental_extensions : Flag<["-"],
"menable-experimental-extensions">, Group,
HelpText<"Enable use of experimental RISC-V extensions.">;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a020e00cd17392..e91df8838032cd 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
CmdArgs.push_back(A->getValue());
}
+ if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs,
+ options::OPT_mno_load_store_pairs)) {
+if (A->getOption().matches(options::OPT_mload_store_pairs)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-load-store-pairs=1");
+}
+ }
+
+ if (Arg *A = Args.getLastArg(options::OPT_mccmov,
+ options::OPT_mno_ccmov)) {
+if (A->getOption().matches(options::OPT_mno_ccmov)) {
+ CmdArgs.push_back("-mllvm");
+ CmdArgs.push_back("-riscv-ccmov=0");
+}
+ }
// Handle -mrvv-vector-bits=
if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) {
StringRef Val = A->getValue();
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 22600f5720553e..06b32a69cef9ea 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -444,6 +444,12 @@ The current vendor extensions supported are:
``experimental-Xqcisls``
LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension
specification `__ by
Qualcomm. All instructions are prefixed with `qc.` as described in the
specification. These instructions are only available for riscv32.
+``Xmipscmove``
+ LLVM implements conditional move for the `p8700 processor
<
