subject:"\[clang\] \[llvm\] \[RISCV\] Add Qualcomm uC Xqcia \(Arithmetic\) extension \(PR #118076\)"

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread Sudharsan Veeravalli via cfe-commits


svs-quic wrote:

Don't think force push was the right thing to do here. I'll put up another PR. 
Closing this.

https://github.com/llvm/llvm-project/pull/118076
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread Sudharsan Veeravalli via cfe-commits


https://github.com/svs-quic closed 
https://github.com/llvm/llvm-project/pull/118076
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread Sudharsan Veeravalli via cfe-commits


https://github.com/svs-quic updated 
https://github.com/llvm/llvm-project/pull/118076

>From f1031947890501ba543ee9c937110f75379f2069 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli 
Date: Fri, 29 Nov 2024 14:25:31 +0530
Subject: [PATCH] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension

This extension adds 11 instructions that perform integer
arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/ReleaseNotes.md |   2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |   3 +
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   2 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   8 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 184 +---
 llvm/lib/TargetParser/RISCVISAInfo.cpp|   3 +-
 llvm/test/CodeGen/RISCV/attributes.ll |   2 +
 llvm/test/MC/RISCV/xqcia-invalid.s| 201 ++
 llvm/test/MC/RISCV/xqcia-valid.s  |  55 +
 .../TargetParser/RISCVISAInfoTest.cpp |   6 +
 12 files changed, 393 insertions(+), 75 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcia-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcia-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 70b7a96daf1daf..9df903115b57c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -188,6 +188,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6d50839d68953e..dc3f3aeb735f87 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled 
Load Store)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b843bb5ae43100..7c91dc07bbd3e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm11() const { return IsUImm<11>(); }
   bool isUImm16() const { return IsUImm<16>(); }
   bool isUImm20() const { return IsUImm<20>(); }
   bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
 "immediate must be a multiple of 16 bytes and non-zero in the range");
+  case Match_InvalidUImm11:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
   case Match_InvalidSImm12:
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 95658f24f79e1c..4d563046923a58 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst 
&MI, uint64_t &Size,
 "Qualcomm uC CSR custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
 "Qualcomm uC Scaled Load Store custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
+"Qualcomm uC Arithmetic custom opcode table");
   TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
   return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-mc

Author: Sudharsan Veeravalli (svs-quic)


Changes

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---
Full diff: https://github.com/llvm/llvm-project/pull/118076.diff


12 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) llvm/docs/ReleaseNotes.md (+2) 
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+3) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+36) 
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) 
- (added) llvm/test/MC/RISCV/xqcia-invalid.s (+201) 
- (added) llvm/test/MC/RISCV/xqcia-valid.s (+55) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+6) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 70b7a96daf1daf..9df903115b57c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -188,6 +188,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6d50839d68953e..dc3f3aeb735f87 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled 
Load Store)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b843bb5ae43100..7c91dc07bbd3e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm11() const { return IsUImm<11>(); }
   bool isUImm16() const { return IsUImm<16>(); }
   bool isUImm20() const { return IsUImm<20>(); }
   bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
 "immediate must be a multiple of 16 bytes and non-zero in the range");
+  case Match_InvalidUImm11:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
   case Match_InvalidSImm12:
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 95658f24f79e1c..4d563046923a58 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst 
&MI, uint64_t &Size,
 "Qualcomm uC CSR custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
 "Qualcomm uC Scaled Load Store custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
+"Qualcomm uC Arithmetic custom opcode table");
   TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
   return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index ca2f868cd4e764..9e36d62352ae51 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -312,6 +312,7 @@ enum OperandType : unsigned {

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread via cfe-commits


llvmbot wrote:




@llvm/pr-subscribers-clang-driver

Author: Sudharsan Veeravalli (svs-quic)


Changes

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---
Full diff: https://github.com/llvm/llvm-project/pull/118076.diff


12 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) llvm/docs/ReleaseNotes.md (+2) 
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+3) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+36) 
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) 
- (added) llvm/test/MC/RISCV/xqcia-invalid.s (+201) 
- (added) llvm/test/MC/RISCV/xqcia-valid.s (+55) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+6) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 70b7a96daf1daf..9df903115b57c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -188,6 +188,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6d50839d68953e..dc3f3aeb735f87 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled 
Load Store)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b843bb5ae43100..7c91dc07bbd3e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm11() const { return IsUImm<11>(); }
   bool isUImm16() const { return IsUImm<16>(); }
   bool isUImm20() const { return IsUImm<20>(); }
   bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
 "immediate must be a multiple of 16 bytes and non-zero in the range");
+  case Match_InvalidUImm11:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
   case Match_InvalidSImm12:
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 95658f24f79e1c..4d563046923a58 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst 
&MI, uint64_t &Size,
 "Qualcomm uC CSR custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
 "Qualcomm uC Scaled Load Store custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
+"Qualcomm uC Arithmetic custom opcode table");
   TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
   return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index ca2f868cd4e764..9e36d62352ae51 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -312,6 +312,7 @@ enum OperandType : uns

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread via cfe-commits


llvmbot wrote:



@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Sudharsan Veeravalli (svs-quic)


Changes

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---
Full diff: https://github.com/llvm/llvm-project/pull/118076.diff


12 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) llvm/docs/ReleaseNotes.md (+2) 
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+3) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+36) 
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) 
- (added) llvm/test/MC/RISCV/xqcia-invalid.s (+201) 
- (added) llvm/test/MC/RISCV/xqcia-valid.s (+55) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+6) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 70b7a96daf1daf..9df903115b57c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -188,6 +188,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6d50839d68953e..dc3f3aeb735f87 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled 
Load Store)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b843bb5ae43100..7c91dc07bbd3e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm11() const { return IsUImm<11>(); }
   bool isUImm16() const { return IsUImm<16>(); }
   bool isUImm20() const { return IsUImm<20>(); }
   bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
 "immediate must be a multiple of 16 bytes and non-zero in the range");
+  case Match_InvalidUImm11:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
   case Match_InvalidSImm12:
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 95658f24f79e1c..4d563046923a58 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst 
&MI, uint64_t &Size,
 "Qualcomm uC CSR custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
 "Qualcomm uC Scaled Load Store custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
+"Qualcomm uC Arithmetic custom opcode table");
   TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
 
   return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index ca2f868cd4e764..9e36d62352ae51 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -312,6 +31

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

2024-11-29 Thread Sudharsan Veeravalli via cfe-commits


https://github.com/svs-quic created 
https://github.com/llvm/llvm-project/pull/118076

This extension adds 11 instructions that perform integer arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

>From 42c15c348dd0cfec249058e5222475bc3620aaef Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli 
Date: Fri, 29 Nov 2024 14:25:31 +0530
Subject: [PATCH] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension

This extension adds 11 instructions that perform integer
arithmetic.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/ReleaseNotes.md |   2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |   3 +
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   2 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   8 +
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   |  36 
 llvm/lib/TargetParser/RISCVISAInfo.cpp|   3 +-
 llvm/test/CodeGen/RISCV/attributes.ll |   2 +
 llvm/test/MC/RISCV/xqcia-invalid.s| 201 ++
 llvm/test/MC/RISCV/xqcia-valid.s  |  55 +
 .../TargetParser/RISCVISAInfoTest.cpp |   6 +
 12 files changed, 319 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/xqcia-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcia-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 70b7a96daf1daf..9df903115b57c1 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -188,6 +188,7 @@
 // CHECK-NEXT: smctr1.0   'Smctr' (Control Transfer 
Records Machine Level)
 // CHECK-NEXT: ssctr1.0   'Ssctr' (Control Transfer 
Records Supervisor Level)
 // CHECK-NEXT: svukte   0.3   'Svukte' 
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
+// CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 6d50839d68953e..dc3f3aeb735f87 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -215,6 +215,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcisls` (Scaled 
Load Store)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcia` (Arithmetic)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b843bb5ae43100..7c91dc07bbd3e5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -717,6 +717,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm6() const { return IsUImm<6>(); }
   bool isUImm7() const { return IsUImm<7>(); }
   bool isUImm8() const { return IsUImm<8>(); }
+  bool isUImm11() const { return IsUImm<11>(); }
   bool isUImm16() const { return IsUImm<16>(); }
   bool isUImm20() const { return IsUImm<20>(); }
   bool isUImm32() const { return IsUImm<32>(); }
@@ -1563,6 +1564,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 9), (1 << 9) - 16,
 "immediate must be a multiple of 16 bytes and non-zero in the range");
+  case Match_InvalidUImm11:
+return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 11) - 1);
   case Match_InvalidSImm12:
 return generateImmOutOfRangeError(
 Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 95658f24f79e1c..4d563046923a58 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -686,6 +686,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst 
&MI, uint64_t &Size,
 "Qualcomm uC CSR custom opcode table");
   TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcisls, DecoderTableXqcisls32,
 "Qualcomm uC Scaled Load Store custom opcode table");
+  TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcia, DecoderTableXqcia32,
+"Qualcomm uC Arithmetic custom opcode table");
   TRY_TO_DECODE(

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (PR #118076)

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