[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-13 Thread Sudharsan Veeravalli via cfe-commits

https://github.com/svs-quic closed 
https://github.com/llvm/llvm-project/pull/119823
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-13 Thread Craig Topper via cfe-commits

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/119823
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-13 Thread Sam Elliott via cfe-commits

https://github.com/lenary approved this pull request.

LGTM, but please wait for Craig to approve as well.

https://github.com/llvm/llvm-project/pull/119823
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-12 Thread Sudharsan Veeravalli via cfe-commits

https://github.com/svs-quic updated 
https://github.com/llvm/llvm-project/pull/119823

>From 87da7f670dcd0843c27bc533f62c710053ca4c86 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli 
Date: Fri, 13 Dec 2024 12:06:33 +0530
Subject: [PATCH 1/2] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple)
 extension

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  12 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   2 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   8 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   |  58 +
 llvm/lib/TargetParser/RISCVISAInfo.cpp|   2 +-
 llvm/test/CodeGen/RISCV/attributes.ll |   2 +
 llvm/test/MC/RISCV/xqcilsm-aliases-valid.s|  35 ++
 llvm/test/MC/RISCV/xqcilsm-invalid.s  | 112 ++
 llvm/test/MC/RISCV/xqcilsm-valid.s|  35 ++
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 14 files changed, 273 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-aliases-valid.s
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index c268f75a0fd8df..715d9e414e6114 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -191,6 +191,7 @@
 // CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
+// CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Supported Profiles
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2867dcceb84fd7..f6a0dd4bf2383c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -435,6 +435,9 @@ The current vendor extensions supported are:
 ``experimental-Xqcicsr``
   LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
+``experimental-Xqcilsm``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ddee4ab8ce1b37..5d2ff17ee19848 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -223,6 +223,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcics` (Conditonal 
Select)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilsm` (Load 
Store Multiple)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7c91dc07bbd3e5..5b9946e5132e40 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -724,6 +724,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm48() const { return IsUImm<48>(); }
   bool isUImm64() const { return IsUImm<64>(); }
 
+  bool isUImm5NonZero() const {
+if (!isImm())
+  return false;
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
+   VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm8GE32() const {
 int64_t Imm;
 RISCVMCExpr::Varia

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-12 Thread Craig Topper via cfe-commits


@@ -105,6 +112,26 @@ class QCISELECTICCI funct3, string opcodestr>
   let rs1 = imm;
 }
 
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class QCILoadMultiple func2, DAGOperand InTyRs2, string opcodestr>

topperc wrote:

func -> funct

https://github.com/llvm/llvm-project/pull/119823
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-12 Thread via cfe-commits

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)


Changes

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---
Full diff: https://github.com/llvm/llvm-project/pull/119823.diff


14 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) llvm/docs/RISCVUsage.rst (+3) 
- (modified) llvm/docs/ReleaseNotes.md (+2) 
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+12) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+2) 
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+58) 
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+1-1) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) 
- (added) llvm/test/MC/RISCV/xqcilsm-aliases-valid.s (+35) 
- (added) llvm/test/MC/RISCV/xqcilsm-invalid.s (+112) 
- (added) llvm/test/MC/RISCV/xqcilsm-valid.s (+35) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index c268f75a0fd8df..715d9e414e6114 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -191,6 +191,7 @@
 // CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
+// CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Supported Profiles
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2867dcceb84fd7..f6a0dd4bf2383c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -435,6 +435,9 @@ The current vendor extensions supported are:
 ``experimental-Xqcicsr``
   LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
+``experimental-Xqcilsm``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ddee4ab8ce1b37..5d2ff17ee19848 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -223,6 +223,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcics` (Conditonal 
Select)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilsm` (Load 
Store Multiple)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7c91dc07bbd3e5..5b9946e5132e40 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -724,6 +724,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm48() const { return IsUImm<48>(); }
   bool isUImm64() const { return IsUImm<64>(); }
 
+  bool isUImm5NonZero() const {
+if (!isImm())
+  return false;
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && isUInt<5>(Imm) && (Imm != 0) &&
+   VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm8GE32() const {
 int64_t Imm;
 RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
@@ -1506,6 +1516,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
 return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
   case Match_InvalidUImm5:
 return generateImmOutOfRangeError(

[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple) extension (PR #119823)

2024-12-12 Thread Sudharsan Veeravalli via cfe-commits

https://github.com/svs-quic created 
https://github.com/llvm/llvm-project/pull/119823

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

>From 87da7f670dcd0843c27bc533f62c710053ca4c86 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli 
Date: Fri, 13 Dec 2024 12:06:33 +0530
Subject: [PATCH] [RISCV] Add Qualcomm uC Xqcilsm (Load Store Multiple)
 extension

This extension adds 6 instructions that can do multi-word load/store.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |   1 +
 llvm/docs/RISCVUsage.rst  |   3 +
 llvm/docs/ReleaseNotes.md |   2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  12 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |   2 +
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |   1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|   8 ++
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   |  58 +
 llvm/lib/TargetParser/RISCVISAInfo.cpp|   2 +-
 llvm/test/CodeGen/RISCV/attributes.ll |   2 +
 llvm/test/MC/RISCV/xqcilsm-aliases-valid.s|  35 ++
 llvm/test/MC/RISCV/xqcilsm-invalid.s  | 112 ++
 llvm/test/MC/RISCV/xqcilsm-valid.s|  35 ++
 .../TargetParser/RISCVISAInfoTest.cpp |   1 +
 14 files changed, 273 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-aliases-valid.s
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcilsm-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index c268f75a0fd8df..715d9e414e6114 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -191,6 +191,7 @@
 // CHECK-NEXT: xqcia0.2   'Xqcia' (Qualcomm uC 
Arithmetic Extension)
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
+// CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
 // CHECK-NEXT: xqcisls  0.2   'Xqcisls' (Qualcomm uC 
Scaled Load Store Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Supported Profiles
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 2867dcceb84fd7..f6a0dd4bf2383c 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -435,6 +435,9 @@ The current vendor extensions supported are:
 ``experimental-Xqcicsr``
   LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
+``experimental-Xqcilsm``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ddee4ab8ce1b37..5d2ff17ee19848 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -223,6 +223,8 @@ Changes to the RISC-V Backend
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcics` (Conditonal 
Select)
   extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilsm` (Load 
Store Multiple)
+  extension.
 
 Changes to the WebAssembly Backend
 --
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 7c91dc07bbd3e5..5b9946e5132e40 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -724,6 +724,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   bool isUImm48() const { return IsUImm<48>(); }
   bool isUImm64() const { return IsUImm<64>(); }
 
+  bool isUImm5NonZero() const {
+if (!isImm())
+  return false;
+int64_t Imm;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+bool IsConstantImm = evaluateConstantImm(getIm