[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-13 Thread via cfe-commits 

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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-13 Thread Sam Elliott via cfe-commits 

https://github.com/lenary closed 
https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-13 Thread Sam Elliott via cfe-commits 

https://github.com/lenary approved this pull request.

LGTM.

Thank you for doing this PR for Xqcili support, it's great to see interest in 
this from the RISC-V community beyond Qualcomm. In future, it would be great to 
coordinate on what you are planning to upstream, as we (Qualcomm) have 
downstream implementations of the extensions which we are in the process of 
upstreaming, and we would like to avoid duplicated work in this area.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-13 Thread Craig Topper via cfe-commits 

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-12 Thread Sudharsan Veeravalli via cfe-commits 

https://github.com/svs-quic approved this pull request.

LGTM!

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-12 Thread Sudharsan Veeravalli via cfe-commits 


@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
   def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
 } // Predicates = [HasVendorXqcilo, IsRV32]
 
+let Predicates = [HasVendorXqcili, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def QC_LI : RVInstU, (outs GPRNoX0:$rd), (ins 
simm20:$imm20),

svs-quic wrote:

I believe this has not been addressed?

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-12 Thread via cfe-commits 

u4f3 wrote:

> It looks like there are some conflicts. Please fix them before merging.
> 
> Also just noticed that you have been updating the same commit with the 
> changes requested in the reviews. Please have them as separate commits in the 
> future so that we can know what changed.

You're right. Maybe I should try not to use `git commit --amend` next time.

Rebased to main and solve those conflicts. Hope I'm doing things right.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-12 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From 52cfa2c358ba20ec20f023828ba2d8bcccb38e83 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 32 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 132 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index d9335fe502bb6..912a3ad4b6d6e 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.4   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 831e8fd5d186b..32a65d898bb31 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 3d608c636a8f6..be465bfe5dc6b 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread via cfe-commits 

llvmbot wrote:



@llvm/pr-subscribers-clang-driver

@llvm/pr-subscribers-backend-risc-v

Author: None (u4f3)


Changes

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.

---
Full diff: https://github.com/llvm/llvm-project/pull/130012.diff


11 Files Affected:

- (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) 
- (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+13) 
- (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3-2) 
- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+15) 
- (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+3-3) 
- (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) 
- (added) llvm/test/MC/RISCV/xqcili-invalid.s (+21) 
- (added) llvm/test/MC/RISCV/xqcili-valid.s (+46) 
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+3-1) 


``diff
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+   isInt<20>(fixImmediateForRV32(Imm, isRV64Imm()));
+  }
+
   bool isSImm26() const {
 if (!isImm())
   return false;
@@ -1712,6 +1722,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
   case Match_InvalidSImm26:
 return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
   (1 << 25) - 1);
+  case Match_InvalidSImm20:
+return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 19),
+  (1 << 19) - 1);
   case Match_InvalidSImm32:
 return generateImmOutOfRangeError(Operands, ErrorInfo,
   std::numeric_limits::min(),
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 6dfebc1989e92..3972a34a803e0 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -654,8 +654,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
 RISCV::FeatureVendorXqcibm,  RISCV::FeatureVendorXqcicli,
 RISCV::FeatureVendorXqcicm,  RISCV::FeatureVendorXqcics,
 RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
-RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
-RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
+RISCV::FeatureVendorXqcili,  RISCV::FeatureVendorXqcilia,
+RISCV::FeatureVendorXqcilo,  RISCV::FeatureVendorXqcilsm,
+RISCV::FeatureVendorXqcisls,
 };
 
 static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 863bfc76d45c0..96ffbfd5476b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -329,6 +329,7 @@ enum OperandType : unsigned {
   OPERAND_SIMM11,
   OPERAND_SIMM12,
   OPERAND_SIMM12_LSB0,
+  OPERAND_SIMM20,
   OPERAND_SIMM26,
   OPERAND_SIMM32,
   OPERAND_CLUI_IMM,
diff --git a/llvm/

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread Sudharsan Veeravalli via cfe-commits 

svs-quic wrote:

It looks like there are some conflicts. Please fix them before merging.

Also just noticed that you have been updating the same commit with the changes 
requested in the reviews. Please have them as separate commits in the future so 
that we can know what changed.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread Sam Elliott via cfe-commits 

https://github.com/lenary approved this pull request.

LGTM. Thanks!

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread Sudharsan Veeravalli via cfe-commits 

https://github.com/svs-quic approved this pull request.

LGTM! @lenary do you have any comments?

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From 68336aeededdd6f839134d0ace9f098d799bc2b0 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 32 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 132 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 62c6a4fd80fd4..38c49d10d7999 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index fe3b508d5c5b0..733f6947da823 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread Sudharsan Veeravalli via cfe-commits 


@@ -0,0 +1,27 @@
+# Xqcili - Qualcomm uC Load Large Immediate Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcili < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcili < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
+
+# CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0)
+# CHECK_MINUS: :[[@LINE+1]]:9: error: invalid operand for instruction
+qc.e.li 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.li x9
+
+# CHECK-PLUS: :[[@LINE+2]]:13: error: immediate must be an integer in the 
range [-2147483648, 4294967295]
+# CHECK_MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction
+qc.e.li x9, 4294967296
+
+# CHECK-PLUS: :[[@LINE+2]]:7: error: register must be a GPR excluding zero (x0)
+# CHECK_MINUS: :[[@LINE+1]]:7: error: invalid operand for instruction
+qc.li x0, 114514
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.li x10
+
+# CHECK-PLUS: :[[@LINE+2]]:12: error: immediate must be an integer in the 
range [-524288, 524287]
+# CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.li x10, 33554432

svs-quic wrote:

Please add valid instructions that print an error  like 
"error: instruction requires the following: 'Xqcili'" with CHECK-MINUS:

You can look at patches that add support for the other extensions for reference.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From b8d8e7d3f442d28f9771317c337fb650dd50aaa9 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 27 +++
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 127 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 62c6a4fd80fd4..38c49d10d7999 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index fe3b508d5c5b0..733f6947da823 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-11 Thread Sudharsan Veeravalli via cfe-commits 


@@ -0,0 +1,21 @@
+# Xqcili - Qualcomm uC Load Large Immediate Extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcili < %s 2>&1 \

svs-quic wrote:

Please add a run line with mattr=-experimental-xqcili

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-07 Thread via cfe-commits 

u4f3 wrote:

Seems that the error in `/llvm-project/clang/test/Driver/offload-Xarch.c` is 
not relevant. And I can't reproduce this error since I don't have a windows 
machine...

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-07 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From eb3abc4fa7f6f09b0400e615e5a4a7cc5c8bca89 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 21 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 62c6a4fd80fd4..38c49d10d7999 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index fe3b508d5c5b0..733f6947da823 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From 9e91a77551d81407be4fd19c4fcb4d5bdf1c1c17 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 21 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 62c6a4fd80fd4..38c49d10d7999 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index fe3b508d5c5b0..733f6947da823 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

https://github.com/u4f3 edited https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From 416c8f2c30dafccc6eda420b1d8f4adf9fa48886 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Fri, 7 Mar 2025 15:01:57 +0800
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7.0

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 llvm/docs/RISCVUsage.rst  |  3 ++
 llvm/docs/ReleaseNotes.md |  2 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  8 
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 21 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 13 files changed, 121 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 62c6a4fd80fd4..38c49d10d7999 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -456,6 +456,9 @@ The current vendor extensions supported are:
 ``experimental-Xqciint``
   LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension 
specification `__ by 
Qualcomm.  All instructions are prefixed with `qc.` as described in the 
specification. These instructions are only available for riscv32.
 
+``experimental-Xqcili``
+  LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
+
 ``experimental-Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic 
extension specification 
`__ by Qualcomm.  All 
instructions are prefixed with `qc.` as described in the specification. These 
instructions are only available for riscv32.
 
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index fe3b508d5c5b0..733f6947da823 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -107,6 +107,8 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -
 
+* Adds experimental assembler support for the Qualcomm uC 'Xqcili` (Load Large 
Immediate)
+  extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large 
Immediate Arithmetic)
   extension.
 * Adds experimental assembler support for the Qualcomm uC 'Xqcibm` (Bit 
Manipulation)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 


@@ -1358,6 +1358,12 @@ def HasVendorXqciint
   AssemblerPredicate<(all_of FeatureVendorXqciint),
  "'Xqciint' (Qualcomm uC Interrupts Extension)">;
 
+def FeatureVendorXqcili : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load 
Large Immediate Extension", []>;

u4f3 wrote:

It seems that this requirement is not explicitly specified in the spec, or I'm 
missing some part of documents somewhere. Anyway I add [FeatureStdExtZca].

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Craig Topper via cfe-commits 

https://github.com/topperc requested changes to this pull request.

Dropping my approval based on other comments.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Sudharsan Veeravalli via cfe-commits 


@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
   def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
 } // Predicates = [HasVendorXqcilo, IsRV32]
 
+let Predicates = [HasVendorXqcili, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def QC_LI : RVInstU, (outs GPRNoX0:$rd), (ins 
simm20:$imm20),

svs-quic wrote:

This can be OPC_OP_IMM_32?

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Sudharsan Veeravalli via cfe-commits 

https://github.com/svs-quic commented:

Please add entries in RISCVUsage.rst and ReleaseNotes.md.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Sudharsan Veeravalli via cfe-commits 


@@ -1358,6 +1358,12 @@ def HasVendorXqciint
   AssemblerPredicate<(all_of FeatureVendorXqciint),
  "'Xqciint' (Qualcomm uC Interrupts Extension)">;
 
+def FeatureVendorXqcili : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load 
Large Immediate Extension", []>;

svs-quic wrote:

This needs [FeatureStdExtZca] as well given that it has a 48 bit instruction.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Craig Topper via cfe-commits 


@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
   def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
 } // Predicates = [HasVendorXqcilo, IsRV32]
 
+let Predicates = [HasVendorXqcili, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def QC_LI : RVInstU, (outs GPRNoX0:$rd), (ins 
simm20:$imm20),
+  "qc.li", "$rd, $imm20">{

topperc wrote:

Space before {

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Craig Topper via cfe-commits 


@@ -588,6 +590,19 @@ let Predicates = [HasVendorXqcilo, IsRV32] in {
   def QC_E_SW: QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
 } // Predicates = [HasVendorXqcilo, IsRV32]
 
+let Predicates = [HasVendorXqcili, IsRV32] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  def QC_LI : RVInstU, (outs GPRNoX0:$rd), (ins 
simm20:$imm20),

topperc wrote:

Wrap this line to keep it under 80 characters.

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread Craig Topper via cfe-commits 

https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/130012
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[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

https://github.com/u4f3 updated https://github.com/llvm/llvm-project/pull/130012

>From 1abf892d26713b3425b1f1dc0d6834b9bd0aba70 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Wed, 5 Mar 2025 12:59:03 +
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  6 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 21 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 11 files changed, 114 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+   isInt<20>(fixImmediateForRV32(Imm, isRV64Imm()));
+  }
+
   bool isSImm26() const {
 if (!isImm())
   return false;
@@ -1712,6 +1722,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
   case Match_InvalidSImm26:
 return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
   (1 << 25) - 1);
+  case Match_InvalidSImm20:
+return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 19),
+  (1 << 19) - 1);
   case Match_InvalidSImm32:
 return generateImmOutOfRangeError(Operands, ErrorInfo,
   std::numeric_limits::min(),
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 6dfebc1989e92..3972a34a803e0 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -654,8 +654,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
 RISCV::FeatureVendorXqcibm,  RISCV::FeatureVendorXqcicli,
 RISCV::FeatureVendorXqcicm,  RISCV::FeatureVendorXqcics,
 RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
-RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
-RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
+RISCV::FeatureVendorXqcili,  RISCV::FeatureVendorXqcilia,
+RISCV::FeatureVendorXqcilo,  RISCV::FeatureVendorXqcilsm,
+RISCV::FeatureVendorXqcisls,
 };
 
 static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 863bfc76d45c0..96ffbfd5476b5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -329,6 +329,7 @@ enum OperandType : unsigned {
   OP

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

https://github.com/u4f3 created https://github.com/llvm/llvm-project/pull/130012

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.

>From f8f8c84a5abf3fc79849758d3d586b8da2b34111 Mon Sep 17 00:00:00 2001
From: u4f3 
Date: Wed, 5 Mar 2025 12:59:03 +
Subject: [PATCH] [RISCV] Add Qualcomn uC Xqcili (load large immediates)
 extension

The Xqcili extension includes a two instructions that load large immediates 
than is available with the base RISC-V ISA.

The current spec can be found at: 
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.
---
 .../Driver/print-supported-extensions-riscv.c |  1 +
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++
 .../RISCV/Disassembler/RISCVDisassembler.cpp  |  5 +-
 .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h |  1 +
 llvm/lib/Target/RISCV/RISCVFeatures.td|  6 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td   | 15 ++
 llvm/lib/TargetParser/RISCVISAInfo.cpp|  6 +--
 llvm/test/CodeGen/RISCV/attributes.ll |  2 +
 llvm/test/MC/RISCV/xqcili-invalid.s   | 21 +
 llvm/test/MC/RISCV/xqcili-valid.s | 46 +++
 .../TargetParser/RISCVISAInfoTest.cpp |  4 +-
 11 files changed, 114 insertions(+), 6 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/xqcili-invalid.s
 create mode 100644 llvm/test/MC/RISCV/xqcili-valid.s

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c 
b/clang/test/Driver/print-supported-extensions-riscv.c
index 69b76f0c4c4cd..21f79c7565295 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -202,6 +202,7 @@
 // CHECK-NEXT: xqcics   0.2   'Xqcics' (Qualcomm uC 
Conditional Select Extension)
 // CHECK-NEXT: xqcicsr  0.2   'Xqcicsr' (Qualcomm uC CSR 
Extension)
 // CHECK-NEXT: xqciint  0.2   'Xqciint' (Qualcomm uC 
Interrupts Extension)
+// CHECK-NEXT: xqcili   0.2   'Xqcili' (Qualcomm uC Load 
Large Immediate Extension)
 // CHECK-NEXT: xqcilia  0.2   'Xqcilia' (Qualcomm uC Large 
Immediate Arithmetic Extension)
 // CHECK-NEXT: xqcilo   0.2   'Xqcilo' (Qualcomm uC Large 
Offset Load Store Extension)
 // CHECK-NEXT: xqcilsm  0.2   'Xqcilsm' (Qualcomm uC Load 
Store Multiple Extension)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 
b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index b342c18bece08..372e2e2ad8ba1 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1076,6 +1076,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm20() const {
+if (!isImm())
+  return false;
+RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+int64_t Imm;
+bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
+   isInt<20>(fixImmediateForRV32(Imm, isRV64Imm()));
+  }
+
   bool isSImm26() const {
 if (!isImm())
   return false;
@@ -1712,6 +1722,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, 
unsigned &Opcode,
   case Match_InvalidSImm26:
 return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
   (1 << 25) - 1);
+  case Match_InvalidSImm20:
+return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 19),
+  (1 << 19) - 1);
   case Match_InvalidSImm32:
 return generateImmOutOfRangeError(Operands, ErrorInfo,
   std::numeric_limits::min(),
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 
b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 6dfebc1989e92..3972a34a803e0 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -654,8 +654,9 @@ static constexpr FeatureBitset XqciFeatureGroup = {
 RISCV::FeatureVendorXqcibm,  RISCV::FeatureVendorXqcicli,
 RISCV::FeatureVendorXqcicm,  RISCV::FeatureVendorXqcics,
 RISCV::FeatureVendorXqcicsr, RISCV::FeatureVendorXqciint,
-RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
-RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisls,
+RISCV::FeatureVendorXqcili,  RISCV::FeatureVendorXqcilia,
+RISCV::FeatureVendorXqcilo,  RISCV::FeatureVendorXqcilsm,
+RISCV::FeatureVendorXqcisls,
 };
 
 static constexpr FeatureBitset XSfVectorGroup = {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h 
b/

[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)

2025-03-06 Thread via cfe-commits 

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