[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-16 Thread Djordje Todorovic via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }

djtodoro wrote:

The datasheet figure might indeed be a bit misleading. While there's a separate 
load queue and store queue, it's essentially a single LSU composed of these 
integrated blocks, not distinct pipelines. We'll consider clarifying this in a 
future revision of the datasheet.

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-16 Thread Djordje Todorovic via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;

djtodoro wrote:

You are right, thanks!

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }

mshockwave wrote:

just want to double check: the datasheet says "1 load, 1 store pipe". Are there 
separate pipes for load and store within a single LSU?

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {

mshockwave wrote:

ditto, Latency is default to 1 already.

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;

mshockwave wrote:

are the divisions pipelined? In the programmer's reference, both integer and 
floating point divisions' "Rate" (i.e. ReleaseAtCycle) columns are empty. I 
thought that means non-pipelined, which matches what you wrote for floating 
point divisions below (i.e. Latency == ReleaseAtCycles), but it doesn't seems 
to be the case for integer division here. Is this intentional?

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+
+// Handle CTI Pipeline.
+let Latency = 1 in {

mshockwave wrote:

ditto

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 0 in {
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 3 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 7 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 4 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+let Latency = 8, ReleaseAtCycles = [5] in {
+def : WriteRes;
+def : WriteRes;
+}
+
+def : WriteRes;
+
+def : WriteRes;
+def : WriteRes;
+
+// Handle CTI Pipeline.
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle FPU Pipelines.
+def p8700FPQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueFPUS : ProcResource<1> { let Super = p8700FPQ; }
+def p8700IssueFPUL : ProcResource<1> { let Super = p8700FPQ; }
+def p8700FpuApu   : ProcResource<1>;

mshockwave wrote:

nit: could you align the position of ':' with that in line 147?

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Min-Yih Hsu via cfe-commits


@@ -0,0 +1,290 @@
+//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+
+//===--===//
+// P8700 - a RISC-V processor by MIPS.
+// Pipelines:
+//   - 2 Integer Arithmetic and Logical Units (ALU and AL2)
+//   - Multiply / Divide Unit (MDU)
+//   - Branch Unit (CTI)
+//   - Load Store Unit (LSU)
+//   - Short Floating Point Pipe (FPUS)
+//   - Long Floating Point Pipe (FPUL)
+//===--===//
+
+def MIPSP8700Model : SchedMachineModel {
+  int IssueWidth = 4;
+  int MicroOpBufferSize = 96;
+  int LoadLatency = 4;
+  int MispredictPenalty = 8;
+  let CompleteModel = 0;
+}
+
+let SchedModel = MIPSP8700Model in {
+// Handle ALQ Pipelines.
+// It contains 1 ALU Unit only.
+def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
+
+// Handle AGQ Pipelines.
+def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
+def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
+def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
+def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
+
+// Handle Multiply Divide Pipe.
+def p8700GpDiv : ProcResource<1>;
+def p8700GpMul : ProcResource<1>;
+
+let Latency = 1 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+
+// Handle zba.
+def : WriteRes;
+def : WriteRes;
+}
+
+// Handle zbb.
+let Latency = 2 in {
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+def : WriteRes;
+}
+let Latency = 1 in {

mshockwave wrote:

Latency is default to 1 already I believe

https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Michael Maitland via cfe-commits

https://github.com/michaelmaitland edited 
https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Michael Maitland via cfe-commits

https://github.com/michaelmaitland commented:

Please split the processor definition and scheduler model into their own 
patches.

See:
https://github.com/llvm/llvm-project/commit/867ece181afe59aa020d365928169d2ebdc7d74a
https://github.com/llvm/llvm-project/commit/373d9d72145cd40c9dc00abefd14632763a2987b




https://github.com/llvm/llvm-project/pull/119885
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[clang] [llvm] [RISCV] Add scheduling model for mips p8700 CPU (PR #119885)

2024-12-13 Thread Djordje Todorovic via cfe-commits

https://github.com/djtodoro edited 
https://github.com/llvm/llvm-project/pull/119885
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