[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
weiguozhi wrote: > This causes a substantial compile-time regression (around 0.5% on average): > https://llvm-compile-time-tracker.com/compare.php?from=71122e716c7f507cb98df69961dbce21a187aa91&to=82ea1d26eca4bb8d12513d29a71536c35f3ff47b&stat=instructions:u > It does seem to have a positive optimization impact on stage2 builds though. > > Can you please analyze what the cause of the compile-time regression is and > mitigate it? Glad to see it has real world performance improvement, will try to find out some compile time improvements. https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `ml-opt-devrel-x86-64`
running on `ml-opt-devrel-x86-64-b2` while building `clang,llvm` at step 6
"test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/175/builds/3996
Here is the relevant piece of the build log for the reference
```
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
TEST 'LLVM :: CodeGen/MLRegAlloc/dev-mode-logging.ll'
FAILED
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 6
/b/ml-opt-devrel-x86-64-b1/build/bin/llc -o /dev/null
-mtriple=x86_64-linux-unknown -regalloc=greedy
-regalloc-enable-advisor=development
-regalloc-training-log=/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1
<
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/Inputs/input.ll
# executed command: /b/ml-opt-devrel-x86-64-b1/build/bin/llc -o /dev/null
-mtriple=x86_64-linux-unknown -regalloc=greedy
-regalloc-enable-advisor=development
-regalloc-training-log=/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1
# RUN: at line 8
"/usr/bin/python3"
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/../../../lib/Analysis/models/log_reader.py
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1
>
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable
# executed command: /usr/bin/python3
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/../../../lib/Analysis/models/log_reader.py
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1
# RUN: at line 9
/b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --input-file
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
--check-prefixes=CHECK,NOML
# executed command: /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --input-file
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
--check-prefixes=CHECK,NOML
# .---command stderr
# |
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll:31:15:
error: CHECK-NEXT: is not on the line after the previous match
# | ; CHECK-NEXT: observation: 1
# | ^
# |
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable:242:1:
note: 'next' match was here
# | observation: 10
# | ^
# |
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable:49:10:
note: previous match ended here
# | reward: 0.0
# | ^
# |
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable:50:1:
note: non-matching line after previous match is here
# | observation: 2
# | ^
# |
# | Input file:
/b/ml-opt-devrel-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-logging.ll.tmp1.readable
# | Check file:
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-logging.ll
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<
# |.
# |.
# |.
# | 44: use_def_density:
0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.05077143386006355,1.0,0.014165595173835754,0.014222974888980389,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.019454877823591232
# | 45: max_stage:
0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4
# | 46: min_stage:
0,0,0,0,0,0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4
# | 47: progress: 0.888955116272
# | 48: index_to_evict: 11
# | 49: reward: 0.0
# | next:31'0 { search range start (exclusive)
# | 50: observation: 2
# | 51: mask:
0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1
# | 52: is_free:
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
# | 53: nr_urgent:
0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0
# | 54: nr_broken_hints:
0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0
...
```
https://github.com/llvm/llvm-project/pull/220090
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[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
llvm-ci wrote: LLVM Buildbot has detected a new failure on builder `ml-opt-dev-x86-64` running on `ml-opt-dev-x86-64-b2` while building `clang,llvm` at step 6 "test-build-unified-tree-check-all". Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/47170 Here is the relevant piece of the build log for the reference ``` Step 6 (test-build-unified-tree-check-all) failure: test (failure) TEST 'LLVM :: CodeGen/MLRegAlloc/dev-mode-prio-logging.ll' FAILED Exit Code: 1 Command Output (stdout): -- # RUN: at line 6 /b/ml-opt-dev-x86-64-b1/build/bin/llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development -regalloc-priority-training-log=/b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1 < /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/Inputs/input.ll # executed command: /b/ml-opt-dev-x86-64-b1/build/bin/llc -o /dev/null -mtriple=x86_64-linux-unknown -regalloc=greedy -regalloc-enable-priority-advisor=development -regalloc-priority-training-log=/b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1 # RUN: at line 10 "/usr/bin/python3" /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/../../../lib/Analysis/models/log_reader.py /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1 > /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable # executed command: /usr/bin/python3 /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/../../../lib/Analysis/models/log_reader.py /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1 # RUN: at line 11 /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --input-file /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-prio-logging.ll --check-prefixes=CHECK,NOML # executed command: /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --input-file /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/dev-mode-prio-logging.ll --check-prefixes=CHECK,NOML # RUN: at line 12 diff /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt # executed command: diff /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt # .---command stdout # | *** /b/ml-opt-dev-x86-64-b1/build/test/CodeGen/MLRegAlloc/Output/dev-mode-prio-logging.ll.tmp1.readable # | --- /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/MLRegAlloc/Inputs/reference-prio-log-noml.txt # | *** # | *** 237,399 # | li_size: 0 # | stage: 0 # | weight: 0.0 # | ! priority: 2684354816.0 # | reward: 0.0 # | observation: 40 # | li_size: 0 # | stage: 0 # | weight: 0.0 # | ! priority: 2684354560.0 # | reward: 0.0 # | observation: 41 # | li_size: 0 # | stage: 0 # | weight: 0.0 # | priority: 2684357888.0 # | reward: 0.0 # | - observation: 42 # | - li_size: 0 # | - stage: 0 # | - weight: 0.0 # | - priority: 2684354816.0 # | - reward: 0.0 # | - observation: 43 # | - li_size: 0 # | - stage: 0 # | - weight: 0.0 # | - priority: 2684358144.0 ... ``` https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
nikic wrote: This causes a substantial compile-time regression (around 0.5% on average): https://llvm-compile-time-tracker.com/compare.php?from=71122e716c7f507cb98df69961dbce21a187aa91&to=82ea1d26eca4bb8d12513d29a71536c35f3ff47b&stat=instructions:u It does seem to have a positive optimization impact on stage2 builds though. Can you please analyze what the cause of the compile-time regression is and mitigate it? https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
https://github.com/weiguozhi closed https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
https://github.com/hstk30-hw approved this pull request. https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
weiguozhi wrote: I will merge this pr next week if there are no other comments. https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
david-xl wrote: LGTM https://github.com/llvm/llvm-project/pull/220090 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
@@ -1296,3 +1296,13 @@ bool X86RegisterInfo::isNonRex2RegClass(const
TargetRegisterClass *RC) const {
return true;
}
}
+
+unsigned X86RegisterInfo::getCSRFirstUseCost(const MachineFunction &MF) const {
+ // If PPX is implemented, push/pop pairs don't access memory.
+ const X86Subtarget &ST = MF.getSubtarget();
+ if (ST.is64Bit() && ST.hasPPX())
+return 0;
+
+ // push + pop.
weiguozhi wrote:
getCSRFirstUseCost returns target specific property, it is determined by ISA
and/or micro architecture, it should not be tuned by user. Users should always
tune this optimization through -regalloc-csr-cost-scale.
The actual CSRCost computation formula is
```
CSRCost = getCSRFirstUseCost * EntryFreq * CostScale / 100;
```
Tune getCSRCostScale/-regalloc-csr-cost-scale for this expression is enough.
https://github.com/llvm/llvm-project/pull/220090
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[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
@@ -1296,3 +1296,13 @@ bool X86RegisterInfo::isNonRex2RegClass(const
TargetRegisterClass *RC) const {
return true;
}
}
+
+unsigned X86RegisterInfo::getCSRFirstUseCost(const MachineFunction &MF) const {
+ // If PPX is implemented, push/pop pairs don't access memory.
+ const X86Subtarget &ST = MF.getSubtarget();
+ if (ST.is64Bit() && ST.hasPPX())
+return 0;
+
+ // push + pop.
david-xl wrote:
what I meant is to also introduce another option regalloc-csr-first-use-cost.
https://github.com/llvm/llvm-project/pull/220090
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[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
@@ -1296,3 +1296,13 @@ bool X86RegisterInfo::isNonRex2RegClass(const
TargetRegisterClass *RC) const {
return true;
}
}
+
+unsigned X86RegisterInfo::getCSRFirstUseCost(const MachineFunction &MF) const {
+ // If PPX is implemented, push/pop pairs don't access memory.
+ const X86Subtarget &ST = MF.getSubtarget();
+ if (ST.is64Bit() && ST.hasPPX())
+return 0;
+
+ // push + pop.
david-xl wrote:
Better controlled by an option instead of hard coded with 2.
https://github.com/llvm/llvm-project/pull/220090
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[clang] [llvm] [RegAlloc] [X86] Enable callee saved register optimization for x86 (PR #220090)
@@ -182,6 +182,11 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
}
+
+ unsigned getCSRFirstUseCost(const MachineFunction &MF) const override;
+ unsigned getCSRCostScale(const MachineFunction &MF) const override {
+return 30;
david-xl wrote:
Add an option to control the scale.
https://github.com/llvm/llvm-project/pull/220090
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