Re: [coreboot] Dual SPI Flash

Hi, the schematic looks good. Sorry I haven't noticed this thread earlier. I don't know what's your mainboard, but I had some problems with mine since EFI writes to flash during power up?/down? cycles and doesn't like hot switched chip during poweroff. Anyways, better be prepared to use external p

Re: [coreboot] FILO managed by Gerrit and Jenkins now, also coreboot patchwork status

> > FILO is now managed by Gerrit, using Jenkins for build-testing it. It uses > the latest libpayload of coreboot to validate that things work. > Hi, I would prefer that patch mails have a [FILO] tag instead of [coreboot]. Anyways, great improvement! Thanks, Tadas -- coreboot mailing list: core

Re: [coreboot] [PATCH] Adding Jetway J7BXAN to mainboards and some Pentium 3 Processors to Slot 1 Category.

Good start for learning git :) Now drop backup files that name ends with tilde symbol like this: src/mainboard/jetway/j7bxan/Kconfig~ Then, try to rebase to current tree commit, as I can't apply the patch to freshly cloned tree. P.S. try that copies detection, so less text to review. Thanks, Tada

Re: [coreboot] Creating patches

> I made some changes in the POST source code. As Tadas said, I added > "post_code(0xii);" where ii=20,21,22to various files. Should I > revert those back? > I think we should keep them and use ii=E0,E1,E2,E3.as errors. But > then it would restrict it to only 10 numbers. What do you thin

Re: [coreboot] POST code error "EE"

Hi, nice to hear it boots :) I believe you have git installed, and downloaded tree with git clone command. So in directory src/mainboard/jetway/j7bxan run: "git add ." this will start tracking j7bxan dir files. Use git add to any other files if you have created them. then in the root coreboot dir

Re: [coreboot] POST code error "EE"

> But the keyboard is not working so are the serial ports. You could look if the right superio is selected in the config. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] POST code error "EE"

> Coreboot started working. It didn't give any error. That's great to hear it! One more board will be supported :) > But the keyboard is not working so are the serial ports. The Null > modem cable is working. I checked it with HyperTerminal and minicom. You could try extracting pirq table from

Re: [coreboot] POST code error "EE"

Is your serial cable really working? I recommend you to remove unneeded microcode updates. Check what is your cpu model/cpuid and remove unneded stuff like I did: for example I have modified these files: ./cpu/intel/slot_1/Makefile.inc // leave only your models ./cpu/intel/model_65x/model_65x_init

Re: [coreboot] POST code error "EE"

Also you could comment that line where you get post code in ./arch/x86/lib/c_start.S:85: so you could see the last post code you want. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] POST code error "EE"

> 10,11,40,24,25,55,66,9b > > > 24 is ./cpu/intel/model_6ex/cache_as_ram.inc:254: > 25 is ./cpu/intel/model_106cx/cache_as_ram.inc:244: could you add more post codes somewhere around this: ./boot/hardwaremain.c:105: cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload"); -- c

Re: [coreboot] POST code error "EE"

On Pn, 2011-08-19 at 21:55 +0530, Abhinav Hardikar wrote: > Hi, > > > I did as you said and the POST code referred to > ./arch/x86/lib/c_start.S:85: > > > > And no I don't get any serial messages. > > > Thanx, > Abhinav Please when replying use "Reply to all" or manually make sure that

Re: [coreboot] POST code error "EE"

> I am trying to use coreboot with my mobo. Its a Jetway J7BXAN v2.1 > with i440BX NB, 82371EB SB and W83977EF SuperIO. > I tried many coreboot images of various mobos with the same specs but > I get stuck on 0xee code and Source code says: > > > "0xee Not supposed to get here" Hi there, if yo

Re: [coreboot] libpci accesses in CAR, I need a suggestion

> There will be a problem leaving the XIP area cached while trying to > write to the flash. At the least this means it's not possible to write > the whole flash. Is this intended? What's the plan here? Should it be possible to map flash contents in cache to somewhat non existing location? Than

Re: [coreboot] libpci accesses in CAR, I need a suggestion

Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included: x86_setu

Re: [coreboot] ASRock e350m1 problems

> It seems like it might not be able to read SPD at all. It is possible > your DIMM has SMBus signaling difficulty when run at 400 KHz. You could > try running the SMBus at the default frequency (93750 KHz) by removing > the last statement in function setupFch in file dimmSpd.c: > > static void s

Re: [coreboot] [RFC] flashrom as a payload requirements, for updating firmware without OS help.

> > When using SeaBios you can select another payload (flashrom) > > to execute instead of loading OS. Also for payload development, > little > > trimmed SeaBios with CBFS support could be used - this invokes > flashrom > > or the development payload or even another full-featured SeaBios. > This w

[coreboot] [RFC] flashrom as a payload requirements, for updating firmware without OS help.

Hi, legacy BIOS provided flasher, to update firmware image to better one (via floppy, usb, hdd...). Users were provided with working images, so the possibility to brick was low. If our codebase is ready, I mean the default settings build the right image, we may want to provide similar tool too. Wh

[coreboot] Triggering another payload

This one is not bad for triggering another payload (flashrom) via key press or console input. Unfortunately it works only with PS/2 keyboard. Signed-off-by: Tadas Slotkus diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c index 3d15b55..7726afd 100644 --- a/src/boot/hardwaremain.c

Re: [coreboot] [RFC] Universal panic-room serial console, for x86 BIOS bootblock

> But part of the reason I posted is also to find out what the current > coreboot plans with regards to the panic-room implementation are, > especially as there is a GSoC project for it. Has the set of feature, > and how they should be implemented, already been agreed on, or is it > still open

Re: [coreboot] Question about USB support in libpayload / FILO

> What have other folks experiences been with the EHCI driver in > libpayload? > > Steve > Hi, I had problems with USB2.0 expansion card and flash drive attached. It stopped with this log: > 05.830: FILO version 0.6.0 (ts@ts-laptop) Sat Dec 18 23:35:10 EET 2010 > 05.844: 00:07.2 7112:8086

Re: [coreboot] ASRock e350m1 problems

> Just to completely rule out the bad SPD idea, can you please dump the > SPD content when you boot with the production BIOS? i2cdump output > (ASCII) or raw output from sysfs would be great. Then we can plug it > into bc and confirm that the checksum is correct. This would also be a > good way to

Re: [coreboot] ASRock e350m1 problems

Hi, thank you all for the quick reply. > If the DIMMs work with the production BIOS but not with your BIOS, it is > possible that you are using low cost modules that do not have a valid > SPD checksum. The coreboot project is configured to validate the SPD > checksum, while the Asrock productio

[coreboot] ASRock e350m1 problems

Hi, just compiled coreboot for e350m1, flashed original flashchip and got this (log attached) everytime I power on or reset my system. Any hints? Thanks, Tadas coreboot-4.0-r Tue Jul 5 21:01:54 EEST 2011 starting... BSP Family_Model: 00500f10 cpu_init_detectedx = Got past sb800_earl

[coreboot] [RFC][PATCH 0/2] SerialICE for coreboot.

This is for testing/developing purpose, not for merging. SerialICE in coreboot would be great for developing at least CPUs cache init code. This strategy makes use of early serial functions directly from coreboot tree. This is with example for one board (copy from romstage early serial code for y

[coreboot] [PATCH 2/2] SerialICE patch

Add serial init function example to use coreboot early serial funcions Add selection which cpuid or msr functions to use (coreboot's or serialice's) Addapt for coreboot Signed-off-by: Tadas Slotkus --- src/arch/x86/SerialICE/io.h|8 +++--- src/arch/x86/SerialICE/serial.c

[coreboot] [PATCH 1/2] SerialICE files, receive function for romcc_console, bootblock_simple example

Copy required SerialICE files (not patched yet), add receive byte function to romcc_console, add SerialICE to bootblock_simple SerialICE revision: 107 Signed-off-by: Tadas Slotkus --- src/arch/x86/SerialICE/io.h | 195 ++ src/arch/x86/SerialICE/serial.c

[coreboot] Flashrom as a payload with usb flash drive support

hanks, Tadas Slotkus >From 4a32d7dca4f8ccdca655ba5b164554212df6d83a Mon Sep 17 00:00:00 2001 From: Tadas Slotkus Date: Fri, 1 Jul 2011 00:38:34 +0300 Subject: [PATCH] coreboot mods for flashrom payload This enables to choose flashrom payload, when using SEABIOS with cbfs support also li

[coreboot] [PATCH] Temporary libpayload fixes for flashrom as a payload

Signed-off-by: Tadas Slotkus --- payloads/libpayload/drivers/serial.c|2 +- payloads/libpayload/include/libpayload.h|1 + payloads/libpayload/lib/libpayload.ldscript |4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers

[coreboot] One more student would like to participate in GSoC

ld choose which flash chip(s) are needed to be included in our payload's build. The rom image might be transferred through serial port. But payload needs RAM, so this idea is in discussion list. The first idea would be the primary objective for me. What do you think? Thanks, Tadas Slotkus P.S

[coreboot] [PATCH] FILO: USB_DISK by default should be disabled (trivial)

d be great if you could suggest how to link that dependency. Trivial fix. If we are using default config we don't have USB enabled in libpayload's config. Signed-off-by: Tadas Slotkus Index: Config.in === --- Config.