On Wed, 26 Feb 2014 16:00:46 +
Mark Rutland wrote:
> On Tue, Feb 25, 2014 at 03:50:32PM +, Arnd Bergmann wrote:
> > On Tuesday 25 February 2014 19:47:57 Alexander Shiyan wrote:
> > > Вторник, 25 февраля 2014, 16:33 +01:00 от Arnd Bergmann :
> > > > On Tuesday 25 February 2014 19:27:47 Ale
On Fri, Feb 28, 2014 at 09:34:33AM -0700, Stephen Warren wrote:
> On 02/27/2014 10:58 PM, Mark Brown wrote:
> > I'm not sure that renaming the property really deals with the concerns
> > though since drivers still all need to manually add support for this,
> > shouldn't there be an interrupt contr
On Fri, 2014-02-28 at 04:00PM -0800, Soren Brinkmann wrote:
> Add a driver for the Cadence I2C controller. This controller is for
> example found in Xilinx Zynq.
>
> Signed-off-by: Soren Brinkmann
> ---
> .../devicetree/bindings/i2c/i2c-cadence.txt| 21 +
> MAINTAINERS
2014-01-20 17:35 GMT+08:00 Barry Song <21cn...@gmail.com>:
> 2014/1/20 Vinod Koul :
>> On Wed, Jan 08, 2014 at 10:12:49PM +0800, Barry Song wrote:
>>> From: Barry Song
>>>
>>> move to support of_dma_request_slave_channel() and
>>> dma_request_slave_channel.
>>> we add a xlate() to let dma clients
On Fri, Feb 28, 2014 at 06:07:05PM -0800, Tanmay Inamdar wrote:
> Earlier email did not deliver to mailing lists because of plain text
> setting problem on my side. Apologies for spamming. Sending it again.
>
> Hello Liviu,
>
Hello Tanmay,
> While porting X-Gene PCIe driver to v2 series, follow
On Fri, 2014-02-28 at 04:00PM -0800, Soren Brinkmann wrote:
> Signed-off-by: Soren Brinkmann
> ---
> arch/arm/boot/dts/zynq-7000.dtsi | 22
> arch/arm/boot/dts/zynq-zc702.dts | 76
>
> arch/arm/boot/dts/zynq-zc706.dts | 68 +++
Earlier email did not deliver to mailing lists because of plain text
setting problem on my side. Apologies for spamming. Sending it again.
Hello Liviu,
While porting X-Gene PCIe driver to v2 series, following problems were observed.
1. In 'of_create_pci_host_bridge' function, bus_range is define
On Fri, Feb 28, 2014 at 9:28 AM, Lucas Stach wrote:
> This series cleans up the PCI irq mapping for all
> the ARM PCI host drivers, so they handle it in the
> way defined in the common PCI bindings.
>
> Testing appreciated.
>
> Lucas Stach (7):
> ARM: dts: tegra: add PCIe interrupt mapping prope
contact me for details of $21.4m transfer.
The information contained in this electronic communication is intended solely
for the individual(s) or entity to which it is addressed. It may contain
proprietary, confidential and/or legally privileged information. Any review,
retransmission, dissemi
Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'next' branch of Felipe Balbi's 'usb.git' repo.
Changes in version 2:
- restored devm_clk_get() call and
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts/zynq-7000.dtsi | 22
arch/arm/boot/dts/zynq-zc702.dts | 76
arch/arm/boot/dts/zynq-zc706.dts | 68 +++
3 files changed, 166 insertions(+)
diff --git a/arch/a
Add a driver for the Cadence I2C controller. This controller is for
example found in Xilinx Zynq.
Signed-off-by: Soren Brinkmann
---
.../devicetree/bindings/i2c/i2c-cadence.txt| 21 +
MAINTAINERS| 1 +
drivers/i2c/busses/Kconfig
On Friday 28 February 2014 06:14 PM, Arnd Bergmann wrote:
> On Friday 28 February 2014 17:56:40 Santosh Shilimkar wrote:
>> The Packet DMA driver sets up the dma channels and flows for the
>> QMSS(Queue Manager SubSystem) who triggers the actual data movements
>> across clients using destination qu
Add device tree binding for ImgTec Consumer Infrared block, specifically
major revision 1 of the hardware.
Signed-off-by: James Hogan
Acked-by: Rob Herring
Cc: Mauro Carvalho Chehab
Cc: linux-me...@vger.kernel.org
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicetre
Add base driver for the ImgTec Infrared decoder block. The driver is
split into separate components for raw (software) decode and hardware
decoder which are in following commits.
Signed-off-by: James Hogan
Cc: Mauro Carvalho Chehab
Cc: linux-me...@vger.kernel.org
Cc: Grant Likely
Cc: Rob Herrin
Add a driver for the ImgTec Infrared decoder block. Two separate rc
input devices are exposed depending on kernel configuration. One uses
the hardware decoder which is set up with timings for a specific
protocol and supports mask/value filtering and wake events. The other
uses raw edge interrupts a
From: Sandeep Nair
QMSS(Queue Manager Sub System) uses PDSPs to implement various
QM related functions like packet accumulation, QoS or event
management.
Patch adds firmware blob for the QMSS accumulator
functionality.
Cc: Greg Kroah-Hartman
Cc: Kumar Gala
Cc: Olof Johansson
Cc: Arnd Bergman
Based on earlier thread "https://lkml.org/lkml/2013/10/7/662"; and
further discussion at Kernel Summit'2013, series creates 'driver/soc'
for drivers which are very SOC specific.
Then we add the Keystone QMSS (Queue Manager SubSystem) driver.
The QMSS found on Keystone SOCs is one of the main hardw
Based on earlier thread "https://lkml.org/lkml/2013/10/7/662"; and
further discussion at Kernel Summit'2013, it was agreed to create
'driver/soc' for drivers which are quite SOC specific.
Lets take the discussion forward with this patch.
Cc: Greg Kroah-Hartman
Cc: Kumar Gala
Cc: Paul Walmsley
On Friday 28 February 2014 17:56:40 Santosh Shilimkar wrote:
> The Packet DMA driver sets up the dma channels and flows for the
> QMSS(Queue Manager SubSystem) who triggers the actual data movements
> across clients using destination queues. Every client modules like
> NETCP(Network Coprocessor), S
* Suman Anna [140228 12:46]:
> Hi Joerg, Tony,
>
> This is an updated series of the OMAP IOMMU DT adaptation intended
> for 3.15 merge window, addressing the comments from the v2 series.
> This series is rebased onto 3.14-rc4, and the only change to bindings
> is to drop the dma-window property.
From: Sandeep Nair
The Packet DMA driver sets up the dma channels and flows for the
QMSS(Queue Manager SubSystem) who triggers the actual data movements
across clients using destination queues. Every client modules like
NETCP(Network Coprocessor), SRIO(Serial Rapid IO) and CRYPTO
Engines has its
* yegorsli...@googlemail.com [140227 23:22]:
> From: Yegor Yefremov
>
> Enable second USB channel and set it into 'host' mode.
>
> Signed-off-by: Yegor Yefremov
Thanks applying into omap-for-v3.15/dt.
Tony
> ---
> arch/arm/boot/dts/am335x-evmsk.dts |9 +
> 1 files changed, 9 in
* Roger Quadros [140227 06:21]:
> Hi,
>
> This patchset brings up USB Host ports and Ethernet port on
> the OMAP5 uEVM board.
>
> It also does some cleanup with respect to DT clock binding
> for the mfd/omap-usb-host driver.
>
> Please queue these for -next.
>
> Lee,
>
> I've folded some plat
* Tero Kristo [140213 01:04]:
> default-rate property can now be used to define default rates for clocks,
> which get configured during boot.
>
> Signed-off-by: Tero Kristo
This can go with the drivers/clk patches as far as I'm concerned:
Acked-by: Tony Lindgren
> ---
> arch/arm/mach-omap2/
* Marek Belisko [140125 13:31]:
Hmm care to add descriptions and repost the remaining patches
that I did not yet pick up for the fixes?
> Signed-off-by: NeilBrown
Hmm should this also have From: NeilBrown ?
Also, while at it, maybe change your long time habit of adding
a period to the end of
* Belisko Marek [140228 14:42]:
> Sure . Thanks for notice ;). It there possibility that missing patches
> go to 3.15?
Sure if you update them over next few days.
Regards,
Tony
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.ke
* Matt Porter [140129 13:02]:
> Add missing interrupt properties to the ecap0, ecap1, and ecap2
> nodes.
>
> Signed-off-by: Matt Porter
Thanks taking this patch only into omap-for-v3.15/dt, the rest
should go via the driver mailing lists.
Regards,
Tony
> ---
> arch/arm/boot/dts/am33xx.dtsi
* Tero Kristo [140220 09:00]:
> On 01/29/2014 08:19 PM, Nishanth Menon wrote:
> >OMAP34xx, AM3517 and OMAP36xx platforms use dpll1 clock.
> >
> >OMAP443x, OMAP446x, OMAP447x, OMAP5, DRA7, AM43xx platforms use
> >dpll_mpu clock.
> >
> >Latency used is the generic latency defined in omap-cpufreq
> >
Hi Tony,
On Fri, Feb 28, 2014 at 11:25 PM, Tony Lindgren wrote:
> * Marek Belisko [140125 13:31]:
>
> Hmm care to add descriptions and repost the remaining patches
> that I did not yet pick up for the fixes?
Sure I'll do.
>
>> Signed-off-by: NeilBrown
>
> Hmm should this also have From: NeilBro
On 28.02.14, 22:51, Josh Cartwright wrote:
[..]
>> +sg_init_one(&sg, data_buf, sizeof(data_buf));
>> +memset(data_buf, 0, sizeof(data_buf));
>> +mmc_wait_for_req(mmc, &mrq);
>> +
>> +if (!cmd.error && !data.error &&
>> +!memcmp(data_bu
* Tomi Valkeinen [140214 06:38]:
> Hi,
>
> On 14/02/14 16:20, Christoph Fritz wrote:
> > Full device tree support for omapdss is not yet accomplished. Until
> > then, init display by legacy platform code.
> >
> > Signed-off-by: Christoph Fritz
> > ---
> > arch/arm/mach-omap2/dss-common.c |
* Christoph Fritz [140214 06:24]:
> Full device tree support for clock control, especially to set frequencies,
> is not yet accomplished. Until then, configure the 24Mhz of sys_clkout2 to
> feed an USB-Hub here.
Hmm would like to see Tero's comments on this, I wonder if we should
wait on this to
* Peter Ujfalusi [140124 00:21]:
> Hi Benoit,
>
> OMAP: Put the audio nodes to disabled styate by default and board dts files
> should
> enable the nodes which is used on the board.
>
> am335x: correct the audio mclk clock. This patch has been marked to go to 3.13
> stable as well.
Looks
* Jack Mitchell [140122 03:09]:
> From: Jack Mitchell
>
> Devicetree include file for setting up the am335x mcasp bus, i2c-2
> bus, and audio codec required for a functioning BeagleBone Audio Cape.
>
> Signed-off-by: Jack Mitchell
> Signed-off-by: Matt Porter
> ---
> arch/arm/boot/dts/am335x
* Suman Anna [140113 16:29]:
> Hi,
>
> This series updates the existing OMAP hwspinlock DT nodes to have a
> #hwlock-cells property as suggested by Mark Rutland [1], and adds the
> hwspinlock nodes for two other newer SoCs - DRA7xx and AM43xx.
>
> Posting the series separately from the driver DT
On 28.02.14, 18:51, Kumar Gala wrote:
>
> On Feb 28, 2014, at 5:24 AM, Georgi Djakov wrote:
>
>> This patch adds implementation for platform specific tuning in order to
>> support
>> HS200 bus speed mode on Qualcomm SDHCI controller.
>>
>> Signed-off-by: Asutosh Das
>> Signed-off-by: Venkat Go
* Sourav Poddar [131205 01:50]:
> On Wednesday 27 November 2013 01:00 PM, Sourav Poddar wrote:
> >The patch series adds support for enabling pwm backlight, i2c2, spi and
> >matrix gpio keys on am43x-gp-evm.
> >
> >Done on top of 3.13-rc1 + tero clock series(1)
> >
> >[1]: https://patchwork.kernel.
* Tero Kristo [140214 05:50]:
> On 02/14/2014 03:25 AM, Sebastian Reichel wrote:
> >On Thu, Feb 13, 2014 at 02:49:14PM -0800, Tony Lindgren wrote:
> >>* Sebastian Reichel [140121 06:39]:
> >>>update aliases for the ssi clocks ssi_ssr_fck, ssi_sst_fck and ssi_ick
> >>>to make them consistent for o
* Sricharan R [140205 06:13]:
> Tony,
>
> On Wednesday 05 February 2014 06:41 PM, Sricharan R wrote:
> > On Tuesday 04 February 2014 09:44 PM, Thomas Gleixner wrote:
> >> On Mon, 3 Feb 2014, Sricharan R wrote:
> I already have your reviewed-by tag for the first patch in this series.
>
>
* Sathya Prakash M R [131203 00:35]:
> Add device node for DSS module for AM4372. Both the
> AM437x-Gp evm and Am43x-Epos evm use the same LCD panel.
> The lcd timings are added in respective dts files.
> Adds display pinctrl and enables required gpio.
> Also set the right parent clock to the DSS
Some PWM outputs are wired such that the LED they're controlling is
connected to supply rather than ground. Therefore, the duty cycle
needs to be inverted to make the LED behave as it should do.
We also provide a way to specify the default brightness when a
trigger is not specified.
Signed-off-b
The front panel LED on the Cubox-i is driven by one of the iMX6 PWM
channels, and is wired between the PWM output and supply. This means
that outputting a low level results in the LED being turned on, so we
need the duty cycle inverted.
There's a question about whether the output inversion should
Hello.
On 02/27/2014 06:56 PM, Mark Rutland wrote:
Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov
---
This patch is against the 'next' branch of Felipe Balbi's 'usb.git' repo.
On 02/27/2014 06:35 PM, Philipp Zabel wrote:
This patch adds a new struct of_endpoint which is then embedded in struct
v4l2_of_endpoint and contains the endpoint properties that are not V4L2
(or even media) specific: the port number, endpoint id, local device tree
node and remote endpoint phandle
Hi Philipp,
Just couple minor comments...
On 02/27/2014 06:35 PM, Philipp Zabel wrote:
The device tree graph bindings as used by V4L2 and documented in
Documentation/device-tree/bindings/media/video-interfaces.txt contain
generic parts that are not media specific but could be useful for any
sub
On 02/27/2014 06:35 PM, Philipp Zabel wrote:
If of_graph_get_next_endpoint is given a parentless node instead of an
endpoint node, it is clearly a bug.
Signed-off-by: Philipp Zabel
---
drivers/of/base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/base.c
On Sat, Feb 22, 2014 at 04:53:37PM +0100, Hans de Goede wrote:
> + /*
> + * set PHY Paremeters, two steps to configure the GPR13,
> + * one write for rest of parameters, mask of first write
> + * is 0x07ff, and the other one write for setting
>
Hi.
A couple of suggestions and a couple of questions.
I made the patch below against your patches to.
o Look for ".compatible = "foo" strings in .c and .h files too
o Improve the vendor name match in vendor-prefix.txt by only
matching the exact vendor name at the beginning of lines.
I then p
On Fri, Feb 28, 2014 at 9:32 PM, Belisko Marek wrote:
> Hi Sebastian,
>
> On Fri, Feb 28, 2014 at 3:05 AM, Sebastian Reichel wrote:
>> On Thu, Feb 27, 2014 at 10:34:35PM +0100, Belisko Marek wrote:
>>> Well I've tried and it's worse :). I got during booting:
>>> [2.218383] ERROR: could not ge
On Fri, Feb 28, 2014 at 01:24:35PM +0200, Georgi Djakov wrote:
> This patch adds implementation for platform specific tuning in order to
> support
> HS200 bus speed mode on Qualcomm SDHCI controller.
>
> Signed-off-by: Asutosh Das
> Signed-off-by: Venkat Gopalakrishnan
> Signed-off-by: Georgi D
From: Florian Vaussard
Add the IOMMU nodes for the DSP and IPU subsystems. The MMU
within the IPU sub-system also supports a bus error back
capability, not available on the DSP MMU.
Signed-off-by: Florian Vaussard
[s-a...@ti.com: IPU bus error back addition]
Signed-off-by: Suman Anna
---
arch
The IOMMU DT nodes have been added for the DSP and IPU
subsystems. The MMUs in OMAP5 are identical to those in
OMAP4, including the bus error back capability on IPU.
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/omap5.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/ar
Hi,
This is an updated series of the OMAP IOMMU DTS nodes
for OMAP3, OMAP4 and OMAP5. The main change is the removal
of the dma-window property from all the IOMMU DT nodes, as
per the discussion on the bindings posted previously [1].
This series goes along with the v3 version of the driver
DT ada
From: Florian Vaussard
Update the IOMMU node for the camera subsystem as per the
OMAP IOMMU bindings.
Signed-off-by: Florian Vaussard
[s-a...@ti.com: corrected interrupt number]
Signed-off-by: Suman Anna
---
arch/arm/boot/dts/omap3.dtsi | 7 ---
1 file changed, 4 insertions(+), 3 deletion
From: Florian Vaussard
Add the DT node for the IOMMU within the DSP subsystem. The entry
is disabled to keep in line with the hwmod usage as intended by
the deprecated CONFIG_OMAP_IOMMU_IVA2 flag.
Signed-off-by: Florian Vaussard
[s-a...@ti.com: split the entry and disable the node]
Signed-off-b
Nit below.
On Fri, Feb 28, 2014 at 01:24:35PM +0200, Georgi Djakov wrote:
> This patch adds implementation for platform specific tuning in order to
> support
> HS200 bus speed mode on Qualcomm SDHCI controller.
>
> Signed-off-by: Asutosh Das
> Signed-off-by: Venkat Gopalakrishnan
> Signed-off-
The OMAP iommu driver performs the reset management for the
iommu instances in processor sub-systems using the omap_device
API which are currently supplied as platform data ops. Use pdata
quirks to maintain the functionality as the OMAP iommu driver
gets converted to use DT nodes, until the reset p
OMAP5 has the same iommus as OMAP4, so extend the OMAP4
iommu pdata quirks for OMAP5 as well.
Signed-off-by: Suman Anna
---
arch/arm/mach-omap2/pdata-quirks.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c
b/arch/arm/mach-omap2/pdata-quirks.c
index 74
The IOMMU DT adaptation support uses the device name instead
of an iommu object name. Fixup the ISP device archdata MMU
name at runtime if using DT-boot. This allows the OMAP3 camera
to be functional in both legacy and DT boots. The iommu object
names should eventually vanish when all the IOMMU use
The IVA MMU is not functional when used through the hwmod and
omap_device layers. Add fixes to clockdomain and hwmod data
to have it functional. The hwmod changes are needed to enable
the clock, and the SWSUP change is needed to wakeup the domain
because the power domain is programmed to be in RET,
From: Laurent Pinchart
The OMAP IOMMU driver locates the IOMMU associated to a device using the
IOMMU name stored in the device archdata iommu field. That field is
expected to be populated by platform code and is left unset for DT-based
devices. This results in a crash when the IOMMU driver attac
A new MMU hwmod class and data structures are created
to represent the MMUs within the IPU and DSP processor
subsystems in OMAP5. The MMUs in OMAP5 are identical to
those in OMAP4.
Signed-off-by: Suman Anna
---
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 83 ++
1 fil
The remoteproc MMUs in OMAP4+ SoCs have some additional debug
registers that can give out the PC value in addition to the
MMU fault address. The PC value can be extracted properly only
on the DSP cores, and is not available on the ARM processors
within the IPU sub-systems. Instead, the MMUs have be
From: Florian Vaussard
CONFIG_OMAP_IOMMU_IVA2 was defined originally to avoid conflicting
usage by tidspbridge and other iommu users. The same can be achieved
by marking the DT node disabled, so remove this obsolete flag and
the corresponding hwmod data can be enabled.
Cc: Paul Walmsley
Signed-
From: Florian Vaussard
As OMAP2+ is moving to a full DT boot for all SoC families, commit
7ce93f3 "ARM: OMAP2+: Fix more missing data for omap3.dtsi file"
adds basic DT bits for OMAP3. But the driver is not yet converted,
so this will not work and driver will not be probed. Convert it!
The legac
From: Florian Vaussard
This patch adds the iommu bindings for all OMAP2+ SoCs. Apart from
the standard bindings used by OMAP peripherals, this patch uses a
'dma-window' (already used by Tegra SMMU) and adds two OMAP custom
bindings - 'ti,#tlb-entries' and 'ti,iommu-bus-err-back'.
Signed-off-by:
From: Florian Vaussard
When booting with a devicetree, no platform data is provided.
Do not prematurely exit iommu_enable() and iommu_disable() in
such a case.
Note: As OMAP do not yet has a proper reset controller driver,
IOMMUs requiring a reset signal should use pdata-quirks as a
transitional
There are couple of issues with the error return paths in
omap_iommu_attach():
1. omap_iommu_attach() returns NULL or ERR_PTR in case of error,
but omap_iommu_attach_dev() only checks for IS_ERR. Thus a NULL
return value (in case driver_find_device fails) will cause the
kernel to panic whe
Hi Joerg, Tony,
This is an updated series of the OMAP IOMMU DT adaptation intended
for 3.15 merge window, addressing the comments from the v2 series.
This series is rebased onto 3.14-rc4, and the only change to bindings
is to drop the dma-window property.
The first 7 patches in the series are in
Use the various devm_ interfaces to simplify the cleanup in
probe and remove functions.
Signed-off-by: Florian Vaussard
Signed-off-by: Suman Anna
Acked-by: Laurent Pinchart
---
drivers/iommu/omap-iommu.c | 52 +-
1 file changed, 10 insertions(+), 42
Paul,
On 02/28/2014 01:58 PM, Paul Walmsley wrote:
On Thu, 13 Feb 2014, Suman Anna wrote:
From: Florian Vaussard
CONFIG_OMAP_IOMMU_IVA2 was defined originally to avoid conflicting
usage by tidspbridge and other iommu users. The same can be achieved
by marking the DT node disabled, so remove
Hi Sebastian,
On Fri, Feb 28, 2014 at 3:05 AM, Sebastian Reichel wrote:
> On Thu, Feb 27, 2014 at 10:34:35PM +0100, Belisko Marek wrote:
>> Well I've tried and it's worse :). I got during booting:
>> [2.218383] ERROR: could not get IIO channel /battery:temp(0)
>> [2.224639] platform batte
On 02/28/2014 10:28 AM, Lucas Stach wrote:
> Those are defined by the common PCI binding.
I have no reason to object to the two Tegra patches, but I'll wait for
Thierry to take a closer look.
I expect once he does, I would apply patch 1/7 through the Tegra tree,
and Bjorn would take patch 2/7 thr
On Fri, Feb 28, 2014 at 9:28 AM, Lucas Stach wrote:
> The glue around the core designware IP is
> significantly different between the Exynos and
> i.MX, which is reflected in the DT bindings.
>
> Note that this patch doesn't change any bindings,
> but just alters the documentation to match reality
On Friday 28 February 2014, Lucas Stach wrote:
> This series cleans up the PCI irq mapping for all
> the ARM PCI host drivers, so they handle it in the
> way defined in the common PCI bindings.
>
> Testing appreciated.
>
> Lucas Stach (7):
> ARM: dts: tegra: add PCIe interrupt mapping propertie
On Friday 28 February 2014, Lucas Stach wrote:
> +Required properties:
> +- compatible: "fsl,imx6q-pcie"
> +- reg: base addresse and length of the pcie controller
> +- interrupts: First entry must contain interrupt handle for controller
> + INTA output.
I think this should be documented as "optio
On Thu, 13 Feb 2014, Suman Anna wrote:
> From: Florian Vaussard
>
> CONFIG_OMAP_IOMMU_IVA2 was defined originally to avoid conflicting
> usage by tidspbridge and other iommu users. The same can be achieved
> by marking the DT node disabled, so remove this obsolete flag and
> the corresponding hw
On 02/28/2014 03:23 AM, Tero Kristo wrote:
> This patch adds support for initializing also omap2-prcm and omap2-scrm
> through DT.
>
> Signed-off-by: Tero Kristo
> ---
> arch/arm/mach-omap2/prm_common.c |2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/prm_common
On 02/28/2014 03:22 AM, Tero Kristo wrote:
[...]
> +static void __init of_omap2_apll_setup(struct device_node *node)
> +{
> + struct dpll_data *ad = NULL;
> + struct clk_hw_omap *clk_hw = NULL;
> + struct clk_init_data *init = NULL;
> + struct clk *clk;
> + const char *parent_na
On Fri, Feb 28, 2014 at 10:37:08AM -0800, Stephen Boyd wrote:
> On 02/28, Josh Cartwright wrote:
> > On Thu, Feb 27, 2014 at 05:55:18PM -0800, Stephen Boyd wrote:
> > > +
> > > +EXAMPLE
> > > +
> > > + keypad {
> > > + compatible = "qcom,pm8921-keypad";
> > > + interrupt-parent = <&
On 02/28, Josh Cartwright wrote:
> On Thu, Feb 27, 2014 at 05:55:18PM -0800, Stephen Boyd wrote:
>
> - linux,wakeup?
> - linux,no-auto-repeat?
Added.
>
> > +
> > +EXAMPLE
> > +
> > + keypad {
> > + compatible = "qcom,pm8921-keypad";
> > + interrupt-parent = <&pmicintc>;
>
* Tero Kristo [140228 10:21]:
>
> Hmm, some clock node is broken, might be missing a name or parent
> name for some reason. Can you try to boot with DEBUG enabled so you
> get pr_debug:s out and see which clock is being initialized during
> the crash?
...
[0.00] ti_dt_clk_init_provider:
On 02/28/2014 08:01 PM, Tony Lindgren wrote:
* Nishanth Menon [140228 08:02]:
On 02/28/2014 03:22 AM, Tero Kristo wrote:
Hi,
This set concludes the omap2+ clock DT conversion work by creating the
DT clock data for omap2 SoC also.
I am also currently doing related work to cleanup CM/PRM codeb
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. To allow keystone SoC reset if
watchdog is triggered we have to enable it in reset mux configuration
register regarding of watchdog configuration. Also we need to set
soft/hard reset we are going to u
This node is intended to allow SoC reset in case of software reset
or appropriate watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be configured to cause reset or not.
Additi
The reset controller registers are part of the PLL Controller MMRs.
According to TRM there are the following registers:
RSTYPE, RSCTRL, RSCFG and RSISO. Currently declared only one of them,
but that is not enough to correctly setup reset properties, so add
whole range of pll registers - pllregs.
A
These patches introduce keystone reset driver.
The keystone SoC can be rebooted in several ways. By external reset
pin, by soft and by watchdogs. This driver allows software reset or reset
by one of the watchdogs. Also added opportunity to set soft/hard reset type.
Based on v3.14-rc4
CC: Dmitry
Enable reset driver support in order to have opportunity
to reboot SoC by watchdog and by software.
Signed-off-by: Ivan Khoronzhuk
---
CC: Russell King
CC: Santosh Shilimkar
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_d
Remove reset stuff in flavour of using keystone reset driver:
driver/power/reset/keystone-reset.c
Signed-off-by: Ivan Khoronzhuk
---
CC: Santosh Shilimkar
CC: Russell King
arch/arm/mach-keystone/keystone.c | 35 ---
1 file changed, 35 deletions(-)
diff --git
* Nishanth Menon [140228 08:02]:
> On 02/28/2014 03:22 AM, Tero Kristo wrote:
> > Hi,
> >
> > This set concludes the omap2+ clock DT conversion work by creating the
> > DT clock data for omap2 SoC also.
> >
> > I am also currently doing related work to cleanup CM/PRM codebase in
> > preparation
On Fri, 2014-02-28 at 17:37 +0100, Maxime Ripard wrote:
> The Allwinner A31 has a 16 channels DMA controller that it shares with the
> newer A23. Although sharing some similarities with the DMA controller of the
> older Allwinner SoCs, it's significantly different, I don't expect it to be
> possibl
As defined by the common PCI bindings.
Signed-off-by: Lucas Stach
---
arch/arm/boot/dts/imx6qdl.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fb28b2ecb1db..db3339e7d3a2 100644
--- a/arch/arm/boot/dts/im
So it actually works.
Signed-off-by: Lucas Stach
---
arch/arm/boot/dts/exynos5440.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 02a0a1226cef..65d425d9ec27 100644
--- a/arch/arm/boot/dts/ex
Those are defined by the common PCI binding.
Signed-off-by: Lucas Stach
---
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 8
arch/arm/boot/dts/tegra20.dtsi| 4
arch/arm/boot/dts/tegra30.dtsi| 4
This is the recommended method of doing the IRQ
mapping. For old devicetrees we fall back to the
previous practice.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pcie-designware.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/d
This series cleans up the PCI irq mapping for all
the ARM PCI host drivers, so they handle it in the
way defined in the common PCI bindings.
Testing appreciated.
Lucas Stach (7):
ARM: dts: tegra: add PCIe interrupt mapping properties
PCI: tegra: use new OF interrupt mapping when possible
PC
This is the recommended method of doing the IRQ
mapping. Still fall back to the old method in order
to not break the just submitted board files.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-rcar-gen2.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/
This is the recommended method of doing the IRQ
mapping. For old devicetrees we fall back to the
previous practice.
Signed-off-by: Lucas Stach
---
drivers/pci/host/pci-tegra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/hos
The glue around the core designware IP is
significantly different between the Exynos and
i.MX, which is reflected in the DT bindings.
Note that this patch doesn't change any bindings,
but just alters the documentation to match reality
of deployed DTs and kernels.
Signed-off-by: Lucas Stach
---
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