Hi Peter,
On Sat, Apr 5, 2014 at 4:44 AM, Peter Crosthwaite
wrote:
> On Sat, Apr 5, 2014 at 12:30 AM, Harini Katakam
> wrote:
>> Hi,
>>
>> On Fri, Apr 4, 2014 at 7:38 PM, Harini Katakam
>> wrote:
>>> Hi Mark,
>>>
>>> On Fri, Apr 4, 2014 at 6:16 PM, Mark Brown wrote:
On Fri, Apr 04, 2014 a
This patch adds the Device Tree bindings for the Hisilicon hip04
Ethernet controller, including 100M / 1000M controller.
Signed-off-by: Zhangfei Gao
---
.../bindings/net/hisilicon-hip04-net.txt | 88
1 file changed, 88 insertions(+)
create mode 100644
Documenta
Hisilicon hip04 platform mdio driver
Reuse Marvell phy drivers/net/phy/marvell.c
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/Kconfig|1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/hisilicon/Kconfig | 31 +
drivers/net/ether
Support Hisilicon hip04 ethernet driver, including 100M / 1000M controller
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/hisilicon/Makefile|2 +-
drivers/net/ethernet/hisilicon/hip04_eth.c | 777
2 files changed, 778 insertions(+), 1 deletion(-)
crea
v7:
Remove select NET_CORE in 0002
v6:
Suggest by Russell: Use netdev_sent_queue & netdev_completed_queue to solve
latency issue
Also shorten the period of timer, which is used to wakeup the queue since no
tx completed interrupt.
v5:
no big change, fix typo
v4:
Modify accoringly to the suggeti
Add binding documentation for the Cadence UART.
Signed-off-by: Soren Brinkmann
Acked-by: Peter Crosthwaite
Acked-by: Rob Herring
Tested-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/serial/cdns,uart.txt | 20
1 file changed
From: Michal Simek
Register port numbers according to order in DT aliases.
If aliases are not defined, order in DT is used.
If aliases are defined, register port id based
on that.
This patch ensures proper ttyPS0/1 assignment.
[soren]: Combined integer declarations in probe(), removed warning me
This is all white space and comment clean up. Mostly reformatting
comments.
Signed-off-by: Soren Brinkmann
Tested-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/tty/serial/xilinx_uartps.c | 210 +
1 file changed, 74 insertions(+), 136
A lot of read-modify-write sequences used a one-line statement which
nests a readl() within a writel(). Convert this into code sequences that
make the three steps more obvious.
Signed-off-by: Soren Brinkmann
Tested-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/tty/seria
Print a warning if the clock notifier rejects a clock frequency change
to facilitate debugging (see:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/304329/focus=304379)
Signed-off-by: Soren Brinkmann
Tested-by: Michal Simek
---
Changes in v3: None
Changes in v2: None
drivers/tty/serial/
A comment states, that, according to the data sheet, to enable
interrupts the disable register should be written, but the enable
register could be left untouched. And it suspsects a HW bug requiring
to write both.
Reviewing the data sheet, these statements seem wrong. Just as one would
expect. Writ
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann
Acked-by: Peter Crosthwaite
Acked-by: Rob Herring
Tested-by: Michal Simek
---
This change depends on 'tty: xuartps: Rebrand driver
From: Michal Simek
No functional changes.
Signed-off-by: Michal Simek
---
Changes in v3: None
Changes in v2:
- this patch has been added
---
drivers/tty/serial/xilinx_uartps.c | 109 +
1 file changed, 49 insertions(+), 60 deletions(-)
diff --git a/driver
On Fri, Mar 14, 2014 at 03:34:27PM +, Liviu Dudau wrote:
> Some architectures do not share x86 simple view of the PCI I/O space
> and instead use a range of addresses that map to bus addresses. For
> some architectures these ranges will be expressed by OF bindings
> in a device tree file.
It's
On Fri, Mar 14, 2014 at 03:34:30PM +, Liviu Dudau wrote:
> Make it easier to discover the domain number of a bus by storing
> the number in pci_host_bridge for the root bus. Several architectures
> have their own way of storing this information, so it makes sense
> to try to unify the code.
I
Add the USB EHCI clock to the R8A7791 device tree.
Signed-off-by: Sergei Shtylyov
---
The patch is against 'renesas-devel-3.14-20140403' tag of Simon Horman's
'renesas.git' repo.
arch/arm/boot/dts/r8a7791.dtsi| 25 +++--
include/dt-bindings/clock/r8a7791-clock
On Fri, Mar 14, 2014 at 03:34:31PM +, Liviu Dudau wrote:
> This is a useful function and we should make it visible outside the
> generic PCI code. Export it as a GPL symbol.
>
> Signed-off-by: Liviu Dudau
> Tested-by: Tanmay Inamdar
> ---
> drivers/pci/host-bridge.c | 3 ++-
> 1 file change
Convert all Zynq DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.
Inspired-by: Steffen Trumtrar
(http://www.spinics.net/lists/arm-kernel/msg319832.html)
Signed-off-by: Soren Brinkmann
---
Changes in v2: Non
Specify the 'clock-latency' property to avoid certain cpufreq governors
from refusing to work with the following error:
ondemand governor failed, too long transition latency of HW, fallback to
performance governor
Reported-by: Mike Looijmans
Signed-off-by: Soren Brinkmann
Tested-by: Mike Looi
Add header file with symbolic names for Zynq's clocks.
Signed-off-by: Soren Brinkmann
---
Changes in v2:
- this patch has been added
---
include/dt-bindings/clock/zynq-7000.h | 64 +++
1 file changed, 64 insertions(+)
create mode 100644 include/dt-bindings/clo
Use symbolic names instead of bare numbers to specify clocks.
Signed-off-by: Soren Brinkmann
---
Changes in v2:
- this patch has been added
---
arch/arm/boot/dts/zynq-7000.dtsi | 33 +
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boo
On Sat, Apr 5, 2014 at 12:30 AM, Harini Katakam
wrote:
> Hi,
>
> On Fri, Apr 4, 2014 at 7:38 PM, Harini Katakam
> wrote:
>> Hi Mark,
>>
>> On Fri, Apr 4, 2014 at 6:16 PM, Mark Brown wrote:
>>> On Fri, Apr 04, 2014 at 05:44:23PM +0530, Harini Katakam wrote:
On Fri, Apr 4, 2014 at 3:39 PM, Ma
Use #defines from the common include file to describe
interrupt specifiers.
Signed-off-by: Soren Brinkmann
---
Changes in v2: None
arch/arm/boot/dts/zynq-7000.dtsi | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi
Hi,
here's the complete series now. One fix for cpufreq from our vendor tree
and migration to pre-processor syntax.
Thanks,
Sören
Changes in v2:
- Send full series (added patches 1, 4, 5)
Soren Brinkmann (5):
ARM: zynq: DT: Add 'clock-latency' property
ARM: zynq: dt: Conver
On Thu, Apr 3, 2014 at 9:10 PM, Harini Katakam wrote:
> Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
>
> Signed-off-by: Harini Katakam
> ---
>
> v2 changes:
> - Use xilinx compatible string too.
> - Changes read register and write register functions to static inline.
> - Re
Sorry this accidentally went out too early. I meant to include patches
to convert the clocks as well. I'll send a v2 to include those patches.
Sören
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Use #defines from the common include file to describe
interrupt specifiers.
Signed-off-by: Soren Brinkmann
---
---
arch/arm/boot/dts/zynq-7000.dtsi | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/
Convert all Zynq DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.
Inspired-by: Steffen Trumtrar
(http://www.spinics.net/lists/arm-kernel/msg319832.html)
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts
Add device tree binding documentation for the Cadence I2C controller.
Signed-off-by: Soren Brinkmann
---
Changes in v5:
- Document all properties
- list clock-names as optional property (driver doesn't use it, though)
- use lower case hex digits in 'reg' property
- reword description of 'clo
Add a driver for the Cadence I2C controller. This controller is for
example found in Xilinx Zynq.
Signed-off-by: Soren Brinkmann
Tested-by: Michal Simek
Reviewed-by: Harini Katakam
---
Changes in v5:
- change default speed to 100 kHz
- report NACK errors with -ENXIO error code
Changes in v4
Signed-off-by: Soren Brinkmann
Tested-by: Michal Simek
---
Changes in v5:
- use lower case hex digits in 'reg' property
Changes in v4: None
Changes in v3: None
Changes in v2:
- replace 'pmbus' with 'ti' in compatibility strings of UCD devices
---
arch/arm/boot/dts/zynq-7000.dtsi | 22 ++
On Fri, 2014-04-04 at 09:17PM +0200, Gerhard Sittig wrote:
> On Thu, 2014-04-03 at 10:59 -0700, Soren Brinkmann wrote:
> >
> > Add device tree binding documentation for the Cadence I2C controller.
> >
> > [ ... ]
> >
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/i2c/i2c-cadence.t
On Fri, 2014-04-04 at 08:17PM +0100, Russell King - ARM Linux wrote:
> On Fri, Apr 04, 2014 at 09:53:29AM -0700, Sören Brinkmann wrote:
> > On Fri, 2014-03-28 at 03:51PM +, Russell King - ARM Linux wrote:
> > > On Fri, Mar 28, 2014 at 10:42:54AM -0500, Rob Herring wrote:
> > > > On Fri, Mar 28,
On 03/28/2014 04:12 PM, Alex Elder wrote:
> This series proposes creating a single implementation of the "pen
> release" (or spin-table) mechanism for starting secondary CPUs on
> ARM SMP systems. This mechanism is currently implemented at least 5
> times in the kernel, each essentially identical
This patchset adds support for the Krait L1/L2 cache error detection
hardware. The second patch adds the Krait L2 indirection
register code. This patch is in need of an ACK from ARM folks.
The next two patches add the driver and the binding and
the final patch fixes up the DT nodes to match the bi
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi
Cc: Mark Rutland
Cc: Kumar Gala
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/cache.txt | 48 -
1
On 04/04/2014 12:55 PM, Stephen Boyd wrote:
> On 04/03/14 19:18, Alex Elder wrote:
>> +
>> +/*
>> + * Secondary startup method setup routine to extract the location of
>> + * the secondary boot register from a "cpu" or "cpus" device tree
>> + * node. Only the first seen secondary boot register val
On Fri, Apr 04, 2014 at 09:53:29AM -0700, Sören Brinkmann wrote:
> On Fri, 2014-03-28 at 03:51PM +, Russell King - ARM Linux wrote:
> > On Fri, Mar 28, 2014 at 10:42:54AM -0500, Rob Herring wrote:
> > > On Fri, Mar 28, 2014 at 10:20 AM, Russell King
> > > wrote:
> > > > Always enable the L2C l
On Thu, 2014-04-03 at 10:59 -0700, Soren Brinkmann wrote:
>
> Add device tree binding documentation for the Cadence I2C controller.
>
> [ ... ]
>
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/i2c-cadence.txt
> @@ -0,0 +1,21 @@
> +Binding for the Cadence I2C controller
> +
> +Requ
Document the GDSC nodes present within the multimedia clock
controller.
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/clock/qcom,mmcc.txt| 42 ++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
b/Doc
On 04/04/2014 10:30 AM, Tim Kryger wrote:
> On Thu, Apr 3, 2014 at 7:18 PM, Alex Elder wrote:
>
>> diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
>> new file mode 100644
>> index 000..46a64f2
>> --- /dev/null
>> +++ b/arch/arm/mach-bcm/platsmp.c
>
>> +/* Size of mappe
On 04/04/14 09:32, Kumar Gala wrote:
> * Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs
> * Fix incorrect offset for PMIC_SSBI2_RESET
> * Fix typo:
> SIC_TIC -> SPS_TIC_H
> SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK
> * Fix naming convention:
> SFAB_CFPB_S_HCLK -> SFAB_CFPB
On 04/04/14 09:31, Kumar Gala wrote:
> The APQ8064 and MSM8960 share a significant amount of clock data and
> code between the two SoCs. Rather than duplicating the data we just add
> support for a unqiue APQ8064 clock table into the MSM8960 code.
>
> For now add just enough clocks to get a basic
On 04/04/14 09:29, Kumar Gala wrote:
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> new file mode 100644
> index 000..31f735c
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -0,0 +1,122 @@
> +/dts-v1/;
> +
> +/include/ "skeleton.dt
On 04/04/14 09:30, Kumar Gala wrote:
> Add a driver for the global clock controller found on IPQ8064 based
> platforms. This should allow most non-multimedia device drivers to probe
> and control their clocks.
>
> This is currently missing clocks for SATA, USB, audio and networking
> devices.
>
Th
On 04/03/14 19:18, Alex Elder wrote:
> +
> +/*
> + * Secondary startup method setup routine to extract the location of
> + * the secondary boot register from a "cpu" or "cpus" device tree
> + * node. Only the first seen secondary boot register value is used;
> + * any others are ignored. The seco
When you make a new postings of a patch, you must resend the entire
series, not just the patch which is being updated.
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Hello.
On 04/04/2014 09:09 PM, Bjorn Helgaas wrote:
Add OF match table for pci-rcar-gen2 driver for device tree support.
Signed-off-by: Ben Dooks
I'm not sure what the status of this is. I saw comments about a missing
#include, but I didn't see a fixed repost.
Since there was none.
On 04/04/14 18:09, Bjorn Helgaas wrote:
On Thu, Mar 06, 2014 at 06:01:19PM +, Ben Dooks wrote:
Add OF match table for pci-rcar-gen2 driver for device tree support.
Signed-off-by: Ben Dooks
I'm not sure what the status of this is. I saw comments about a missing
#include, but I didn't see
On Thu, Mar 06, 2014 at 06:01:19PM +, Ben Dooks wrote:
> Add OF match table for pci-rcar-gen2 driver for device tree support.
>
> Signed-off-by: Ben Dooks
I'm not sure what the status of this is. I saw comments about a missing
#include, but I didn't see a fixed repost. Ben, could you pleas
On Fri, Apr 04, 2014 at 11:03:41AM -0600, Bjorn Helgaas wrote:
> On Wed, Mar 05, 2014 at 11:42:19AM -0700, Jason Gunthorpe wrote:
> > On Wed, Mar 05, 2014 at 02:25:51PM +0100, Lucas Stach wrote:
> > > - return pp->irq;
> > > + irq = of_irq_parse_and_map_pci(dev, slot, pin);
> > > + if (!irq)
> > >
On Wed, Mar 05, 2014 at 11:42:19AM -0700, Jason Gunthorpe wrote:
> On Wed, Mar 05, 2014 at 02:25:51PM +0100, Lucas Stach wrote:
> > - return pp->irq;
> > + irq = of_irq_parse_and_map_pci(dev, slot, pin);
> > + if (!irq)
> > + irq = pp->irq;
>
> In light of the two bugs that Tim fou
On Wed, Mar 05, 2014 at 02:25:48PM +0100, Lucas Stach wrote:
> This is the recommended method of doing the IRQ
> mapping. Still fall back to the old method in order
> to not break the just submitted board files.
Hi Lucas, can you rebase this to Linus' current tree? This doesn't apply
anymore beca
On Wed, Mar 05, 2014 at 02:25:47PM +0100, Lucas Stach wrote:
> This is the recommended method of doing the IRQ
> mapping. For old devicetrees we fall back to the
> previous practice.
>
> Signed-off-by: Lucas Stach
> Acked-by: Arnd Bergmann
Applied with Stephen's Tested-by to my pending/host-teg
On Fri, 2014-03-28 at 03:51PM +, Russell King - ARM Linux wrote:
> On Fri, Mar 28, 2014 at 10:42:54AM -0500, Rob Herring wrote:
> > On Fri, Mar 28, 2014 at 10:20 AM, Russell King
> > wrote:
> > > Always enable the L2C low power modes on L2C-310 R3P0 and newer parts.
> >
> > I assume you want
Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: Steffen Trumtrar
---
arch/arm/boot/dts/socfpga.dtsi | 8 ++-
include/dt-bindings/reset/altr,rst-mgr.h | 90
2 files
Add basic APQ8064 SoC include device tree and support for basic booting on
the IFC6410 board.
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 12 +++
arch/arm/boot/dts/qcom-apq8064.dtsi| 151 +
* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs
* Fix incorrect offset for PMIC_SSBI2_RESET
* Fix typo:
SIC_TIC -> SPS_TIC_H
SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK
* Fix naming convention:
SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK
SATA_SRC_CLK -> SATA_CLK_SRC
On Fri, 2014-04-04 at 04:38PM +0200, Wolfram Sang wrote:
> On Thu, Apr 03, 2014 at 10:59:26AM -0700, Soren Brinkmann wrote:
> > Add a driver for the Cadence I2C controller. This controller is for
> > example found in Xilinx Zynq.
> >
> > Signed-off-by: Soren Brinkmann
> > Tested-by: Michal Simek
Add a reset-controller driver for the socfpga platform.
The reset-controller has four banks with up to 32 entries all encapsulated in
one module block.
Signed-off-by: Steffen Trumtrar
---
drivers/reset/Makefile| 1 +
drivers/reset/reset-socfpga.c | 149 +
The APQ8064 and MSM8960 share a significant amount of clock data and
code between the two SoCs. Rather than duplicating the data we just add
support for a unqiue APQ8064 clock table into the MSM8960 code.
For now add just enough clocks to get a basic serial port going on an
APQ8064 device.
Signe
To be able to use the reset-controller framework, the property
#reset-cells
is mandatory.
Signed-off-by: Steffen Trumtrar
---
Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera/
Hi!
This series converts the current rst-mgr entry in the socfpga.dtsi to
a driver that registers with the reset-controller framework.
1/3 adds the driver,
2/3 updates the binding to reflect this
3/3 updates the socfpga.dtsi and adds the DT-header file
Regards,
Steffen
Steffen Trumtrar (3):
r
Add basic IPQ8064 SoC include device tree and support for basic booting on
the AP148 Reference board. Also, keep dtb build list and qcom_dt_match in
sorted order.
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/Makefile | 8 +-
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 12 +++
Hi Josh,
Thanks for the comments!
On 04/03/2014 09:19 PM, Josh Cartwright wrote:
> Hey Stanimir-
>
> Just a few comments/questions from a quick scan of your patchset:
>
> On Thu, Apr 03, 2014 at 07:17:58PM +0300, Stanimir Varbanov wrote:
> [..]
>> +++ b/drivers/crypto/qce/core.c
> [..]
>> +
>>
Hisilicon hip04 platform mdio driver
Reuse Marvell phy drivers/net/phy/marvell.c
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/Kconfig|1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/hisilicon/Kconfig | 31 +
drivers/net/ether
Hisilicon hip04 platform mdio driver
Reuse Marvell phy drivers/net/phy/marvell.c
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/Kconfig|1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/hisilicon/Kconfig | 31 +
drivers/net/ether
From: zhangfei
Date: Fri, 04 Apr 2014 23:40:24 +0800
> Thanks Daivd, could I update following this thread first.
You will need to address my feedback, as well as that which anyone
else reviewing this series gives to you.
It is not acceptable, ever, to "just fix it later". You must fix
all issu
On 04/04/2014 11:30 PM, David Miller wrote:
From: Zhangfei Gao
Date: Fri, 4 Apr 2014 23:16:36 +0800
+config HIP04_ETH
+ tristate "HISILICON P04 Ethernet support"
+ select NET_CORE
+ select PHYLIB
+ select MARVELL_PHY
+ select MFD_SYSCON
+ ---help---
+
On Thu, Apr 3, 2014 at 7:18 PM, Alex Elder wrote:
> diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
> new file mode 100644
> index 000..46a64f2
> --- /dev/null
> +++ b/arch/arm/mach-bcm/platsmp.c
> +/* Size of mapped Cortex A9 SCU address space */
> +#define SCU_SIZE
From: Zhangfei Gao
Date: Fri, 4 Apr 2014 23:16:36 +0800
> +config HIP04_ETH
> + tristate "HISILICON P04 Ethernet support"
> + select NET_CORE
> + select PHYLIB
> + select MARVELL_PHY
> + select MFD_SYSCON
> + ---help---
> + If you wish to compile a kernel for a hard
Hisilicon hip04 platform mdio driver
Reuse Marvell phy drivers/net/phy/marvell.c
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/Kconfig|1 +
drivers/net/ethernet/Makefile |1 +
drivers/net/ethernet/hisilicon/Kconfig | 32 +
drivers/net/ether
Support Hisilicon hip04 ethernet driver, including 100M / 1000M controller
Signed-off-by: Zhangfei Gao
---
drivers/net/ethernet/hisilicon/Makefile|2 +-
drivers/net/ethernet/hisilicon/hip04_eth.c | 777
2 files changed, 778 insertions(+), 1 deletion(-)
crea
v6:
Suggest by Russell: Use netdev_sent_queue & netdev_completed_queue to solve
latency issue
Also shorten the period of timer, which is used to wakeup the queue since no
tx completed interrupt.
v5:
no big change, fix typo
v4:
Modify accoringly to the suggetion from Arnd, Florian, Eric, David
U
This patch adds the Device Tree bindings for the Hisilicon hip04
Ethernet controller, including 100M / 1000M controller.
Signed-off-by: Zhangfei Gao
---
.../bindings/net/hisilicon-hip04-net.txt | 88
1 file changed, 88 insertions(+)
create mode 100644
Documenta
This patch adds support for propagation of setup of clock's parent one level
up.
This feature is helpful when a driver changes topology of its clocks using
clk_set_parent(). The problem occurs when on one platform/SoC driver's clock
is located at MUX output but on the other platform/SoC there is
2014-04-04 22:10 GMT+08:00 Russell King - ARM Linux :
> On Fri, Apr 04, 2014 at 09:40:31PM +0800, Barry Song wrote:
>> 2014-03-28 23:19 GMT+08:00 Russell King :
>> > Signed-off-by: Russell King
>> > ---
>> > arch/arm/boot/dts/marco.dtsi | 2 +-
>> > arch/arm/boot/dts/prima2.dtsi | 2 +-
>> > a
This reverts commit 59956d35a8618235ea715280b49447bb36f2c975.
Signed-off-by: Tomasz Stanislawski
---
drivers/gpu/drm/exynos/exynos_hdmi.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hd
This patch enables clk_set_parent() propagation for clocks used
by s5p-tv and exynos-drm drivers.
Signed-off-by: Tomasz Stanislawski
---
drivers/clk/samsung/clk-exynos4.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk
Export sclk_hdmiphy clock to be usable from DT.
Signed-off-by: Tomasz Stanislawski
---
drivers/clk/samsung/clk-exynos4.c |2 +-
include/dt-bindings/clock/exynos4.h |1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsu
This patchset adds some updates to clocks for Exynos4 platform and to the clock
core. The patches are rebased on linux/next.
An interesting part might be 'propagation of clk_set_parent()'. This feature
simplifies configuration of complex topologyof clocks by drivers. Such a
situation happens fo
These new properties more accurately reflect the real connections of the
boards and therefore make it easier to match them up with schematics.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra20-harmony.dts | 10 +-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 7 +++
arch/arm
These power supply properties are no longer needed since the binding now
contains the full set properties to accurately describe the power supply
inputs of the Tegra PCIe block.
Signed-off-by: Thierry Reding
---
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | 5 -
1 file chan
The current usage of regulators for the Tegra PCIe block is wrong. It
doesn't accurately reflect the actual supply inputs of the IP block and
therefore isn't as flexible as it should be. Rectify this by describing
all possible supply inputs in the device tree binding documentation and
deprecate the
The current device tree binding for the regulator setup on Tegra PCIe is
not accurate. While it does work for current use-cases, that's likely by
accident rather than design. This series replaces the existing set of
power-supply properties with a new set that accurately describes the
inputs of the
These properties are deprecated and no longer of any use.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra20-harmony.dts | 4
arch/arm/boot/dts/tegra20-tamonten.dtsi | 4
arch/arm/boot/dts/tegra20-trimslice.dts | 4
arch/arm/boot/dts/tegra30-beaver.dts| 5 -
arc
Hi Mark,
On Fri, Apr 4, 2014 at 8:12 PM, Mark Brown wrote:
> On Fri, Apr 04, 2014 at 07:38:14PM +0530, Harini Katakam wrote:
>
>> OK. I understand.
>> Can you comment on the case where a decoder is used?
>
>> There is support for adding a decoder where extended slaves can be selected
>> through t
On Fri, Apr 04, 2014 at 07:38:14PM +0530, Harini Katakam wrote:
> OK. I understand.
> Can you comment on the case where a decoder is used?
> There is support for adding a decoder where extended slaves can be selected
> through the IP's control register.
> (This is not currently implemented in the
On Thu, Apr 03, 2014 at 10:59:26AM -0700, Soren Brinkmann wrote:
> Add a driver for the Cadence I2C controller. This controller is for
> example found in Xilinx Zynq.
>
> Signed-off-by: Soren Brinkmann
> Tested-by: Michal Simek
> Reviewed-by: Harini Katakam
Only minor stuff, but since you rese
Hi,
On Fri, Apr 4, 2014 at 7:38 PM, Harini Katakam
wrote:
> Hi Mark,
>
> On Fri, Apr 4, 2014 at 6:16 PM, Mark Brown wrote:
>> On Fri, Apr 04, 2014 at 05:44:23PM +0530, Harini Katakam wrote:
>>> On Fri, Apr 4, 2014 at 3:39 PM, Mark Brown wrote:
>>> > On Fri, Apr 04, 2014 at 08:30:38AM +0530, Har
On Fri, 4 Apr 2014 08:30:42 +, "li.xi...@freescale.com"
wrote:
> > Subject: RE: [PATCH] of: fix of_update_property [v2]
> >
> > On Wed, 2 Apr 2014 05:29:53 +, "li.xi...@freescale.com"
> > wrote:
> > >
> > >
> > > > > @@ -1776,25 +1776,26 @@ int of_update_property(struct device_node *np,
On Fri, Apr 04, 2014 at 09:40:31PM +0800, Barry Song wrote:
> 2014-03-28 23:19 GMT+08:00 Russell King :
> > Signed-off-by: Russell King
> > ---
> > arch/arm/boot/dts/marco.dtsi | 2 +-
> > arch/arm/boot/dts/prima2.dtsi | 2 +-
> > arch/arm/mach-prima2/l2x0.c | 34 +---
On Apr 04, Alexey Brodkin wrote:
> Signed-off-by: Alexey Brodkin
>
Maybe it would be nice adding some driver description here, so the commit
log actually says something useful about the commit.
[..]
> Reviewed-by: Ezequiel Garcia
>
> +/**
> + * axs_flag_wait_and_reset - Waits until requested
Hi Mark,
On Fri, Apr 4, 2014 at 6:16 PM, Mark Brown wrote:
> On Fri, Apr 04, 2014 at 05:44:23PM +0530, Harini Katakam wrote:
>> On Fri, Apr 4, 2014 at 3:39 PM, Mark Brown wrote:
>> > On Fri, Apr 04, 2014 at 08:30:38AM +0530, Harini Katakam wrote:
>
>> >> This IP can drive 4 slaves.
>> >> The CS
2014-03-28 23:19 GMT+08:00 Russell King :
> Signed-off-by: Russell King
> ---
> arch/arm/boot/dts/marco.dtsi | 2 +-
> arch/arm/boot/dts/prima2.dtsi | 2 +-
> arch/arm/mach-prima2/l2x0.c | 34 +-
> 3 files changed, 3 insertions(+), 35 deletions(-)
>
> diff --g
On Fri, Apr 04, 2014 at 05:44:23PM +0530, Harini Katakam wrote:
> On Fri, Apr 4, 2014 at 3:39 PM, Mark Brown wrote:
> > On Fri, Apr 04, 2014 at 08:30:38AM +0530, Harini Katakam wrote:
> >> This IP can drive 4 slaves.
> >> The CS line to be driven is selected in spi device structure and
> >> that
Introduce support for dynamic device tree resolution.
Using it, it is possible to prepare a device tree that's
been loaded on runtime to be modified and inserted at the kernel
live tree.
Export of of_resolve by Guenter Roeck
Signed-off-by: Pantelis Antoniou
---
.../devicetree/dynamic-resolutio
From: Pantelis Antoniou
Dynamically inserting i2c client device nodes requires the use
of a single device registration method. Rework and export it.
Signed-off-by: Pantelis Antoniou
---
drivers/i2c/i2c-core.c | 99 +++---
include/linux/i2c.h| 10
Add the bus handler registration needed for performing overlays
containing platform devices.
Signed-off-by: Pantelis Antoniou
---
drivers/base/platform.c | 98 +++--
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/base/platform.c
This patch adds overlay tests to the OF selftest.
It tests overlay device addition/removal and whether
the apply revert sequence is correct.
Signed-off-by: Pantelis Antoniou
---
drivers/of/selftest.c | 368
drivers/of/testcase-data/testcases.dt
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