On 04/05/2014 02:23 AM, Soren Brinkmann wrote:
> The Zynq UART is Cadence IP and the driver has been renamed accordingly.
> Migrate the DT to use the new binding for the UART driver.
>
> Signed-off-by: Soren Brinkmann
> Acked-by: Peter Crosthwaite
> Acked-by: Rob Herring
> Tested-by: Michal Sim
On 04/05/2014 02:23 AM, Soren Brinkmann wrote:
> Add binding documentation for the Cadence UART.
>
> Signed-off-by: Soren Brinkmann
> Acked-by: Peter Crosthwaite
> Acked-by: Rob Herring
> Tested-by: Michal Simek
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings
Hi,
On Tue, Apr 22, 2014 at 8:19 PM, Felipe Balbi wrote:
> Hi,
>
> On Tue, Apr 22, 2014 at 12:58:41PM +0530, sundeep subbaraya wrote:
>> Hi,
>>
>> On Mon, Apr 21, 2014 at 10:09 PM, Alan Stern
>> wrote:
>> > On Mon, 21 Apr 2014, Felipe Balbi wrote:
>> >
>> >> Hi,
>> >>
>> >> On Fri, Apr 18, 2014
Hi again Andrzej,
On 04/23/2014 10:01 AM, YoungJun Cho wrote:
Hi Andrzej
Thank you for comments.
On 04/22/2014 09:15 PM, Andrzej Hajda wrote:
Hi YoungJun,
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
Some phy control registers are not kept after software reset.
So this patch makes the clocks
On Tue, Apr 22, 2014 at 06:25:25PM -0700, Frank Rowand wrote:
> Create some infrastructure to aid trouble shooting device tree related
> boot issues.
>
> Add a %driver_name file to each device tree node sysfs directory which has had
> a driver bound to it. This allows detecting device tree nodes
On 23 April 2014 00:03, Mark Brown wrote:
> On Tue, Apr 22, 2014 at 07:17:54PM +0530, Tushar Behera wrote:
>> On 22 April 2014 16:14, Mark Brown wrote:
>
>> > In general this isn't up to modern standards, please do try to check
>> > that new code is following best practices. Did the support for
Hi Antoine
On Tue, 22 Apr 2014 08:38:24 -0700
Antoine Ténart wrote:
> The BG2 has an AHCI SATA controller. Add the corresponding node
> in its device tree.
The AHCI IP of BG2 is different with BG2Q, so the driver in the series of patch
doesn't work on BG2.
Thanks
--
To unsubscribe from this li
Hi Antoine,
On Tue, 22 Apr 2014 08:38:25 -0700
Antoine Ténart wrote:
> The BG2CD has an AHCI SATA controller. Add the corresponding node
> in its device tree.
BG2CD doesn't has AHCI controller.
Thanks
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a me
On Wed, Apr 23, 2014 at 12:02 AM, Linus Walleij
wrote:
> On Tue, Apr 15, 2014 at 8:41 AM, Chen-Yu Tsai wrote:
>
>> This patch provides of_get_gpiod_flags_by_name(), which looks up GPIO
>> phandles by name only, through gpios/gpio-names, and not by index.
>>
>> Signed-off-by: Chen-Yu Tsai
>
> Lik
On Tue, Apr 15, 2014 at 05:56:12PM +0200, Laurent Pinchart wrote:
> Hi Geert,
>
> Thank you for the patch.
>
> On Monday 14 April 2014 19:00:40 Geert Uytterhoeven wrote:
> > From: Geert Uytterhoeven
> >
> > Improve the wording for the clock-indices binding documentation.
> > Also replace "empty
From: Rob Herring
The ralink FDT code can be simplified by using
unflatten_and_copy_device_tree function. This removes all accesses to
FDT header data by the arch code.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
v2: no change
arch/mips/ralink/of.c | 25 +---
From: Rob Herring
The existing code is buggy because built-in DTBs are in init memory.
It is also broken because the reserved bootmem was then freed after
unflattening, but the unflattened tree points to data in the flat tree.
Fix this by using the unflatten_and_copy_device_tree function.
This r
From: Rob Herring
The octeon FDT code can be simplified by using
unflatten_and_copy_device_tree function. This removes all accesses to
FDT header data by the arch code.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
v2: fix build error
arch/mips/cavium-octeon/s
From: Rob Herring
The existing code is buggy because built-in DTBs are in init memory.
Fix this by using the unflatten_and_copy_device_tree function.
This removes all accesses to FDT header data by the arch code.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
Cc: linux-m...@linux-mips.org
---
v2
From: Rob Herring
Now that ARM is using memblock instead of bootmem, the default version
of early_init_dt_alloc_memory_arch can be used.
Signed-off-by: Rob Herring
Cc: Russell King
Cc: linux-arm-ker...@lists.infradead.org
---
v2: no change
arch/arm/kernel/devtree.c | 5 -
1 file changed,
Create some infrastructure to aid trouble shooting device tree related
boot issues.
Add a %driver_name file to each device tree node sysfs directory which has had
a driver bound to it. This allows detecting device tree nodes which failed
to be bound to any driver.
Examples of using the %driver_n
From: Rob Herring
The architecture code does not need to access the internals of the FDT
blob, so make the pointer to it void *.
Signed-off-by: Rob Herring
Cc: Mark Salter
Cc: Aurelien Jacquiot
Cc: linux-c6x-...@linux-c6x.org
---
v2: remove unneeded casting
arch/c6x/kernel/setup.c | 4 ++--
Hi Andrzej
Thank you for comment.
On 04/22/2014 11:02 PM, Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by Sa
From: Rob Herring
Whatever needed powerpc machdep.h appears to have been removed, so the
include can be dropped.
module.h is not needed as this code is always built-in.
Signed-off-by: Rob Herring
Cc: Grant Likely
---
v2: no change
drivers/of/fdt.c | 5 -
1 file changed, 5 deletions(-)
From: Rob Herring
of_scan_flat_dt_by_path is unused anywhere in the kernel, so remove it.
Signed-off-by: Rob Herring
---
v2: no change
drivers/of/fdt.c | 67 --
include/linux/of_fdt.h | 3 ---
2 files changed, 70 deletions(-)
diff --git
From: Rob Herring
With libfdt support, we can take advantage of helper accessors in libfdt
for accessing the FDT header data. This makes the code more readable and
makes the FDT blob structure more opaque to the kernel. This also
prepares for removing struct boot_param_header completely.
Signed-
From: Rob Herring
Make of_get_flat_dt_prop arguments compatible with libfdt fdt_getprop
call in preparation to convert FDT code to use libfdt. Make the return
value const and the property length ptr type an int.
Signed-off-by: Rob Herring
---
v2: fix warning on microblaze
arch/arc/kernel/devt
From: Rob Herring
The kernel FDT functions predate libfdt and are much more limited in
functionality. Also, the kernel functions and libfdt functions are
not compatible with each other because they have different definitions
of node offsets. To avoid this incompatibility and in preparation to
add
From: Rob Herring
Both powerpc and microblaze have the same FDT blob in debugfs feature.
Move this to common location and remove the powerpc and microblaze
implementations. This feature could become more useful when FDT
overlay support is added.
This changes the path of the blob from "$arch/flat
From: Rob Herring
Move the /memreserve/ processing and dtb memory reservations into
early_init_fdt_scan_reserved_mem. This converts arm, arm64, and powerpc
as they are the only users of early_init_fdt_scan_reserved_mem.
memblock_reserve is safe to call on the same region twice, so the
reservatio
From: Rob Herring
With libfdt support, we can take advantage of helper accessors in libfdt
for accessing the FDT header data. This makes the code more readable and
makes the FDT blob structure more opaque to the kernel. This also
prepares for removing struct boot_param_header completely.
Signed-
From: Rob Herring
Add a wrapper function to retrieve the FDT size from the FDT header. This
is primarily to avoid libfdt include paths for the whole kernel.
Signed-off-by: Rob Herring
---
v2: new patch
drivers/of/fdt.c | 8
include/linux/of_fdt.h | 1 +
2 files changed, 9 inser
From: Rob Herring
Fix warnings in early_init_dt_reserve_memory_arch when phys_addr_t is
32-bit and memblock is not enabled.
Signed-off-by: Rob Herring
---
v2: New patch
drivers/of/fdt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
From: Rob Herring
Now that all accesses to FDT header data has been converted to accessor
helpers, initial_boot_params can become an opaque pointer.
Signed-off-by: Rob Herring
---
v2: no change
drivers/of/fdt.c | 2 +-
include/linux/of_fdt.h | 2 +-
2 files changed, 2 insertions(+), 2 d
From: Rob Herring
Remove the direct accesses to FDT header data using accessor
function instead. This makes the code more readable and makes the FDT
blob structure more opaque to the arch code. This also prepares for
removing struct boot_param_header completely.
Signed-off-by: Rob Herring
Cc: T
From: Rob Herring
Now powerpc is the only user of struct boot_param_header and FDT defines,
so they can be moved into the powerpc architecture code.
Signed-off-by: Rob Herring
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-...@lists.ozlabs.org
---
v2: no change
arch/powerpc/incl
From: Rob Herring
Unify the various architectures __dtb_start and __dtb_end definitions
moving them into of_fdt.h.
Signed-off-by: Rob Herring
Acked-by: Vineet Gupta
Acked-by: James Hogan
Cc: Ralf Baechle
Cc: Jonas Bonn
Cc: Chris Zankel
Cc: Max Filippov
Cc: linux-me...@vger.kernel.org
Cc:
From: Rob Herring
The architecture code does not need to access the internals of the FDT
blob directly, so make the pointers to it void * and use char arrays
for section variables.
Signed-off-by: Rob Herring
Cc: Ralf Baechle
---
v2: no change
arch/mips/include/asm/mips-boards/generic.h | 4 +
From: Rob Herring
This is a series of clean-ups of architecture FDT code and converts the
core FDT code over to using libfdt functions. This is in preparation
to add FDT based address translation parsing functions for early
console support. This series removes direct access to FDT data from all
a
Hi Thierry
Thank you for the comments.
On 04/22/2014 04:34 PM, Thierry Reding wrote:
On Mon, Apr 21, 2014 at 09:28:33PM +0900, YoungJun Cho wrote:
[...]
diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h
index 7209df1..244d197 100644
--- a/include/drm/drm_mipi_dsi.h
+++ b/inc
On Tue, 22 Apr 2014 18:53:51 +0530, Shaik Ameer Basha wrote:
> Hi KyongHo Cho,
>
>
>
> On Fri, Mar 14, 2014 at 10:40 AM, Cho KyongHo wrote:
> > Some master device descriptor like fimc-is which is an abstraction
> > of very complex H/W may have multiple System MMUs. For those devices,
> > the de
Hi Andrzej
Thank you for comments.
On 04/22/2014 09:15 PM, Andrzej Hajda wrote:
Hi YoungJun,
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
Some phy control registers are not kept after software reset.
So this patch makes the clocks containing phy control to be set
after software reset.
Signed-
From: Josh Cartwright
The Qualcomm 8941 and 8841 PMICs are components used with the Snapdragon
800 series SoC family. This driver exists largely as a glue mfd component,
it exists to be an owner of an SPMI regmap for children devices
described in device tree.
Signed-off-by: Josh Cartwright
Sig
From: Josh Cartwright
Document the bindings used to describe the Qualcomm 8x41 PMICs.
Signed-off-by: Josh Cartwright
Signed-off-by: Courtney Cavin
---
Documentation/devicetree/bindings/mfd/pm8x41.txt | 34
1 file changed, 34 insertions(+)
create mode 100644 Documenta
On Tuesday 22 April 2014 06:02 PM, Stephen Hemminger wrote:
> On Tue, 22 Apr 2014 17:21:13 -0400
> Santosh Shilimkar wrote:
>
>> NetCP driver has a plug-in module architecture where each of the NetCP
>> sub-modules exist as a loadable kernel module which plug in to the netcp
>> core. These sub-mo
Rahul Sharma wrote:
>
> The patch adds the dts files for exynos5260.
>
> Signed-off-by: Pankaj Dubey
> Signed-off-by: Rahul Sharma
> Signed-off-by: Arun Kumar K
> Reviewed-by: Tomasz Figa
Looks good to me. I will queue this 5260 SoC dtsi and 3rd xyref5260 board dt
for 3.6 and I hope I can se
Tomasz Figa wrote:
>
> On 16.04.2014 10:08, Sachin Kamat wrote:
> > Hi Tomasz,
> >
> > On 16 April 2014 13:27, Tomasz Figa wrote:
> >> Hi Rahul,
> >>
> >>
> >> On 16.04.2014 05:58, Rahul Sharma wrote:
> >>>
> >>> From: Pankaj Dubey
> >>>
> >>> This patch add basic arch side support for exynos526
The mailbox module is capable of generating two interrupts
to MPU in OMAP2420, compared to one in OMAP2430. The second
interrupt is to handle interrupts from the additional IVA
processor present only on OMAP2420.
Move the current common mailbox DT node into the SoC
specific files to allow the abov
Hi Tony, Benoit,
This series includes couple of minor fixes in the OMAP DTS files. The patches
are based on 3.15-rc2.
The first patch fixes the only WARN_ON trace present during kernel boot on
OMAP5 uEVM, and this has been present since some time now.
[0.045578] [ cut here ]-
AM3517 inherits OMAP3 dts file, but does not have all the IPs
that are present on OMAP3. This patch disables the following
absent IPs for AM3517: Mailbox, IVA, MMU_ISP, MPU_IVA SmartReflex.
A label had to be added for IVA node in omap3.dtsi to be able to
get a reference to the node for disabling.
Add the mailbox device DT node for OMAP5 SoC. The OMAP5 mailbox
IP is identical to that used in OMAP4.
The OMAP5 hwmod data no longer publishes the module address space,
so this patch fixes the WARN_ON backtrace associated with the
following trace during the kernel boot:
"omap_hwmod: mailbox: does
On Tue, 22 Apr 2014 17:21:13 -0400
Santosh Shilimkar wrote:
> NetCP driver has a plug-in module architecture where each of the NetCP
> sub-modules exist as a loadable kernel module which plug in to the netcp
> core. These sub-modules are represented as "netcp-devices" in the dts
> bindings. It is
On Mon, Apr 14, 2014 at 8:33 PM, Geert Uytterhoeven
wrote:
> From: Geert Uytterhoeven
>
> Signed-off-by: Geert Uytterhoeven
> Cc: Linus Walleij
> Cc: Laurent Pinchart
> Cc: linux-g...@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> v2:
> - Functional clock is mandatory depending on
Couple of patches to add Keystone NetCP ethernet driver support.
The network coprocessor (NetCP) is a hardware accelerator that processes
Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accel
From: Sandeep Nair
The network coprocessor (NetCP) is a hardware accelerator that processes
Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accelerator (PA) module to perform packet classifi
This 2 patches adding display support for openmoko gta04 device.
First patch add DT bindings for topolly td028 panel and second add description
for
dss + panel.
Marek Belisko (2):
omapdss: panel-tpo-td028ec1: Add DT support.
ARM: dts: oma3-gta04: Add display support
.../bindings/video/toppo
Signed-off-by: Marek Belisko
---
.../bindings/video/toppoly,td028ttec1.txt | 30
.../omap2/displays-new/panel-tpo-td028ttec1.c | 32 +-
2 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/vi
This patch add support for lcd display on gta04 board. Display control
is connected on spi (used spi bitbang driver).
Signed-off-by: Marek Belisko
---
arch/arm/boot/dts/omap3-gta04.dts | 86 +++
1 file changed, 86 insertions(+)
diff --git a/arch/arm/boot/dts/
Add the necessary nodes to enable the LCD controller and the
LCD panel that is attached to the Texas Instruments AM335x
EVMSK platform. Also setup the necessary pin mux within the
DT file to drive the LCD connector and add the correct
pinmux settings for the lcd pins to be configured to when
the S
[ Moved Lorenzo up in the addressee list to get his attention ]
On Tue, 22 Apr 2014, Daniel Lezcano wrote:
> On 04/22/2014 05:40 PM, Nicolas Pitre wrote:
> > On Tue, 22 Apr 2014, Daniel Lezcano wrote:
> >
> > > On 04/22/2014 08:17 AM, Abhilash Kesavan wrote:
> > > > +/*
> > > > + * The common v7
On 04/22/2014 01:58 PM, Nishanth Menon wrote:
On 04/22/2014 01:52 PM, Dave Gerlach wrote:
The VTT regulator for DDR3 termination on the am437x-gp-evm is
controlled by a gpio. It is configured by the bootloader so here we
define an always-on, fixed voltage regulator to hold the gpio.
Signed-off-
On 04/22/2014 02:01 PM, Tony Lindgren wrote:
* Dave Gerlach [140422 11:52]:
This patch, along with patch here [1], fixes boot for am437x-gp-evm. The
bootloader configures gpio5_7 to control the DDR3 termination regulator,
the linked patch prevents that gpio bank from being reset and losing
the
On Mon, Apr 14, 2014 at 01:46:12PM +0200, Robert Baldyga wrote:
That's quite some CC list you've got there, and the mail seems a bit
corrupted too (it confused my MUA).
> This patch adds extcon devicetree bindings. Documentation describes in general
> client and provider bindings, and contains de
On 04/22/2014 05:40 PM, Nicolas Pitre wrote:
On Tue, 22 Apr 2014, Daniel Lezcano wrote:
On 04/22/2014 08:17 AM, Abhilash Kesavan wrote:
Add machine-dependent MCPM call-backs for Exynos5420. These are used
to power up/down the secondary CPUs during boot, shutdown, s2r and
switching.
Signed-off
On Tue, 22 Apr 2014, Abhilash Kesavan wrote:
> Add machine-dependent MCPM call-backs for Exynos5420. These are used
> to power up/down the secondary CPUs during boot, shutdown, s2r and
> switching.
>
> Signed-off-by: Thomas Abraham
> Signed-off-by: Inderpal Singh
> Signed-off-by: Andrew Brestic
From: Heiko Stuebner
It's possible that the controller has an individually switchable power supply.
Therefore add support to control a supplying regulator.
As this is not always the case, the regulator is requested as optional.
Signed-off-by: Heiko Stuebner
---
.../bindings/input/touchscreen/
* Dave Gerlach [140422 11:52]:
> This patch, along with patch here [1], fixes boot for am437x-gp-evm. The
> bootloader configures gpio5_7 to control the DDR3 termination regulator,
> the linked patch prevents that gpio bank from being reset and losing
> the previously configured state, and this pa
On 04/22/2014 01:52 PM, Dave Gerlach wrote:
> The VTT regulator for DDR3 termination on the am437x-gp-evm is
> controlled by a gpio. It is configured by the bootloader so here we
> define an always-on, fixed voltage regulator to hold the gpio.
>
> Signed-off-by: Dave Gerlach
> ---
> arch/arm/boo
The VTT regulator for DDR3 termination on the am437x-gp-evm is
controlled by a gpio. It is configured by the bootloader so here we
define an always-on, fixed voltage regulator to hold the gpio.
Signed-off-by: Dave Gerlach
---
arch/arm/boot/dts/am437x-gp-evm.dts | 11 +++
1 file changed,
This patch, along with patch here [1], fixes boot for am437x-gp-evm. The
bootloader configures gpio5_7 to control the DDR3 termination regulator,
the linked patch prevents that gpio bank from being reset and losing
the previously configured state, and this patch binds the gpio to a
regulator so the
On Tue, Apr 15, 2014 at 10:00 AM, Ludovic Desroches
wrote:
> On Tue, Apr 15, 2014 at 09:39:59AM +0200, Richard Genoud wrote:
>> On 14/04/2014 17:22, Ludovic Desroches wrote:
>> > Hi Richard,
>> >
>> > On Mon, Apr 14, 2014 at 04:58:02PM +0200, Richard Genoud wrote:
>> >> RTS pin is an active low pi
Signed-off-by: Geert Uytterhoeven
Cc: Benoit Cousson
Cc: Srinivas Kandagatla
Cc: linux-o...@vger.kernel.org
Cc: ker...@stlinux.com
Cc: linux-arm-ker...@lists.infradead.org
---
arch/arm/boot/dts/am33xx.dtsi |4 ++--
arch/arm/boot/dts/am4372.dtsi |4 ++--
arch/arm/boot/d
Signed-off-by: Geert Uytterhoeven
Cc: Linus Walleij
Cc: Signed-off-by: Mark Brown
---
.../devicetree/bindings/pinctrl/pinctrl-st.txt |4 ++--
.../bindings/sound/davinci-mcasp-audio.txt |2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/device
Signed-off-by: Geert Uytterhoeven
---
drivers/of/irq.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 9bcf2cf19357..e2e4c548a42f 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -364,7 +364,7 @@ int of_irq_to_resource(struct
Signed-off-by: Geert Uytterhoeven
Cc: Dinh Nguyen
Cc: Arnd Bergmann
Cc: net...@vger.kernel.org
---
.../devicetree/bindings/net/socfpga-dwmac.txt |2 +-
Documentation/devicetree/bindings/net/stmmac.txt |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documenta
On Tue, Apr 22, 2014 at 07:17:54PM +0530, Tushar Behera wrote:
> On 22 April 2014 16:14, Mark Brown wrote:
> > In general this isn't up to modern standards, please do try to check
> > that new code is following best practices. Did the support for setting
> > the clocking up in the device tree ge
On Fri, 2014-04-18 at 15:29 +0400, Alexander Popov wrote:
>
> 2014-04-17 0:44 GMT+04:00 Gerhard Sittig :
> > On Tue, 2014-04-15 at 14:54 +0400, Alexander Popov wrote:
> >>
> >> +- reg: Address and size of the DMA controller's register set
> >> +- interrupts: Interrupt for the DMA controller. Gener
On 04/17/2014 10:45 AM, Antoine Ténart wrote:
> After adding support for the Berlin BG2Q GPIOs, this series uses the
> same GPIO dwapb driver to support the Berlin BG2 and BG2CD GPIOs.
>
> Applies on top of Sebastian's for-next branch[1].
>
> [1] https://github.com/shesselba/linux-berlin/commits/
On Thu, 10 Apr 2014, Vivek Gautam wrote:
> Add support to consume phy provided by Generic phy framework.
> Keeping the support for older usb-phy intact right now, in order
> to prevent any functionality break in absence of relevant
> device tree side change for ohci-exynos.
> Once we move to new p
On Tue, 22 Apr 2014, Vivek Gautam wrote:
> On Thu, Apr 10, 2014 at 6:54 PM, Vivek Gautam
> wrote:
> > Add support to consume phy provided by Generic phy framework.
> > Keeping the support for older usb-phy intact right now, in order
> > to prevent any functionality break in absence of relevant
>
[Added MMC maintainers Chris and Ulf for one question below]
On 04/22/2014 10:27 AM, Antoine Ténart wrote:
> Add the SDHCI nodes for the Marvell Berlin BG2Q, using the mrvl,pxav3-mmc
> driver.
>
> Signed-off-by: Antoine Ténart
> ---
> arch/arm/boot/dts/berlin2q.dtsi | 32 +++
On 04/22/2014 06:28 PM, Thomas Petazzoni wrote:
> Dear Antoine Ténart,
>
> On Tue, 22 Apr 2014 17:38:22 +0200, Antoine Ténart wrote:
>> The BG2Q has an AHCI SATA controller. Add the corresponding node
>> in its device tree.
>
> I believe the commit log should explain why an apparently unrelated
>
On 04/22/2014 05:38 PM, Antoine Ténart wrote:
> The berlin-achi driver allows Berlin SoCs to support their AHCI SATA
> controller.
> Add the compatible to the device tree bindings documentation.
>
> Signed-off-by: Antoine Ténart
> ---
> Documentation/devicetree/bindings/ata/ahci-platform.txt |
This adds the EC i2c tunnel (and devices under it) to the
tegra124-venice2 device tree.
Signed-off-by: Doug Anderson
Tested-by: Andrew Bresticker
Tested-by: Stephen Warren
---
Changes in v2:
- Removed i2c20 alias for i2c tunnel
arch/arm/boot/dts/tegra124-venice2.dts | 26 +
On ARM Chromebooks we have a few devices that are accessed by both the
AP (the main "Application Processor") and the EC (the Embedded
Controller). These are:
* The battery (sbs-battery).
* The power management unit tps65090.
On the original Samsung ARM Chromebook these devices were on an I2C
bus
This series adds the most critical cros_ec changes for newer boards
using cros_ec. Specifically:
* Fixes timing/locking issues with the previously upstreamed (but
never used upstream) cros_ec_spi driver.
* Updates the cros_ec header file to the latest version which allows
us to use newer EC fe
Dear Antoine Ténart,
On Tue, 22 Apr 2014 17:38:21 +0200, Antoine Ténart wrote:
> The berlin-achi driver allows Berlin SoCs to support their AHCI SATA
> controller.
> Add the compatible to the device tree bindings documentation.
>
> Signed-off-by: Antoine Ténart
Typo in the commit title: s/achi
Dear Antoine Ténart,
On Tue, 22 Apr 2014 17:38:22 +0200, Antoine Ténart wrote:
> + ahci: sata@e9 {
> + compatible = "marvell,berlin-ahci";
> + reg = <0xe9 0x1>;
> + interrupts = ;
> + status =
Dear Antoine Ténart,
On Tue, 22 Apr 2014 17:38:22 +0200, Antoine Ténart wrote:
> The BG2Q has an AHCI SATA controller. Add the corresponding node
> in its device tree.
I believe the commit log should explain why an apparently unrelated
generic-regs@ node gets added in this commit.
Thanks!
Thoma
Hi Ivan,
On 22/04/14 10:20, Ivan T. Ivanov wrote:
From: "Ivan T. Ivanov"
Allows MSM OTG controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanov
---
.../devicetree/bindings/usb/msm-hsusb.txt | 67 +
drivers/usb/phy/phy-msm-usb.c |
On Tue, Apr 22, 2014 at 04:30:36PM +0100, Rob Herring wrote:
> On Tue, Apr 22, 2014 at 10:25 AM, Catalin Marinas
> wrote:
> > On Tue, Apr 22, 2014 at 04:02:19PM +0100, Arnd Bergmann wrote:
> >> On Saturday 19 April 2014, Thomas Petazzoni wrote:
>
> [...]
>
> >> I would hope we can find a way to
Linus,
On Tue, Apr 22, 2014 at 02:48:04PM +0200, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 3:07 PM, Antoine Ténart
> wrote:
>
> > When using a group only pinctrl driver, which does not have any
> > information on the pins it is useless to define a get_group_pins
> > always returning an empt
Am Dienstag, den 22.04.2014, 09:23 +0200 schrieb Thierry Reding:
> On Mon, Apr 21, 2014 at 01:43:18PM -0600, Stephen Warren wrote:
> > On 04/17/2014 06:02 AM, Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > Properties referencing GPIOs should use the plural suffix -gpios. This
> > >
Linus,
On Tue, Apr 22, 2014 at 02:52:10PM +0200, Linus Walleij wrote:
> On Fri, Apr 11, 2014 at 3:35 PM, Sebastian Hesselbarth
> wrote:
> > On 04/11/2014 02:37 PM, Antoine Ténart wrote:
> >> On Fri, Apr 11, 2014 at 11:03:48AM +0200, Sebastian Hesselbarth wrote:
> >>> On 04/10/2014 03:07 PM, Antoi
On Tue, Apr 22, 2014 at 10:28 AM, Alexey Charkov wrote:
> This should make the driver usable with VIA/WonderMedia ARM-based
> Systems-on-Chip integrated Rhine III adapters. Note that these
> are always in MMIO mode, and don't have any known EEPROM.
>
> Signed-off-by: Alexey Charkov
For the bindi
The BG2Q has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 07452a7
This series adds the support for Berlin SoCs AHCI controllers. The
controller allows to use the SATA host interface and, for example, the
eSATA port on the BG2Q.
Also enable the eSATA interface on the BG2Q DMP.
Tested on the BG2Q DMP.
Antoine Ténart (6):
ata: ahci: add AHCI support for Berlin
On Mon, Apr 21, 2014 at 06:39:17PM -0700, Florian Fainelli wrote:
> Add a DTS file for the Broadcom BCM963138DVT reference platform board
> which leverages the bcm63138.dtsi SoC DTSi file.
>
> Signed-off-by: Florian Fainelli
> ---
> arch/arm/boot/dts/Makefile| 3 +++
> arch/arm/boot/dts
The BG2Q has an AHCI SATA controller with an eSATA interface. Enable it.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
The BG2CD has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2cd.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 094968c275
On Tue, 22 Apr 2014, Daniel Lezcano wrote:
> On 04/22/2014 08:17 AM, Abhilash Kesavan wrote:
> > Add machine-dependent MCPM call-backs for Exynos5420. These are used
> > to power up/down the secondary CPUs during boot, shutdown, s2r and
> > switching.
> >
> > Signed-off-by: Thomas Abraham
> > Sig
The BG2 has an AHCI SATA controller. Add the corresponding node
in its device tree.
Signed-off-by: Antoine Ténart
---
arch/arm/boot/dts/berlin2.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f1052..3e98
The berlin-achi driver allows Berlin SoCs to support their AHCI SATA controller.
Add the compatible to the device tree bindings documentation.
Signed-off-by: Antoine Ténart
---
Documentation/devicetree/bindings/ata/ahci-platform.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff -
On Tue, Apr 22, 2014 at 8:11 AM, Linus Walleij wrote:
> On Tue, Apr 15, 2014 at 5:10 AM, Andy Gross wrote:
>
>> This set of patches adds pinctrl support for the Qualcomm IPQ8064 platform.
>> The IPQ8064 uses the same TLMM block as the APQ8064, but has a different
>> number
>> of pins, functions,
Remove legacy PCI DMA wrappers and instead use generic DMA functions
directly in preparation for OF bus binding
Signed-off-by: Alexey Charkov
---
drivers/net/ethernet/via/via-rhine.c | 84 ++--
1 file changed, 43 insertions(+), 41 deletions(-)
diff --git a/driver
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