Hi, Dinh.
Thanks for pointing out.
Will Fix it.
Best Regards,
Jaehoon Chung
On 06/10/2014 12:53 AM, Dinh Nguyen wrote:
> On Mon, 2014-06-09 at 12:34 +0900, Jaehoon Chung wrote:
>> dw-mmc controller can support multiple slots.
>> But, there are no use-cases anywhere. So we don't need to support t
This patch add support for the imx6dl based aristainetos board
with following configuration:
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
DRAM: 1 GiB
NAND: 512 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB
As this board can used
Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
defined under "controller-data" node under each slave node.
&spi_x {
cs-gpios <>;
...
slave_node {
controller-data {
cs-gpio = <>;
...
This patch moves the "cs-gpio" field from "controller-data" child
node to under the spi device node.
Respective changes are preposed to spi-s3c64xx.c driver.
Signed-off-by: Naveen Krishna Chatradhi
Acked-by: Rob Herring
Cc: Javier Martinez Canillas
Cc: Doug Anderson
Cc: Tomasz Figa
---
Chang
Hello Tomasz,
On 11 June 2014 01:19, Tomasz Figa wrote:
> Hi Naveen,
>
> On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
>> Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
>> defined under "controller-data" node under each slave node.
>
> [snip]
>
>> @@ -85,6 +83,7 @@ Example
Hello Doug,
On 10 June 2014 23:56, Doug Anderson wrote:
> Naveen,
>
> Not a full review, but a few quick things I happened to notice:
>
> On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
> wrote:
>> @@ -94,7 +93,6 @@ Example:
>> spi-max-frequency = <1>;
>>
>>
When the output clock of AUDSS mux is disabled, we are getting kernel
oops while doing a clk_get() on other clocks provided by AUDSS. Though
user manual doesn't specify this dependency, we came across this issue
while disabling the parent of AUDSS mux clocks.
Keeping the parents of AUDSS mux alway
Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux.
As per the user manual, it should be CLK_MAU_EPLL.
The problem surfaced when the bootloader in Peach-pit board set
the EPLL clock as the parent of AUDSS mux. While booting the kernel,
we used to get a system hang during late boot
Peach-pi board has MAX98090 audio codec connected on HSI2C-7 bus.
Signed-off-by: Tushar Behera
---
arch/arm/boot/dts/exynos5800-peach-pi.dts | 31 +
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5
With next-20140610, Peach-pit/Peach-pi board hangs during boot if we
run 'sound init' during u-boot. The issue is fixed in following patches.
While at it, also enable audio support for Peach-pi board.
How to test audio on Peach-pi:
* On top of exynos_defconfig, enable SND_SOC_SNOW and
Adding devicetree and linux-arm-kernel lists based on feedback on IRC...
On Tue, Jun 10, 2014 at 12:46 PM, Jason Kridner wrote:
> I'd like to discuss moving our current library of cape devicetree
> overlay sources into a single tree, including the boot .dtb files for
> BeagleBoard.org boards and
On 06/10/2014 08:59 PM, Guenter Roeck wrote:
> Commit bf5db2f (microblaze: Use generic device.h) removes the
> microblaze specific pdev_archdata and dma_mask.
>
> At the same time, commit 591c1ee (of: configure the platform
> device dma parameters) initializes the just removed field.
> This causes
The regulation_constraints structure includes specific field to support
suspend state for global PMIC STANDBY/HIBERNATE mode. This patch add support
for parsing regulator_state for suspend state.
Signed-off-by: Chanwoo Choi
---
drivers/regulator/of_regulator.c | 76 ++
This patch add regulator suspend state to constraint in dt file. The regulation_
constraints structure already has regulator suspend state field as following.
The regulator suspend state control the state of regulator according to
PM (Power Management) state.
- struct regulator_state state_disk
- s
The regulators would set different state/mode according to the kind of suspend
state. So regulation_constraints structure has already regulator suspend state
filed.
This patch parse regulator suspend state from devicetree file.
For example:
ldoX_reg: LDOx {
regulator-name
On Tuesday, June 10, 2014 11:42:25 PM Tomasz Figa wrote:
> On 10.06.2014 23:27, Greg Kroah-Hartman wrote:
> > On Tue, Jun 10, 2014 at 11:27:45PM +0200, Rafael J. Wysocki wrote:
> >> On Tuesday, June 10, 2014 02:53:26 PM Ulf Hansson wrote:
> >>> On 10 June 2014 14:11, Rafael J. Wysocki wrote:
> >>>
This patch is against 'renesas-devel-v3.15-20140610' tag of Simon Horman's
> 'renesas.git' repo.
>
> Changes in version 2:
> - removed I2C devices, to be added by separate patches.
>
> arch/arm/boot/dts/r8a7791-henninger.dts | 13 +
>
On Wed, Jun 11, 2014 at 03:04:18AM +0400, Sergei Shtylyov wrote:
> Hello.
>
>Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
> 'renesas-devel-v3.15-20140610' tag plus the Henninger I2C2 DT support patch
> that I posted e
Define the Henninger board dependent part of the VIN0 device node. Add the
device node for Analog Devices ADV7180 video decoder to I2C2 bus. Add the
necessary subnodes to interconnect VIN0 and ADV7180 devices.
Signed-off-by: Sergei Shtylyov
---
arch/arm/boot/dts/r8a7791-henninger.dts | 35 ++
Define the generic R8A7791 parts of the VIN[0-2] device nodes. Add aliases for
the VIN[0-2] device nodes.
Signed-off-by: Sergei Shtylyov
---
arch/arm/boot/dts/r8a7791.dtsi | 27 +++
1 file changed, 27 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7791.dtsi
==
Hello.
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-v3.15-20140610' tag plus the Henninger I2C2 DT support patch
that I posted earlier. Here we add the VIN and ADV7180 video decoder device
tree support on the R8A7791
Define the Henninger board dependent part of the I2C2 device node.
Based on the Koelsch I2C2 device tree patch by Wolfram Sang.
Signed-off-by: Sergei Shtylyov
---
This patch is against 'renesas-devel-v3.15-20140610' tag of Simon Horman's
'renesas.git' repo.
Changes in
This adds the Gumstix Pepper[1] single-board computer based on the
TI AM335x processor. Schematics are available [2].
[1] https://store.gumstix.com/index.php/products/344/
[2] https://pubs.gumstix.com/boards/PEPPER/
Signed-off-by: Ash Charles
---
arch/arm/boot/dts/Makefile | 3 +-
ar
On Tue, Jun 10, 2014 at 8:59 AM, Florian Vaussard
wrote:
> It is not very common to add oneself as the maintainer of a single .dts
> file. I could only found the am335x-nano.dts with such a way of doing.
> Usually get_maintainer.pl will also take into account the commit author
> and properly handl
On 10 June 2014 23:42, Tomasz Figa wrote:
> On 10.06.2014 23:27, Greg Kroah-Hartman wrote:
>> On Tue, Jun 10, 2014 at 11:27:45PM +0200, Rafael J. Wysocki wrote:
>>> On Tuesday, June 10, 2014 02:53:26 PM Ulf Hansson wrote:
On 10 June 2014 14:11, Rafael J. Wysocki wrote:
> On Tue, Jun 10,
On 10.06.2014 23:27, Greg Kroah-Hartman wrote:
> On Tue, Jun 10, 2014 at 11:27:45PM +0200, Rafael J. Wysocki wrote:
>> On Tuesday, June 10, 2014 02:53:26 PM Ulf Hansson wrote:
>>> On 10 June 2014 14:11, Rafael J. Wysocki wrote:
On Tue, Jun 10, 2014 at 12:51 PM, Ulf Hansson
wrote:
>
On Tue, Jun 10, 2014 at 11:27:45PM +0200, Rafael J. Wysocki wrote:
> On Tuesday, June 10, 2014 02:53:26 PM Ulf Hansson wrote:
> > On 10 June 2014 14:11, Rafael J. Wysocki wrote:
> > > On Tue, Jun 10, 2014 at 12:51 PM, Ulf Hansson
> > > wrote:
> > >> From: Tomasz Figa
> > >>
> > >> On a number o
On Tuesday, June 10, 2014 02:53:26 PM Ulf Hansson wrote:
> On 10 June 2014 14:11, Rafael J. Wysocki wrote:
> > On Tue, Jun 10, 2014 at 12:51 PM, Ulf Hansson
> > wrote:
> >> From: Tomasz Figa
> >>
> >> On a number of platforms, devices are part of controllable power
> >> domains, which need to b
On Tue, Jun 10, 2014 at 1:09 PM, Doug Anderson wrote:
> Naveen / Sylwester,
>
> On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
> wrote:
>>> Can we support both "cs-gpio" and "cs-gpios" for backward compatibility ?
>>> After your change all DTBs using the original pattern will not work with
>>
Tomasz,
On Tue, Jun 10, 2014 at 12:59 PM, Tomasz Figa wrote:
> On 10.06.2014 21:58, Doug Anderson wrote:
>> Tomasz,
>>
>> On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa wrote:
>>> This is wrong. The "cs-gpios" property is supposed to be an array,
>>> indexed by chip select number of SPI devices (
On 10.06.2014 21:58, Doug Anderson wrote:
> Tomasz,
>
> On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa wrote:
>> This is wrong. The "cs-gpios" property is supposed to be an array,
>> indexed by chip select number of SPI devices (indicated by their "reg"
>> properties).
>>
>> Moreover, is there a n
Tomasz,
On Tue, Jun 10, 2014 at 12:49 PM, Tomasz Figa wrote:
> This is wrong. The "cs-gpios" property is supposed to be an array,
> indexed by chip select number of SPI devices (indicated by their "reg"
> properties).
>
> Moreover, is there a need to parse this manually in this driver? I can
> se
Hi Naveen,
On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
> Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
> defined under "controller-data" node under each slave node.
[snip]
> @@ -85,6 +83,7 @@ Example:
> #size-cells = <0>;
> pinctrl-names = "
Hi,
compiling this driver gives me:
drivers/i2c/busses/i2c-sun6i-p2wi.c: In function 'p2wi_probe':
drivers/i2c/busses/i2c-sun6i-p2wi.c:272:2: error: implicit declaration of
function 'devm_reset_control_get' [-Werror=implicit-function-declaration]
drivers/i2c/busses/i2c-sun6i-p2wi.c:272:13: warni
On 10.06.2014 20:09, Doug Anderson wrote:
> Naveen / Sylwester,
>
> On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
> wrote:
>>> Can we support both "cs-gpio" and "cs-gpios" for backward compatibility ?
>>> After your change all DTBs using the original pattern will not work with
>>> new kernel
Hi,
On Sat, Jun 07, 2014 at 07:36:19PM +0200, Max Schwarz wrote:
> Driver for the native I2C adapter found in Rockchip RK3xxx SoCs.
>
> Configuration is only possible through devicetree. The driver is
> interrupt driven and supports the I2C_M_IGNORE_NAK mangling bit.
>
> Signed-off-by: Max Schwa
On 10.06.2014 20:26, Doug Anderson wrote:
> Naveen,
>
> Not a full review, but a few quick things I happened to notice:
>
> On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
> wrote:
>> @@ -94,7 +93,6 @@ Example:
>> spi-max-frequency = <1>;
>>
>>
On Tue, May 27, 2014 at 10:35:36AM +0200, Ludovic Desroches wrote:
> +static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
> +struct of_dma *of_dma)
> +{
> + struct at_xdmac_chan*atchan;
> + struct dma_chan *chan;
> + d
Commit bf5db2f (microblaze: Use generic device.h) removes the
microblaze specific pdev_archdata and dma_mask.
At the same time, commit 591c1ee (of: configure the platform
device dma parameters) initializes the just removed field.
This causes all microblaze builds to fail.
Drop the unnecessary ini
Add pcie related options by default for keystone architecture
Signed-off-by: Murali Karicheri
CC: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Herring
CC: Mohit Kumar
CC: Jingoo Han
CC: Bjorn Helgaas
CC: Pratyush Anand
CC: Richard Zhu
CC: Kishon Vijay Abraham I
CC: Marek
v3.65 version of the designware h/w, requires application space
registers to be configured to access the remote EP config space.
To support this, add rd[wr]_other_conf API in the pcie_host_opts
Signed-off-by: Murali Karicheri
CC: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Her
v3.65 version of the dw hw has MSI controller implemented in the
application space. Add a version variable in the port struct to
identify v3.65 hardware for different code treatment. This variable
will have DW_V3_65 bit set when running on this hw version. The host
init code is expected to set this
This patch adds a PCIe controller driver for Keystone SoCs. This
is based on v1 of the series posted to the mailing list.
CC: Santosh Shilimkar
CC: Russell King
CC: Grant Likely
CC: Rob Herring
CC: Mohit Kumar
CC: Jingoo Han
CC: Bjorn Helgaas
CC: Pratyush Anand
CC: Richard Zhu
CC: Kishon
Add dw msi controller functions for v3.65 hw. This adds dw_v3_65_msi_chip
and dw_v3_65_msi_domain_ops so that can be used on this version of the hw.
This required since MSI irq registers reside in the application space
for v3.65 hw. The functions are used by v3.65 dw pci core functions to
support i
This phy driver added to support keystone PCI driver. This is
a generic phy driver and can work with multiple hardware IPs
available on Keystone SoC. The hw vendor that provides the phy
hw published only registers and their values. So this driver
uses these hard coded values to initialize the phy.
keystone pcie hardware is based on designware version 3.65.
This driver make use of the functions from pci-dw-old.c and
pci-dw-old-msi.c to implement the driver.
Driver mainly handle the platform specific part of the
PCI driver and depends on DW Old driver to configure
application specific registe
Current DW PCI host init code has code specific to newer hw such as
ATU port specific resource parsing and map. v3.65 DW PCI host has
MSI controller in application space and requires different controller
initialization code. So refactor the msi host controller code into a
separate function. Other c
Add common PCI controller functions for v3.65 DW hw version. This
provides a function, dw_v3_65_pcie_host_init() to initialize the host.
It check compatibility string dw,snps-pcie-v3.65 that is expected
to be present in the device node of a v3.65 compliant hw and initialize
the controller using oth
Naveen,
Not a full review, but a few quick things I happened to notice:
On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
wrote:
> @@ -94,7 +93,6 @@ Example:
> spi-max-frequency = <1>;
>
> controller-data {
> -
Signed-off-by: Bjorn Andersson
---
.../bindings/pinctrl/qcom,msm8960-pinctrl.txt | 108 ++
drivers/pinctrl/Kconfig|8 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-msm8960.c | 1254
Naveen / Sylwester,
On Tue, Jun 10, 2014 at 4:00 AM, Naveen Krishna Ch
wrote:
>> Can we support both "cs-gpio" and "cs-gpios" for backward compatibility ?
>> After your change all DTBs using the original pattern will not work with
>> new kernels any more. At least I would expect such backward com
On Tuesday 10 June 2014 17:41:18 Maxime Ripard wrote:
> > +DMA clients connected to the Atmel XDMA controller must use the format
> > +described in the dma.txt file, using a three-cell specifier for each
> > channel:
> > +a phandle plus two integer cells.
> > +The three cells in order are:
> > +
>
This makes sure a format string cannot leak into the kobject name that
is constructed. (And splits the >80 character line.)
Signed-off-by: Kees Cook
---
drivers/of/base.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 8368d96a
Hi Ash,
On 06/06/2014 10:51 PM, Ash Charles wrote:
> This adds the Gumstix Pepper[1] single-board computer based on the
> TI AM335x processor. Schematics are available [2].
>
> [1] https://store.gumstix.com/index.php/products/344/
> [2] https://pubs.gumstix.com/boards/PEPPER/
>
> Signed-off-by:
Hi Ludovic,
On Tue, May 27, 2014 at 10:35:36AM +0200, Ludovic Desroches wrote:
> Introduction of a new atmel DMA controller known as xdmac.
>
> Signed-off-by: Ludovic Desroches
> ---
>
> Hi,
>
> All comments are welcomed to improve this driver!
>
> Thanks
>
> .../devicetree/bindings/dma/atm
Hi,
On 26.05.2014 13:56, Shaik Ameer Basha wrote:
> From: Arun Kumar K
>
> Adds IDs for MUX clocks to be used by power domain for MFC
> for doing re-parenting while pd on/off.
>
> Signed-off-by: Arun Kumar K
> Signed-off-by: Shaik Ameer Basha
> ---
> drivers/clk/samsung/clk-exynos5420.c |
Hi,
On 26.05.2014 13:56, Shaik Ameer Basha wrote:
> From: Prathyush K
>
> While powering on/off a local powerdomain in exynos5 chipsets, the input
> clocks to each device gets modified. This behaviour is based on the
> SYSCLK_SYS_PWR_REG registers.
> E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent
On Tuesday 10 June 2014 16:36:04 Maxime Ripard wrote:
> On Tue, Jun 10, 2014 at 03:54:56PM +0200, Arnd Bergmann wrote:
> > On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
> > >
> > > +config I2C_SUN6I_P2WI
> > > + tristate "Allwinner sun6i internal P2WI controller"
> > > + depe
Hi Arnd,
On Tue, Jun 10, 2014 at 03:54:56PM +0200, Arnd Bergmann wrote:
> On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
> >
> > +config I2C_SUN6I_P2WI
> > + tristate "Allwinner sun6i internal P2WI controller"
> > + depends on ARCH_SUNXI
> > + help
> > + If you
On Tuesday 10 June 2014 15:47:16 Boris BREZILLON wrote:
>
> +config I2C_SUN6I_P2WI
> + tristate "Allwinner sun6i internal P2WI controller"
> + depends on ARCH_SUNXI
> + help
> + If you say yes to this option, support will be included for the
> + P2WI (Push/Pull 2
Hello Paul,
On 10/06/2014 10:56, Paul Carpenter wrote:
> Wolfram Sang wrote:
>> On Tue, Jun 03, 2014 at 10:49:52AM +0200, Boris BREZILLON wrote:
>>> The P2WI looks like an SMBus controller which only supports byte data
>>> transfers. But, it differs from standard SMBus protocol on several
>>> aspe
P2WI (Push/Pull 2 Wire Interface) is an SMBus like bus used to communicate
with some PMICs (like the AXP221).
Document P2WI DT bindings which are pretty much the same as the one defined
for the marvell's mv64xxx controller.
Signed-off-by: Boris BREZILLON
---
.../devicetree/bindings/i2c/i2c-sunx
The P2WI controller looks like an SMBus controller which only supports byte
data transfers. But, it differs from standard SMBus protocol on several
aspects:
- it supports only one slave device, and thus drop the address field
- it adds a parity bit every 8bits of data
- only one read access is requ
Hello,
This series adds support for the P2WI block used by some Allwinner boards
to interface with the AXP221 PMIC.
Best Regards,
Boris
Changes since v4:
- add P2WI protocol description in driver header comment
- remove unneeded i2c address check
- remove unneeded irq field from p2wi struct
Ch
Hi Pankaj,
On 10.05.2014 09:20, Pankaj Dubey wrote:
> Let's handle i2c interrupt re-configuration in i2c driver. This will
> help us in removing some soc specific checks from machine files.
> Since only Exynos5250, and Exynos5420 need to do this, added syscon
> based phandle to i2c device nodes of
On 10 June 2014 14:11, Rafael J. Wysocki wrote:
> On Tue, Jun 10, 2014 at 12:51 PM, Ulf Hansson wrote:
>> From: Tomasz Figa
>>
>> On a number of platforms, devices are part of controllable power
>> domains, which need to be enabled before such devices can be accessed
>> and may be powered down w
Add necessary changes for configuring and compiling the Security System driver.
Signed-off-by: LABBE Corentin
---
drivers/crypto/Kconfig | 91 +
drivers/crypto/Makefile | 1 +
2 files changed, 92 insertions(+)
diff --git a/drivers/crypto/Kconfig
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin
---
drivers/crypto/sunxi-ss/Makefile | 19 ++
drivers/crypto/sunxi-ss/s
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin
---
arch/arm/boot/dts/sun7i-a20.dtsi
This patch adds documentation for Device-Tree bindings for the Security
System cryptographic accelerator driver.
Signed-off-by: LABBE Corentin
---
Documentation/devicetree/bindings/crypto/sunxi-ss.txt | 9 +
1 file changed, 9 insertions(+)
create mode 100644 Documentation/devicetree/bin
Hello
This is the driver for the Security System included in Allwinner SoC A20.
The Security System (SS for short) is a hardware cryptographic accelerator that
support AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on others Allwinner SoC:
- A10s and A31 diagram speak about it with pre
On 09/06/2014 05:31, Bo Shen :
> As the at91sam9n12ek has switch to CCF, so add clock for wm8904
>
> Signed-off-by: Bo Shen
> Reviwed-by: Mark Brown
Acked-by: Nicolas Ferre
Thanks.
> ---
> Changes in v2:
> - None
>
> arch/arm/boot/dts/at91sam9n12ek.dts | 2 ++
> 1 file changed, 2 inserti
On 09/06/2014 05:31, Bo Shen :
> As the sama5d3xek board has switch to CCF, so add clock for wm8904
>
> Signed-off-by: Bo Shen
> Reviwed-by: Mark Brown
Acked-by: Nicolas Ferre
And taken for next "dt" branch (maybe can go in before). Thanks.
> ---
> Changes in v2:
> - None
>
> arch/arm/bo
On Tue, Jun 10, 2014 at 12:51 PM, Ulf Hansson wrote:
> From: Tomasz Figa
>
> On a number of platforms, devices are part of controllable power
> domains, which need to be enabled before such devices can be accessed
> and may be powered down when the device is idle to save some power.
> This means
From: Subbaraya Sundeep Bhatta
Add devicetree bindings for Xilinx axi udc driver.
Signed-off-by: Subbaraya Sundeep Bhatta
---
Changes for v3:
- None
Changes for v2:
- replaced xlnx,include-dma with xlnx,has-builtin-dma
.../devicetree/bindings/usb/udc-xilinx.txt | 20
On Wed, May 21, 2014 at 09:33:14PM +0200, Maxime Ripard wrote:
> Hi,
>
> This patch series add the possibility for the topology code to get the
> CPU frequency through a DT clock handle instead of needing a
> clock-frequency property.
>
> Indeed, this information can be quite redundant if the clo
From: Thierry Reding
The XUSB pad controller found on NVIDIA Tegra SoCs provides several pads
that lanes can be assigned to in order to support a variety of interface
options: USB 2.0, USB 3.0, PCIe and SATA.
In addition to the pin controller used to assign lanes to pads two PHYs
are exposed to
From: Thierry Reding
The device tree node in the SoC file contains only the resources (such
as registers, resets, ...) but none of the lane assignment information
since that's board specific and belongs in the board file.
Signed-off-by: Thierry Reding
---
Changes in v2:
- include dt-bindings/pi
From: Thierry Reding
Assign lanes to the XUSB pads as used on the Jetson TK1.
Signed-off-by: Thierry Reding
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/d
From: Thierry Reding
This patch adds the device tree binding documentation for the XUSB pad
controller found on NVIDIA Tegra SoCs. It exposes both pinmuxing and PHY
capabilities.
Signed-off-by: Thierry Reding
---
Changes in v2:
- move header file to this patch and refer to it in the binding
- u
Hello Sylwester,
Thanks for the review.
On 10 June 2014 16:09, Sylwester Nawrocki wrote:
> On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
>> Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
>> defined under "controller-data" node under each slave node.
>>
>> &spi_x {
>> c
On Tue, Jun 10, 2014 at 01:29:17AM +0200, Javier Martinez Canillas wrote:
> On 06/09/2014 09:38 PM, Mark Brown wrote:
> > On Mon, Jun 09, 2014 at 11:37:47AM +0200, Javier Martinez Canillas wrote:
> >> + case REGULATOR_MODE_STANDBY:/* switch off */
> >> + if (id != MAX
Since ux500 uses genpd, this will enable the power domain support.
Cc: Linus Walleij
Cc: Tomasz Figa
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson
---
arch/arm/mach-ux500/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux50
Since genpd at late init, will try to disable unused domains we don't
need to handle it from here as well.
Cc: Simon Horman
Cc: Magnus Damm
Signed-off-by: Ulf Hansson
---
drivers/sh/pm_runtime.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers
There are no active users of this API. Let's remove it and if future
needs shows up which could consider to have a get/put API instead.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c |5 -
include/linux/pm_domain.h |2 --
2 files changed, 4 insertions(+), 3 deletions(-)
The ux500 SoC uses the generic power domain and requires the domains to
be specified through DT.
Currently the callbacks for handling power gating are empty functions
which shall be implemented once each device are handled properly from a
runtime PM perspective.
Cc: Linus Walleij
Cc: Tomasz Figa
The genpd dev_irq_safe configuration overlaps with the runtime PM
pm_runtime_irq_safe() option. Let's remove it.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c |4
include/linux/pm_domain.h |1 -
2 files changed, 5 deletions(-)
diff --git a/drivers/base/power/domain.c
Since genpd at late init, will try to disable unused domains we don't
need to handle it from here as well.
Cc: Kukjin Kim
Signed-off-by: Ulf Hansson
---
arch/arm/mach-exynos/exynos.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exyno
Cc: Linus Walleij
Cc: Tomasz Figa
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson
---
arch/arm/boot/dts/ste-dbx5x0.dtsi |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi
b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index e41eedc..29a7013 100644
--- a
Since ux500 uses the mmci host driver for these devices and since that
driver are well behaving from a runtime PM perspective, we can now add
these device to the VAPE power domain.
Cc: Linus Walleij
Cc: Tomasz Figa
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson
---
arch/arm/boot/dts
As default behavior let genpd at late init try to disable the unused
domains.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index 825e81d..095a4fa4 100644
--- a/dr
There are no active clients of the legacy API and we now also have a
sophisticated way, where driver core deals with adding devices to genpd
while probing. So, let's remove the legacy API.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c | 33 -
includ
Since genpd at late init, will try to disable unused domains we don't
need to handle it from machine specific code as well.
Cc: Ben Dooks
Cc: Kukjin Kim
Signed-off-by: Ulf Hansson
---
arch/arm/mach-s3c64xx/common.c|5 -
arch/arm/mach-s3c64xx/common.h|7 ---
arch
Cc: Linus Walleij
Cc: Tomasz Figa
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson
---
include/dt-bindings/arm/ux500_pm_domains.h | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 include/dt-bindings/arm/ux500_pm_domains.h
diff --git a/include/dt-bindings/ar
There are currently no need to export default_stop_ok() as an API,
instead let's keep it local to the domain governor.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain_governor.c |7 ++-
include/linux/pm_domain.h|9 +
2 files changed, 3 insertions(+), 13 d
CONFIG_PM_GENERIC_DOMAINS depends on CONFIG_PM, thus there are no need
to check explicity for it.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c |4
1 file changed, 4 deletions(-)
diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c
index a2ebc77..0362360
There no users of these callbacks, let's simplify the generic power
domain by removing them.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c | 64 ++-
include/linux/pm_domain.h |8 --
2 files changed, 8 insertions(+), 64 deletions(-)
The dev_irq_safe configuration is redundant, genpd don't have any
special treatmeant for handling it. Let's remove it.
Cc: Simon Horman
Cc: Magnus Damm
Signed-off-by: Ulf Hansson
---
arch/arm/mach-shmobile/pm-rmobile.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobil
The dev_irq_safe configuration is redundant, genpd don't have any
special treatmeant for handling it. Let's remove it.
Cc: Simon Horman
Cc: Magnus Damm
Signed-off-by: Ulf Hansson
---
arch/arm/mach-shmobile/pm-r8a7779.c |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-shmobil
The pm_genpd_syscore_poweroff() API and pm_genpd_syscore_poweron() API
makes the pm_genpd_syscore_switch() API redundant.
Moreover, since there are no active users, let's just remove it.
Signed-off-by: Ulf Hansson
---
drivers/base/power/domain.c | 17 ++---
include/linux/pm_domain
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