Hi,
On 07/07/2014 08:23 PM, John W. Linville wrote:
> Any word from the devicetree folks?
We changed the compatible string from brcm,bcm43xx-fmac to brcm,bcm4329-fmac
at their request, that is the only feedback we've gotten from them AFAIK.
Regards,
Hans
>
> On Sun, Jun 29, 2014 at 04:16:58PM
On Tue, Jul 8, 2014 at 10:54 AM, Mohit KUMAR DCG wrote:
> Pls find attached patches to push through your repo. These are rebased over
> the top
> of 3.16-rc3.
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git
spear/pcie-support-v8
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To unsubscribe from this list: send the line "
Hi Arnd/Rob/Mike et al,
We didn't conclude anything out of this thread and so kicking it
again as we need to close bindings to support cpufreq-cpu0
better for platforms not sharing clock lines across all CPUs.
https://lkml.org/lkml/2014/7/1/358
On 14 May 2014 20:03, Arnd Bergmann wrote:
> On We
Some Freescale boards like T1040RDB have on board CPLD connected on
the IFC bus. Add binding for this in board.txt file
Signed-off-by: Priyanka Jain
---
Changes for v2: Incorporated Scott's comments
.../devicetree/bindings/powerpc/fsl/board.txt | 16
1 files changed, 16
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K
Signed-off-by: Shaik Ameer Basha
Acked-by: Tomasz Figa
---
drivers/clk/samsung/clk-exynos5420.c |6 --
include/dt-bindings/clock/exynos5420.h |2 ++
2 fi
From: Prathyush K
While powering on/off a local powerdomain in exynos5 chipsets, the input
clocks to each device gets modified. This behaviour is based on the
SYSCLK_SYS_PWR_REG registers.
E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC
(aclk
Adding the optional clock property for the mfc_pd for
handling the re-parenting while pd on/off.
Signed-off-by: Arun Kumar K
Signed-off-by: Shaik Ameer Basha
Reviewed-by: Tomasz Figa
---
arch/arm/boot/dts/exynos5420.dtsi |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/d
This patch series for clock handling in power domain is
re-send for merging after rebasing onto latest linux-samsung.git,
for-next branch.
Original series and discussion can be found here:
https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31550.html
Arun Kumar K (2):
clk: exynos5
On 4 July 2014 09:51, Viresh Kumar wrote:
> Yeah, having something like what you suggested from DT is the perfect
> solution to get over this. The only reason why I am not touching that here
> is to not delay other patches just because of that.
>
> There are separate threads going on for that and
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, July 08, 2014 2:56 AM
> To: Jain Priyanka-B32167
> Cc: devicetree@vger.kernel.org; linuxppc-...@lists.ozlabs.org; linux-
> s...@vger.kernel.org; linux-...@lists.infradead.org
> Subject: Re: [PATCH] devicetree/bindings: Add bi
On Tue, Jul 8, 2014 at 9:21 AM, Mohit KUMAR DCG wrote:
> - These patches are rebased over 3-16-rc3 to go through arm-soc tree.
> Somehow we are having 'sync' issue in providing web link for spear public
> repository with these patches.
>
> It will be resolve soon, and I will provide the link.
I c
> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, July 08, 2014 3:00 AM
> To: Jain Priyanka-B32167
> Cc: devicetree@vger.kernel.org; linuxppc-...@lists.ozlabs.org
> Subject: Re: [PATCH] devicetree/bindings/powerpc/fsl: Add binding for
> board
>
> On Mon, 2014-07-07 at 14:06
It will be resolve soon, and I will provide the link.
>
> [ The patchset applies fine to next-20140707 after fixing trivial
> reject in drivers/pci/host/Makefile in patch #8. To make it build
> the following line from patch #8 needs to be dropped:
>
> + spin_loc
On Sat, Jul 5, 2014 at 11:02 PM, Bjorn Helgaas wrote:
> On Wed, Jun 25, 2014 at 11:26:44PM +0530, Kishon Vijay Abraham I wrote:
>> [1] is split into separate series in order for individual subsystem
>> Maintainers to pick up the patches. This series handles the PCIe
>> support for DRA7.
>>
>> Reba
On 07/08/2014 05:04 AM, Kukjin Kim wrote:
> On 07/01/14 20:59, Tushar Behera wrote:
>> On 06/27/2014 08:18 PM, Kevin Hilman wrote:
>>> On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilman
>>> wrote:
On Thu, Jun 26, 2014 at 8:38 PM, Tushar Behera
wrote:
> Would you please provide me th
In order to facilitate understanding, rockchip SPI controller IP design
looks similar in its registers to designware. But IC implementation
is different from designware, So we need a dedicated driver for Rockchip
RK3XXX SoCs integrated SPI. The main differences:
- dma request line: rockchip SPI co
The rev C1 Wandboard uses the Broadcom 4330 for WiFi and Bluetooth instead of
the 4329. This changes the PADS assigned for the control lines. Another
side effect of the change is that on the rev C1 board, usdhc driver can't
detect the chip presence correctly so usdhc2 now needs its 'non-removeabl
This introduces a pinctrl, pinconf, pinmux and gpio driver for the gpio
block found in pm8018, pm8038, pm8058, pm8917 and pm8921 pmics from
Qualcomm.
Signed-off-by: Bjorn Andersson
---
drivers/pinctrl/Kconfig | 11 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl
This introduced the device tree bindings for the gpio block found in
pm8018, pm8038, pm8058, pm8917 and pm8921 pmics from Qualcomm.
Signed-off-by: Bjorn Andersson
---
.../bindings/pinctrl/qcom,pm8xxx-gpio.txt | 230
include/dt-bindings/pinctrl/qcom,pm8xxx-gpio.h
Most status bits, e.g. for GPIO and MPP input, is retrieved by reading
the interrupt status registers, so this needs to be exposed to clients.
Signed-off-by: Bjorn Andersson
---
drivers/mfd/pm8921-core.c | 36
include/linux/mfd/pm8921-core.h | 32 ++
This is device tree bindings as well as a driver for the gpio blocks found in
Qualcomm pm8018, pm8038, pm8058, pm8917 and pm8921 pmic chips.
The first patch extends the pm8921-core to expose a function to read out the
"RT status" of an interrupt pin. This is the way input many input values are
exp
On Fri, Jul 4, 2014 at 8:57 AM, Liviu Dudau wrote:
> On Mon, Apr 07, 2014 at 11:44:51PM +0100, Bjorn Helgaas wrote:
>> On Mon, Apr 7, 2014 at 4:07 AM, Liviu Dudau wrote:
>> > On Mon, Apr 07, 2014 at 10:14:18AM +0100, Benjamin Herrenschmidt wrote:
>> >> On Mon, 2014-04-07 at 09:46 +0100, Liviu Dud
On Tue, Jul 01, 2014 at 07:43:33PM +0100, Liviu Dudau wrote:
> Several platforms use a rather generic version of parsing
> the device tree to find the host bridge ranges. Move the common code
> into the generic PCI code and use it to create a pci_host_bridge
> structure that can be used by arch cod
On Tue, Jul 01, 2014 at 07:43:31PM +0100, Liviu Dudau wrote:
> Make it easier to discover the domain number of a bus by storing
> the number in pci_host_bridge for the root bus. Several architectures
> have their own way of storing this information, so it makes sense
> to try to unify the code. Whi
On 7/1/2014 7:03 PM, Laura Abbott wrote:
> Currently, early_init_dt_scan validates the header, sets the
> boot params, and scans for chosen/memory all in one function.
> Split this up into two separate functions (validation/setting
> boot params in one, scanning in another) to allow for
> additiona
Commit a67a6ed15513541579d38bcbd127e7be170710e5
(of: Check for phys_addr_t overflows in early_init_dt_add_memory_arch)
corrected early_init_dt_add_memory_arch to account for overflows
but did so in an unclean way using ULONG_MAX. There is no
guarantee that sizeof(unsigned long) == sizeof(phys_addr_
To support MIPI command mode based I80 interface panel,
FIMD should do followings:
- Sets LCD I80 interface timings configuration.
- Uses "lcd_sys" as an IRQ resource and sets relevant IRQ configuration.
- Sets LCD block configuration for I80 interface.
- Sets ideal(pixel) clock is 2 times faster t
To support LCD I80 interface, the DSI host calls this function
to notify the panel tearing effect synchronization signal to
the CRTC device manager to trigger to transfer video image.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/exynos/exynos_drm_d
This patch adds common part of dsi node.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index
This patch adds sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/bo
This patch adds MIPI DSI command mode based
S6E3FA0 AMOLED LCD Panel driver.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
drivers/gpu/drm/panel/Kconfig | 7 +
drivers/gpu/drm/panel/Makefile| 1 +
drivers/gpu/drm/panel/panel-s6e3fa0.c | 569
This patch adds mipi-phy node for MIPI DSI device.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos5420.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index
The offset of register DSIM_PLLTMR_REG in Exynos5410 / 5420 / 5440
SoCs is different from the one in Exynos4 SoCs.
In case of Exynos5410 / 5420 / 5440 SoCs, there is no frequency
band bit in DSIM_PLLCTRL_REG, and it uses DSIM_PHYCTRL_REG and
DSIM_PHYTIMING*_REG instead.
So this patch adds driver d
In case of using MIPI DSI based I80 interface panel,
the relevant registers should be set.
So this patch adds relevant DT bindings.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
.../devicetree/bindings/video/samsung-fimd.txt | 28 ++
1 file
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
.../devicetree/bindings/panel/samsung,s6e3fa0.txt | 46 ++
1 file changed, 46 insertions(+)
This configuration could be used in MIPI DSI command mode also.
And adds user manual description for display configuration.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
Reviewed-by: Andrzej Hajda
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 +++--
1 file
This patch adds sysreg property to fimd device node
which is required to use I80 interface.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
arch/arm/boot/dts/exynos4.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/bo
To support LCD I80 interface, the panel should generate
Tearing Effect synchronization signal between MCU and FB
to display video images.
And the display controller should trigger to transfer
video image at this signal.
So the panel receives the TE IRQ, then calls these handler
chains to notify it
Hi,
This series adds LCD I80 interface display support for Exynos DRM driver.
The FIMD(display controller) specification describes it as "LCD I80 interface"
and the DSI specification describes it as "Command mode interface".
This is based on exynos-drm-next branch.
The previous patches,
RFC: htt
There could be the case that the page flip operation isn't finished correctly
with some abnormal condition such as panel reset. So this patch replaces
wait_event() with wait_event_timeout() to avoid waiting for page flip completion
infinitely.
And clears exynos_crtc->pending_flip in exynos_drm_crtc
This patch adds relevant to exynos5410 compatible
for exynos5410 / 5420 / 5440 SoCs support.
Signed-off-by: YoungJun Cho
Acked-by: Inki Dae
Acked-by: Kyungmin Park
---
Documentation/devicetree/bindings/video/exynos_dsim.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a
Hi Lee, Pekon,
A few additions/corrections to Pekon's comments.
On Thu, Jul 03, 2014 at 09:09:27AM +, Pekon Gupta wrote:
> >From: Brian Norris [mailto:computersforpe...@gmail.com]
> >On Wed, May 28, 2014 at 10:20:05AM +0100, Lee Jones wrote:
> >> diff --git a/arch/arm/boot/dts/stih41x-b2020.d
On Tue, Jul 01, 2014 at 07:43:28PM +0100, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space
> and instead use a range of CPU addresses that map to bus addresses. For
> some architectures these ranges will be expressed by OF bindings
> in a device tree file.
>
>
Hi Boris,
On Thu, Jul 03, 2014 at 10:05:22AM +0200, Boris BREZILLON wrote:
> On Wed, 2 Jul 2014 17:22:37 -0700 Brian Norris
> wrote:
> > On Wed, May 28, 2014 at 10:20:05AM +0100, Lee Jones wrote:
> > > +
> > > + nand_timing0: nand-timing {
> > > + sig-setup = <10>;
> > > +
On 07/01/14 20:59, Tushar Behera wrote:
On 06/27/2014 08:18 PM, Kevin Hilman wrote:
On Fri, Jun 27, 2014 at 7:18 AM, Kevin Hilman wrote:
On Thu, Jun 26, 2014 at 8:38 PM, Tushar Behera wrote:
Would you please provide me the environment setting of your u-boot?
U-boot environment on my board h
On Tue, Jul 01, 2014 at 07:43:27PM +0100, Liviu Dudau wrote:
> This is a useful function and we should make it visible outside the
> generic PCI code. Export it as a GPL symbol.
>
> Signed-off-by: Liviu Dudau
> Tested-by: Tanmay Inamdar
> ---
> drivers/pci/host-bridge.c | 3 ++-
> 1 file change
On Mon, Jul 07, 2014 at 11:26:18PM +0200, Linus Walleij wrote:
...
> > There was another reason for this as well, part of the gpio code I read
> > was confusing me. So I look through the other gpio documentations and
> > found an example that did this as well.
> >
> > int of_gpio_simple_xlate(struc
On 16:52 Thu 03 Jul , Maxime Ripard wrote:
> Hi,
>
> On Thu, Jul 03, 2014 at 10:29:58PM +0800, Jean-Christophe PLAGNIOL-VILLARD
> wrote:
> > no do this at SoC level
>
> Since it has to be done at init_machine, I don't see any other easy
> way to do this at the SoC level.
>
> What is your su
On Mon, 2014-07-07 at 14:06 +0530, Priyanka Jain wrote:
> Signed-off-by: Priyanka Jain
> ---
> .../devicetree/bindings/powerpc/fsl/board.txt | 17 -
> 1 files changed, 16 insertions(+), 1 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
On Fri, 2014-07-04 at 10:03 +0530, Priyanka Jain wrote:
> Some Freescale boards like T1040RDB have on board CPLD connected on
> the IFC bus. Add binding for this in board.txt file
>
> Signed-off-by: Priyanka Jain
> ---
> Changes for v2:
> convert board name to lower-case based on Scott's suggest
On Thu, 2014-07-03 at 23:08 -0500, Jain Priyanka-B32167 wrote:
>
> > -Original Message-
> > From: Wood Scott-B07421
> > Sent: Friday, July 04, 2014 3:40 AM
> > To: Jain Priyanka-B32167
> > Cc: devicetree@vger.kernel.org; linuxppc-...@lists.ozlabs.org; linux-
> > s...@vger.kernel.org; linux
On Mon, Jul 7, 2014 at 8:52 PM, Feng Kan wrote:
> On Fri, Jul 4, 2014 at 2:28 PM, Linus Walleij
> wrote:
>> I don't get this either. The only reason would be that this cell
>> should contain flags (such as open collector) the code for using
>> it being inplemented later.
>
> Yes, open drain con
On Monday 07 July 2014, Liviu Dudau wrote:
> On Sat, Jul 05, 2014 at 09:46:09PM +0100, Arnd Bergmann wrote:
> > On Saturday 05 July 2014 14:25:52 Rob Herring wrote:
> > > On Tue, Jul 1, 2014 at 1:43 PM, Liviu Dudau wrote:
> > > > The ranges property for a host bridge controller in DT describes
> >
Hello.
On 06/24/2014 10:22 PM, Arnd Bergmann wrote:
Here's the set of 3 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-v3.16-rc2-20140623' tag. Here we add PCI USB device tree support
for the R8A7791-based Koelsch and Henninger boards. As the 'pci-rcar-gen2'
driver device
Hi,
On Wed, Jul 2, 2014 at 10:19 PM, Andreas Färber wrote:
> With these 10 patches applied on top of my dt on top of kgene's tree,
> the last U-Boot screen stays visible for ~50 seconds, then the screen
> goes blank, and I can ssh in some time later.
> If I comment out the dp-controller node agai
Andreas,
On Fri, Jul 4, 2014 at 6:06 AM, Andreas Färber wrote:
>> Doug can help you in adding changes required for tps65090.
>
> Hm, Doug had pointed out an issue with tps65090 in my v1, so I dropped
> it: https://patchwork.kernel.org/patch/4397321/
tps65090 on Spring is nowhere near obvious due
On 11:06 Fri 04 Jul , Maxime Ripard wrote:
> On Fri, Jul 04, 2014 at 09:14:43AM +0200, Boris BREZILLON wrote:
> > On Fri, 4 Jul 2014 11:08:20 +0800
> > Jean-Christophe PLAGNIOL-VILLARD wrote:
> >
> > >
> > > On Jul 3, 2014, at 10:59 PM, Maxime Ripard
> > > wrote:
> > >
> > > > On Thu, Jul
On Fri, Jul 4, 2014 at 2:28 PM, Linus Walleij wrote:
> On Mon, Jun 30, 2014 at 2:53 PM, Mark Rutland wrote:
>> On Thu, Jun 26, 2014 at 11:59:46PM +0100, Feng Kan wrote:
>
>>> +- #gpio-cells: Should be two.
>>> + - first cell is the pin number
>>> + - second cell is used to specify optiona
Any word from the devicetree folks?
On Sun, Jun 29, 2014 at 04:16:58PM +0200, Hans de Goede wrote:
> From: Arend van Spriel
>
> The Broadcom bcm43xx sdio devices are fullmac devices that may be
> integrated in ARM platforms. Currently, the brcmfmac driver for
> these devices support use of platf
On Mon, 7 Jul 2014, Andre Heider wrote:
> On Sun, Jun 29, 2014 at 06:21:34PM +0200, Andre Heider wrote:
> >
> > this series adds PRUv2 support to uio_pruss through devicetree, makes the
> > device usable on am33xx and enables it on beaglebone black.
> > Inspired by old patches from Matt Porter fo
On Mon, 2014-07-07 at 04:45PM +0200, Linus Walleij wrote:
> On Wed, Jun 18, 2014 at 1:39 PM, Harini Katakam wrote:
>
> > From: Harini Katakam
> >
> > Add support for GPIO controller used by Xilinx Zynq.
> >
> > Signed-off-by: Harini Katakam
> > Signed-off-by: Soren Brinkmann
> > ---
> >
> > v2
Mark
Thanks for the review
On 07/07/2014 03:08 AM, Mark Brown wrote:
> On Thu, Jul 03, 2014 at 11:24:35AM -0500, Dan Murphy wrote:
>
>> +static int tas2552_power(struct tas2552_data *data, u8 power)
>> +{
>> +int ret = 0;
>> +
>> +mutex_lock(&data->mutex);
>> +
>> +if (power) {
>>
On Mon, 2014-07-07 at 04:53PM +0200, Linus Walleij wrote:
> On Wed, Jun 18, 2014 at 1:39 PM, Harini Katakam wrote:
>
> > From: Harini Katakam
> >
> > Add gpio-zynq bindings documentation.
> >
> > Signed-off-by: Harini Katakam
> > Signed-off-by: Soren Brinkmann
> > ---
> >
> > v2 changes:
> > I
This patch exports the function ahci_qc_issue and ahci_start_fis_rx.
The subsequent patches will make use of them.
Signed-off-by: Loc Ho
Signed-off-by: Suman Tripathi
---
drivers/ata/ahci.h| 2 ++
drivers/ata/libahci.c | 7 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --gi
This patch fixes the dma state machine lockup due to the processing
of IDENTIFY DEVICE PIO mode command. The X-Gene AHCI controller
has an errata in which it cannot clear the BSY bit after the PIO setup
FIS. The dma state machine enters CMFatalErrorUpdate state and locks
up. This patch also removes
This patch addresses the dma state machine lockup for APM X-Gene SoC.
Signed-off-by: Loc Ho
Signed-off-by: Suman Tripathi
---
Suman Tripathi (2):
libahci: Export some of the libahci functions.
ata: Fix the dma state machine lockup for the IDENTIFY DEVICE PIO mode
command.
drivers/ata/
On Mon, Jul 7, 2014 at 8:12 AM, Linus Walleij wrote:
> On Sat, Jun 21, 2014 at 9:22 AM, Alexandre Courbot wrote:
>
>>> I have added Linus Walleij and Alexandre Courbot, the maintainers of
>>> gpio. Let's see if they can point us in a direction.
>>
>> I agree it would be nice if the debounce value
On 07/07/2014 12:11 AM, Mohit KUMAR DCG wrote:
Hello Murali,
-Original Message-
From: Murali Karicheri [mailto:m-kariche...@ti.com]
Sent: Tuesday, July 01, 2014 3:15 AM
To: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org;
devicetree@vger.kernel.org
Cc: Murali Karicheri; Santosh
On 07/07/2014 12:17 AM, Mohit KUMAR DCG wrote:
Hello Murali,
-Original Message-
From: Murali Karicheri [mailto:m-kariche...@ti.com]
Sent: Tuesday, July 01, 2014 3:15 AM
To: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org;
devicetree@vger.kernel.org
Cc: Murali Karicheri; Santosh
Define alternative pin muxing for the LCDC pins.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 50 ++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi
b/arch/arm/boot/dts/sama5d3_lcd.dtsi
index 2186b8
Hello,
Sorry for the noise, but I forgot to add the LAKML in Cc.
This patch series adds support for Atmel HLCDC (HLCD Controller) available
on some Atmel SoCs (i.e. the sama5d3 family).
The first two versions of this series didn't receive any reviews from DRM
maintainers or experienced DRM devel
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
This driver add support for a PWM chip exposing a single PWM device (which
will most likely be used to drive a backlight device).
Signed-off-by: Boris BREZILLON
---
The HLCDC (HLCD Controller) IP supports 4 different output mode (RGB444,
RGB565, RGB666 and RGB888) and the pin muxing will depend on the chosen
RGB mode.
Split pin definitions to be able to set pin config according to the
selected mode.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
The DT bindings used for this PWM device is following the default 3 cells
bindings described in Documentation/devicetree/bindings/pwm/pwm.txt.
Signed-off-by: Boris BR
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
The MFD device provides a regmap and several clocks (those connected
to this hardware block) to its subdevices.
Add LCD panel related nodes (backlight, regulators and panel) to sama5d3
Display Module dtsi.
Reference LCD pin muxing used by sama5d3xek boards.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3xdm.dtsi | 43 +++
1 file changed, 43 insertions(+)
Enable LCD related nodes and reference panel node in the hlcdc (HLCD
Controller) node.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d31ek.dts | 24
arch/arm/boot/dts/sama5d33ek.dts | 24
arch/arm/boot/dts/sama5d34ek.dts | 24
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
This patch adds documentation for atmel-hlcdc DT bindings.
Signed-off-by: Boris BREZILLON
---
.../devicetree/b
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family) provides a display
controller device.
The HLCDC block provides a single RGB output port, and only supports LCD
panels connection to LCD panels for now.
The atmel,panel propert
Define the HLCDC (HLCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36) in sama5d3 dtsi file.
Signed-off-by: Boris BREZILLON
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boo
JPEG IP on Exynos3250 SoC requires enabling two clock
gates for its operation. This patch documents this
requirement.
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicetree@vger.kernel.org
-
Signed-off-by: Jacek Anaszewski
Signed-off-by: Kyungmin Park
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot
Hi Linus,
On Mon, 2014-07-07 at 04:51PM +0200, Linus Walleij wrote:
> On Wed, Jun 18, 2014 at 5:36 PM, Sören Brinkmann
> wrote:
>
> > I did some of the changes for this v2 and a few things are not clear to
> > me.
> >
> > The first is, how is userspace supposed to find the correct offset for a
>
On Thu, Jun 26, 2014 at 3:44 PM, Rickard Strandqvist
wrote:
> Remove variable that are never used
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Patch applied with Patrice's ACK.
Yours,
Linus Walleij
--
To unsubscribe from this l
On Thu, Jun 26, 2014 at 6:58 PM, Rickard Strandqvist
wrote:
> %d in format string used, but the type is unsigned int
>
> This was found using a static code analysis program called cppcheck
>
> Signed-off-by: Rickard Strandqvist
Patch applied.
Yours,
Linus Walleij
--
To unsubscribe from this li
On Thu, Jun 26, 2014 at 3:43 PM, Rickard Strandqvist
wrote:
> Remove variable that are never used
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Makes sense.
Patch applied unless Tony or Haojian has some better error handling coo
On Thu, Jun 26, 2014 at 3:41 PM, Rickard Strandqvist
wrote:
> Remove variable that are never used
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
(...)
> - int ret, val, num_conf = 0;
> + int val, num_conf = 0;
>
> -
On Thu, Jun 26, 2014 at 1:32 PM, Rickard Strandqvist
wrote:
> Remove checking if a unsigned is less than zero
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Patch applied with the ACKs. Thanks!
Yours,
Linus Walleij
--
To unsubscr
On Thu, Jun 26, 2014 at 1:29 PM, Rickard Strandqvist
wrote:
> Remove checking if a unsigned is less than zero
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Patch applied. Thanks!
Yours,
Linus Walleij
--
To unsubscribe from this
On Thu, Jun 26, 2014 at 1:28 PM, Rickard Strandqvist
wrote:
> Remove checking if a unsigned is less than zero
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Patch applied. Thanks!
Yours,
Linus Walleij
--
To unsubscribe from this
On Thu, Jun 26, 2014 at 1:26 PM, Rickard Strandqvist
wrote:
> Remove checking if a unsigned is less than zero
>
> This was found using a static code analysis program called cppcheck.
>
> Signed-off-by: Rickard Strandqvist
Patch applied. Thanks!
Yours,
Linus Walleij
--
To unsubscribe from this
Hi Arnd,
Any update on status of this patchset? Is it OK for it to go through
arm-soc tree or should it be splitted into separate parts which would
go through pci/phy/arm-soc trees?
[ The patchset applies fine to next-20140707 after fixing trivial
reject in drivers/pci/host/Makefile in patch
Hi Linux,
On Mon, Jul 07, 2014 at 04:51:56PM +0200, Linus Walleij wrote:
> On Wed, Jun 18, 2014 at 5:36 PM, Sören Brinkmann
> wrote:
> > The first is, how is userspace supposed to find the correct offset for a
> > GPIO pin.
>
> The sysfs interface to GPIO is *NOT* *GOOD* this is universally
> a
This adds a DT binding documentation for the MT6589 SoC from Mediatek.
Signed-off-by: Matthias Brugger
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/mediatek.txt |8
1 file changed, 8 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mediatek
A call to of_iomap does not request the memory region.
This patch adds the function of_io_request_and_map which requests
the memory region before mapping it.
Signed-off-by: Matthias Brugger
Suggested-by: Thomas Gleixner
Suggested-by: Rob Herring
---
drivers/of/address.c | 36 ++
This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.
The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.
Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock
This adds a generic devicetree board file and a dtsi for boards
based on MT6589 SoCs from Mediatek.
Apart from the generic parts (gic, clocks) the only component
currently supported are the timers.
Signed-off-by: Matthias Brugger
---
arch/arm/Kconfig |2 +
arch/arm/Makefile
Signed-off-by: Matthias Brugger
Acked-by: Rob Herring
---
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 4d7f375..d819d8
Add binding documentation for the General Porpose Timer driver of
the Mediatek SoCs.
Signed-off-by: Matthias Brugger
Acked-by: Sören Brinkmann
Acked-by: Rob Herring
---
.../bindings/timer/mediatek,mtk-timer.txt | 17 +
1 file changed, 17 insertions(+)
create mode 10
The Aquaris5 is a mobile phone based on the MT6589 SoC.
Signed-off-by: Matthias Brugger
---
arch/arm/boot/dts/mt6589-aquaris5.dts | 25 +
1 file changed, 25 insertions(+)
create mode 100644 arch/arm/boot/dts/mt6589-aquaris5.dts
diff --git a/arch/arm/boot/dts/mt6589-aq
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