Hi,
Sorry for the late reply.
On Tue, 09 Dec 2014 08:57:17 +
Lee Jones wrote:
> On Mon, 08 Dec 2014, Inha Song wrote:
>
> > Some boards need to set the OUTn_MONO register to configurates
> > the output signal path as a mono differential output. This
> > wlf,out-mono property is optional. If
Dear Myungjoo,
Thanks for your review.
On 12/18/2014 03:24 PM, MyungJoo Ham wrote:
> Hi Chanwoo,
>
> I love the idea and I now have a little mechanical issues in your code.
>
>> ---
>> drivers/devfreq/Kconfig | 2 +
>> drivers/devfreq/Makefile| 5 +-
>> drivers/devfreq/devf
Signed-off-by: Liu Ying
---
v1->v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 78efebb..3cee528 100644
---
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
--
This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
b/include/linux/mfd
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
di
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying
---
v1->v2:
* Address almost all comments from Thierry Reding.
* Remove several DT properties as they can be implied by the compatible string.
* Add the HIMAX/himax prefixes to the driver's Kconfig name and drive
This patch adds i.MX MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying
---
v1->v2:
* Address almost all comments from Thierry Reding and Russell.
* Update the DT documentation to remove the display-timings node
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying
---
v1->v2:
* To address Thierry Reding's comments, remove several unnecessary
p
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI peripher
Signed-off-by: Liu Ying
---
v1->v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/incl
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/configs/imx_v6_v7_defconfig | 15 +++
1 file changed, 7 i
This patch adds support for MIPI DSI host controller.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the MIPI DSI host controller driver
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/con
This patch adds support for Himax HX8369A panel.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the Himax HX8369A panel driver
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/configs/imx_v
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying
---
v1->v2:
* None.
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 96bf2a0..bfc39fd 100644
--- a/arch/a
Signed-off-by: Liu Ying
---
v1->v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 3cee528..8257f3a 100644
---
Hi,
This series addressed almost all comments from Thierry Redding and Russell
on v1.
This series adds support for i.MX MIPI DSI DRM driver.
Currently, the MIPI DSI driver only supports the burst with sync pulse mode.
This series also includes a DRM panel driver for the Truly TFT480800-16-E pane
Hi Chanwoo,
I love the idea and I now have a little mechanical issues in your code.
> ---
> drivers/devfreq/Kconfig | 2 +
> drivers/devfreq/Makefile| 5 +-
> drivers/devfreq/devfreq-event.c | 449
>
> drivers/devfreq/event/Makefile
On Thu, Dec 18, 2014 at 03:09:21PM +0900, Jingoo Han wrote:
> On Thursday, December 18, 2014 2:48 PM, Gyungoh Yoo wrote:
> >
> > From: Gyungoh Yoo
> >
> > Signed-off-by: Gyungoh Yoo
>
> Please add the following 'Acked-by's when you send this patch
> next time.
>
> Acked-by: Jingoo Han
> Acke
On Thursday, December 18, 2014 2:48 PM, Gyungoh Yoo wrote:
>
> From: Gyungoh Yoo
>
> Signed-off-by: Gyungoh Yoo
Please add the following 'Acked-by's when you send this patch
next time.
Acked-by: Jingoo Han
Acked-by: Bryan Wu
Best regards,
Jingoo Han
> ---
> Changes v10:
> Removed trivial
On Wednesday, December 17, 2014 7:35 PM, Gabriel FERNANDEZ wrote:
>
> sti pcie is built around a Synopsis Designware PCIe IP.
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Gabriel Fernandez
> ---
> drivers/pci/host/Kconfig | 5 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
---
Changes v10:
Removed trivial get_brightness implementations
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for GPIO
Changes v7:
Modified licensing text t
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Made up the example for backlight DT
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Changed DT for regulator : 'lout' node should be defined under 'regulator'
Removed compatible string
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Add SKY81452 to the Trivial Devices list
Documentation/devicetre
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Bryan Wu
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for GPIO
Made up the example for backlight DT
Changes v7:
Nothing
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added vendor prefix for Skyworks Solutions, Inc.
Documentation/d
From: Gyungoh Yoo
This patch set includes regulator and backlight driver for SKY81452.
Also it includes documents for device tree and module.
sky81452-regulator was already applied. So this series doesn't
include it.
v10:
Removed trivial get_brightness implementations for sky81452-backlight
v9:
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Lee Jones
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Modified licensing text to GPLv2
Changes v6:
Added new line character at the end of line of dev_err()
Changes v5:
Move sky81452-backlight.h to inclu
On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> > But in these SoCs PCIe IP doesn't support IO.
Hi Gabriel,
I cannot understand how ST sti SoCs PCIe IP do
Hi,
On Thu, Dec 18, 2014 at 1:18 AM, Hans de Goede wrote:
> On sun6i the cir block is attached to the reset controller, add support
> for de-asserting the reset if a reset controller is specified in dt.
>
> Signed-off-by: Hans de Goede
> Acked-by: Mauro Carvalho Chehab
> Acked-by: Maxime Ripard
On Tue, Dec 16, 2014 at 05:17:57PM -0800, Brian Norris wrote:
> If there are no more concrete objections, I'll apply this patch.
Applied to l2-mtd.git/next.
--
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More majordomo
Hi Russell,
On 12/17/2014 06:40 PM, Russell King - ARM Linux wrote:
On Wed, Dec 17, 2014 at 05:44:33PM +0800, Liu Ying wrote:
Hi Thierry,
Sorry for the late response.
I tried to address almost all your comments locally first.
More feedback below.
On 12/10/2014 09:16 PM, Thierry Reding wrote:
Add the document for ov2640 dt.
Cc: devicetree@vger.kernel.org
Signed-off-by: Josh Wu
---
v3 -> v4:
1. remove aggsigned-clocks as it's general.
2. refine the explation.
v2 -> v3:
1. fix incorrect description.
2. Add assigned-clocks & assigned-clock-rates.
3. resetb pin should be ACTIVE
The master clock (xvclk) is mandatory. It's a common clock framework clock.
It can make sensor output a pixel clock to the camera interface.
Cc: devicetree@vger.kernel.org
Signed-off-by: Josh Wu
Acked-by: Laurent Pinchart
---
v3 -> v4:
1. Add Laurent's acked by.
v2 -> v3:
1. should return P
Add device tree support for ov2640.
Cc: devicetree@vger.kernel.org
Signed-off-by: Josh Wu
Acked-by: Laurent Pinchart
---
v3 -> v4:
1.modify the code comment.
2. Add Laurent's acked by.
v2 -> v3:
1. fix gpiod usage.
2. refine the ov2640_probe() function.
v1 -> v2:
1. use gpiod APIs.
On Wed, 2014-12-17 at 17:59 -0800, Jonathan Richardson wrote:
> Add initial version of the Broadcom touchscreen driver.
trivia:
> diff --git a/drivers/input/touchscreen/bcm_iproc_tsc.c
> b/drivers/input/touchscreen/bcm_iproc_tsc.c
> +/* Bit values for REGCTL2 */
> +#define TS_CONTROLLER_EN_BIT
On Thu, Dec 18, 2014 at 1:17 AM, Dinh Nguyen wrote:
> +MODULE_DEVICE_TABLE(of, altera_mbox_match);
> +
> +static struct platform_driver altera_mbox_driver = {
> +.probe = altera_mbox_probe,
> +.remove = altera_mbox_remove,
> +.driver = {
> +.nam
This patchset contains initial support for the touchscreen on the Broadcom
iProc family of SoCs. This driver has been validated with Cygnus and is expected
to work on other iProc family of SoCs that use the same touchscreen controller.
Jonathan Richardson (2):
Input: touchscreen-iproc: Add Broad
Documents the touchscreen device tree binding for Broadcom iProc family
of SoCs.
Reviewed-by: Scott Branden
Tested-by: Scott Branden
Signed-off-by: Jonathan Richardson
---
.../input/touchscreen/brcm,iproc-touchscreen.txt | 70
1 file changed, 70 insertions(+)
create m
Add initial version of the Broadcom touchscreen driver.
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
Tested-by: Scott Branden
Signed-off-by: Jonathan Richardson
---
drivers/input/touchscreen/Kconfig | 11 +
drivers/input/touchscreen/Makefile|1 +
drivers/input/touchsc
On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
> ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> But in these SoCs PCIe IP doesn't support IO.
>
> To support this, add setup_bus() to pcie_host_ops.
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Gabriel Fernandez
On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote:
> sti pcie is built around a Synopsis Designware PCIe IP.
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Gabriel Fernandez
> ---
> drivers/pci/host/Kconfig | 5 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-
On Wednesday 17 December 2014 11:34:43 Gabriel FERNANDEZ wrote:
> sti pcie is built around a Synopsis Designware PCIe IP.
>
> Signed-off-by: Fabrice Gasnier
> Signed-off-by: Gabriel Fernandez
> ---
> Documentation/devicetree/bindings/pci/st-pcie.txt | 53
> +++
> 1 file cha
On Wed 2014-12-17 09:32:16, Greg KH wrote:
> On Wed, Dec 17, 2014 at 10:54:49AM -0600, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > Enable FPGA manager for Altera socfpga.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_SOCFPGA/
> > --
Hello.
On 12/17/2014 03:31 AM, Chanwoo Choi wrote:
MAX3355E chip integrates a charge pump and comparators to enable a system with
an integrated USB OTG dual-role transceiver to function as a USB OTG dual-role
device. In addition to sensing/controlling Vbus, the chip also passes thru the
ID sign
Hi Wolfram,
Wolfram Sang writes:
> On Tue, Dec 16, 2014 at 10:19:53PM +0100, Arnaud Ebalard wrote:
>>
>> This patch fixes I2C trivial-devices.txt DT documentation file to
>> reference isil (NASDAQ symbol and the most used prefix inside the
>> kernel) for Intersil.
>>
>> It reverts 7c75c1d5e72b
On Wednesday 17 December 2014 16:45:24 Lee Jones wrote:
> +- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc"
> + "st,stih415-lpc" "st,stid127-lpc"
> +- reg : LPC registers base address + size
> +- interrupts: LPC interrupt line number an
On Wednesday 17 December 2014 21:49:44 Laszlo Ersek wrote:
> The qemu patchset has been turned upside down on qemu-devel during
> review (many thanks for that!); one outcome is that now both the
> selector and the data registers are big endian. This series has been
> updated accordingly.
>
>
Ack
The QEMU open source machine emulator and virtualizer presents firmware
and operating systems running in virtual machines ("guests") with purely
virtual hardware (ie. hardware that has never existed in physical form).
Since QEMU exposes some of these devices in a DTB, it makes sense to
define "qemu
Peter Maydell suggested that we describe new devices / DTB nodes in the
kernel Documentation tree that we expose to arm "virt" guests in QEMU.
Although the kernel is not required to access the fw_cfg interface,
"Documentation/devicetree/bindings/arm" is probably the best central spot
to keep the f
The qemu patchset has been turned upside down on qemu-devel during
review (many thanks for that!); one outcome is that now both the
selector and the data registers are big endian. This series has been
updated accordingly.
Thanks
Laszlo
Laszlo Ersek (2):
devicetree: document the "qemu" and "virt
On Wed, 17 Dec 2014, Michal Simek wrote:
> On 12/17/2014 06:32 PM, Greg KH wrote:
> > On Wed, Dec 17, 2014 at 10:54:49AM -0600, at...@opensource.altera.com wrote:
> >> From: Alan Tull
> >>
> >> Enable FPGA manager for Altera socfpga.
> >>
> >> Signed-off-by: Alan Tull
> >> ---
> >> v5: s/CONFIG_
Move the Ethernet node from the ad-hoc lbsc node to the BSC node,
as its connected to the Bus State Controller. This allows the system to
know the right position of the Ethernet node in the clock and PM domain
hierarchy, and manage the clock and PM domain appropriately.
Signed-off-by: Geert Uytte
Add a driver for transparent busses that don't need a real driver (think
"simple-bus"), where the bus controller is part of a PM domain, or under
the control of a functional clock. Typically, the bus controller's
PM domain and/or clock must be enabled for child devices connected to
the bus (either
Add a node for the Bus State Controller (BSC) on r8a73a4, to which
multiple external devices can be connected.
The BSC is driven by the ZB clock, and located in PM domain C4.
A reference to the latter will be added later.
Signed-off-by: Geert Uytterhoeven
---
Untested
v2:
- New
---
arch/arm/
Signed-off-by: Geert Uytterhoeven
---
v2:
- New
---
drivers/bus/Makefile | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 2973c18cbcc27816..3cfaf2c7f25ac4f0 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Ma
Hi all,
The Renesas Bus State Controller (BSC) provides an external bus for
connecting multiple external devices to an SoC, driving several chip
select lines, for e.g. NOR FLASH, Ethernet and USB.
On the kzm9g and ape6evm development boards, an smsc9220 Ethernet
controller is connnected to
Add a node for the Bus State Controller (BSC) on sh73a0, to which
multiple external devices can be connected.
The BSC is driven by the ZB clock, and located in PM domain A4S.
A reference to the latter will be added later.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Postpone power-domains
---
Signed-off-by: Geert Uytterhoeven
---
v2:
- New
---
.../devicetree/bindings/bus/simple-pm-bus.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/simple-pm-bus.txt
diff --git a/Documentation/devicetree/bindings/bus/si
Signed-off-by: Geert Uytterhoeven
---
v2:
- New
---
drivers/bus/Kconfig | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b99729e368608bda..626960819e6df16c 100644
--- a/drivers/bus/
Move the Ethernet node from the root of the device tree to the BSC node,
as its connected to the Bus State Controller. This allows the system to
know the right position of the Ethernet node in the clock and PM domain
hierarchy, and manage the clock and PM domain appropriately.
Also rename the nod
On Wed, Dec 17, 2014 at 09:32:16AM -0800, Greg KH wrote:
> On Wed, Dec 17, 2014 at 10:54:49AM -0600, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > Enable FPGA manager for Altera socfpga.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_S
On 12/17/2014 06:32 PM, Greg KH wrote:
> On Wed, Dec 17, 2014 at 10:54:49AM -0600, at...@opensource.altera.com wrote:
>> From: Alan Tull
>>
>> Enable FPGA manager for Altera socfpga.
>>
>> Signed-off-by: Alan Tull
>> ---
>> v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_SOCFPGA/
>> ---
>> arch/arm
Remove the unnecessary 'of_can_translate_address',
which is already removed in commit
d9c6866be8a145e32da616d8dcbae806032d75b5 ("of: kill off
of_can_translate_address").
Signed-off-by: Tsung-Han Lin
---
drivers/staging/board/board.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff -
On Wed, Dec 17 2014 at 11:14 -0700, Kevin Hilman wrote:
Lina Iyer writes:
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v13:
- Ret
Lina Iyer writes:
> Dependent patchsets -
> https://lkml.org/lkml/2014/8/4/767
> http://www.spinics.net/lists/linux-arm-msm/msg10799.html
> http://www.spinics.net/lists/linux-arm-msm/msg10795.html
>
> Changes since v13:
> - Return values for idle states propagated back to
On Wed, Dec 17, 2014 at 04:45:25PM +, Lee Jones wrote:
> Signed-off-by: David Paris
> Signed-off-by: Lee Jones
Hi Lee and David,
I still have a couple of comments below. Sorry I didn't catch those earlier.
Thanks,
Guenter
> ---
> drivers/watchdog/Kconfig | 13 ++
> drivers/watchdog/Mak
On Wed, Dec 17, 2014 at 10:54:49AM -0600, at...@opensource.altera.com wrote:
> From: Alan Tull
>
> Enable FPGA manager for Altera socfpga.
>
> Signed-off-by: Alan Tull
> ---
> v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_SOCFPGA/
> ---
> arch/arm/configs/socfpga_defconfig |4
> 1 file
Hello.
On 12/17/2014 08:21 AM, Suman Tripathi wrote:
This patch addresses the issue with ATA_CMD_PACKET pio mode
command for enumeration and device detection with ATAPI devices.It is the
same issue as in patch
Ugh, HTML... Please stick to plain text when posting to the
'vger.k
On Wednesday, December 17, 2014 03:43:31 PM Hans de Goede wrote:
> + /*
> +* lradc supports only one keypress at a time, release does not give
> +* any info as to which key was released, so we cache the keycode.
> +*/
> + if ((ints & CHAN0_KEYDOWN_IRQ) && lradc->
This patch addresses the issue with ATA_CMD_PACKET pio mode
command for enumeration and device detection with ATAPI devices.It is the
same issue as in patch
www.spinics.net/lists/linux-ide/msg49092.html
Signed-off-by: Suman Tripathi
---
drivers/ata/ahci_xgene.c | 12 +++-
1 file changed
This patch fixes the big endian mode issue with function
xgene_ahci_read_id.
Signed-off-by: Suman Tripathi
---
drivers/ata/ahci_xgene.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index 0f8538f..0ffd3c9 100644
--- a/driv
Add an ir_clk sub-node to the prcm node.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Use allwinner,sun4i-a10-mod0-clk as compatible, rather then a prcm specific
compatible
---
arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun6
Add support for the ir-clk which is part of the sun6i SoC prcm module.
Signed-off-by: Hans de Goede
---
drivers/mfd/sun6i-prcm.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/mfd/sun6i-prcm.c b/drivers/mfd/sun6i-prcm.c
index 2f2e9f0..1911731 100644
--- a/drivers/mfd
The A31s is a stripped down version of the A31, as such it is missing some
pins and some functions on some pins.
The new pinctrl-sun6i-a31s.c this commit adds is a copy of pinctrl-sun6i-a31s.c
with the missing pins and functions removed.
Note there is no a31s specific version of pinctrl-sun6i-a31
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out.
Note it has no sdcard slot and therefore can only be fel booted.
Signed-off-by: Hans de Goede
---
Add a dtsi file for A31s based boards.
Since the A31s is the same die as the A31 in a different package, this dtsi
simply includes sun6i-a31.dtsi and then overrides the pinctrl compatible to
reflect the different package, everything else is identical.
Signed-off-by: Hans de Goede
---
Changes in
With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.
Silence the error on not finding registers in the of_clk_declare
Add pinmux settings for the ir receive pin of the A31.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 85c6365..9e9504c 100644
--- a/arch/arm/boo
Add a node for the ir receiver found on the A31.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1c1d255..85c6365 100644
--- a/arch/arm/boot
The Mele M9 has an ir receiver, enable it.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31-m9.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts
b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 3ab544f..fccf709 100644
--- a/arch/arm/boot/dts/
Add support for the larger fifo found on sun5i and sun6i, having a separate
compatible for the ir found on sun5i & sun6i also is useful if we ever want
to add ir transmit support, because the sun5i & sun6i version do not have
transmit support.
Note this commits also adds checking for the end-of-pa
So far the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case we need to differentiate later.
Signed-off-by: Hans de Goede
---
Documentation/arm/sunxi/README | 1 -
arch/arm/mach-sunxi/platsmp.c | 3 +
On sun6i the cir block is attached to the reset controller, add support
for de-asserting the reset if a reset controller is specified in dt.
Signed-off-by: Hans de Goede
Acked-by: Mauro Carvalho Chehab
Acked-by: Maxime Ripard
---
.../devicetree/bindings/media/sunxi-ir.txt | 2 ++
driv
Hi All,
Here is v2 of my patch series to add sun6i A31s and ir support.
Changes in v2:
-"pinctrl: sun6i: Add some missing functions, fix i2c3 muxing":
-Drop the changes to the muxing of i2c3 this was based on
"A31s Datasheet v1.40.pdf", but all other A31 related info puts the
While working on pinctrl for the A31s, I noticed that function 4 of
PA15 - PA18 was missing, add these.
Signed-off-by: Hans de Goede
---
Changes in v2:
-Drop the changes to the muxing of i2c3 this was based on
"A31s Datasheet v1.40.pdf", but all other A31 related info puts them at the
pins wher
On 12/16/14, 12:33 AM, Ley Foon Tan wrote:
> On Tue, Dec 16, 2014 at 4:54 AM, Suman Anna wrote:
>> Hi Ley Foon,
>>
>> On 12/12/2014 08:38 AM, Dinh Nguyen wrote:
>>>
>>>
>>> On 12/12/14, 4:04 AM, Ley Foon Tan wrote:
The Altera mailbox allows for interprocessor communication. It supports
On 12/12/14 21:03, Mark Brown wrote:
> On Thu, Dec 11, 2014 at 06:45:50PM +0100, Sylwester Nawrocki wrote:
>
>> +Optional Properties:
>>
>> - samsung,idma-addr: Internal DMA register base address of the audio
>>sub system(used in secondary sound source).
>> - pinctrl-0: Should specify pin co
From: Alan Tull
Intended for after 3.19-rc1
v5 includes changes from feedback from Michal, Steffen, Alan, Greg, and the
kbuild test robot.
The driver is under drivers/staging/fpga/
The header is now in include/linux/fpga/
The sysfs doc is in staging/fpga/Documentation/ABI/
The DT binding is in
From: Alan Tull
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move document to drivers/staging/fpga/Documentation/ABI
---
..
From: Alan Tull
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
should be sufficient for ind
From: Alan Tull
Enable FPGA manager for Altera socfpga.
Signed-off-by: Alan Tull
---
v5: s/CONFIG_FPGA_MGR_ALTERA/CONFIG_FPGA_MGR_SOCFPGA/
---
arch/arm/configs/socfpga_defconfig |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/so
From: Alan Tull
Add Altera FGPA manager to device tree.
Signed-off-by: Alan Tull
---
v5 : remove simple-bus and associated stuff
---
arch/arm/boot/dts/socfpga.dtsi |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
inde
From: Alan Tull
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
---
.../Documentation/bindings/altera-fpga-mgr.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644
d
From: Alan Tull
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull
---
v2: fpga_manager struct now contains struct device
fpga_manager_register parameters now take device
v3: skip a version to align versions
v4: move to dr
On Wed, 10 Dec 2014, Michal Simek wrote:
> On 12/09/2014 09:14 PM, at...@opensource.altera.com wrote:
> > From: Alan Tull
> >
> > Add driver to fpga manager framework to allow configuration
> > of FPGA in Altera SoC FPGA parts.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v2: fpga_manager stru
ST's Low Power Controller (LPC) controls two devices; watchdog and RTC.
Only one of the devices can be used at any one time, which is enforced
by a Device Tree property.
This driver set provides everything you need to choose one (and only
one) of the LPC devices to run per I/P block, of which ther
Signed-off-by: Lee Jones
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index e34d5c6..09b8bce 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_d
ST's Low Power Controller can currently operate in two supported modes;
Watchdog and Real Time Clock. These defines will aid engineers to easily
identify the selected mode.
Signed-off-by: Lee Jones
---
include/dt-bindings/mfd/st-lpc.h | 15 +++
1 file changed, 15 insertions(+)
crea
On current ST platforms the LPC controls a number of functions. This
patch enables support for the LPC Watchdog and LPC RTC devices on LPC1
and LPC2 respectively.
Signed-off-by: David Paris
Signed-off-by: Lee Jones
---
arch/arm/boot/dts/stih407.dtsi | 20
1 file changed, 2
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