> -Original Message-
> From: Rob Herring [mailto:robherri...@gmail.com]
> Sent: Wednesday, January 28, 2015 5:05 AM
> To: Devshatwar, Nikhil
> Cc: devicetree-compi...@vger.kernel.org; devicetree@vger.kernel.org;
> devicetree-s...@vger.kernel.org; linux-omap
> Subject: Re: [PATCH] dtc: parse
On Tue, Jan 27, 2015 at 10:57:28PM +0100, Christophe Ricard wrote:
> tpm_i2c_stm_st33 is a TIS 1.2 TPM with a core interface which can be used
> by different phy such as i2c or spi. The core part is called st33zp24 which
> is also the main part reference.
>
> include/linux/platform_data/tpm_stm_st
Hi Chunyan Zhang,
On Wed, Jan 28, 2015 at 10:47:41AM +0800, Chunyan Zhang wrote:
[...]
> +static inline void sprd_rx(struct uart_port *port)
> +{
> + struct tty_port *tty = &port->state->port;
> + unsigned int ch, flag, lsr, max_count = SPRD_TIMEOUT;
> +
> + while ((serial_in(port, SPR
Hi Arnd,
I added the iommus in the IOMMU AHBC patch. Anything wrong in that ?
In the next version Also I will remove the IOMMU hacks from arasan
driver
On Wed, Jan 28, 2015 at 9:48 AM, Suman Tripathi wrote:
> Hi Arnd,
>
> On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
>>
>> +
On Tue, Jan 27, 2015 at 11:26:11PM +0530, Suman Tripathi wrote:
> This patch addresses the issue with ATA_CMD_SMART pio mode
> command for enumeration and device detection with ATA devices.It is the
> same issue as in patch
>
> www.spinics.net/lists/linux-ide/msg49092.html
The link is broken. Can
On 01/27/2015 09:47 PM, Chunyan Zhang wrote:
> Add a full sc9836-uart driver for SC9836 SoC which is based on the
> spreadtrum sharkl64 platform.
> This driver also support earlycon.
Reviewed-by: Peter Hurley
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On Tue 27 Jan 14:10 PST 2015, Andy Gross wrote:
This solution looks good, just some style things.
> diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c
[..]
> +#define MAX_GSBI 12
> +
> +#define TCSR_ADM_CRCI_BASE 0x70
> +
> +struct crci_config {
> + u32 num
Add a full sc9836-uart driver for SC9836 SoC which is based on the
spreadtrum sharkl64 platform.
This driver also support earlycon.
Originally-by: Lanqing Liu
Signed-off-by: Orson Zhai
Signed-off-by: Chunyan Zhang
Acked-by: Arnd Bergmann
---
drivers/tty/serial/Kconfig | 18 +
drivers/
Adds Spreadtrum's prefix "sprd" to vendor-prefixes file.
Adds the devicetree binding documentations for Spreadtrum's sc9836-uart
and SC9836 SoC based on the Sharkl64 Platform which is a 64-bit SoC
Platform of Spreadtrum.
Signed-off-by: Chunyan Zhang
---
Documentation/devicetree/bindings/arm/sprd
Changes from v8:
- Moved a few unuseful code lines.
Chunyan Zhang (2):
Documentation: DT: Add bindings for Spreadtrum SoC Platform
tty/serial: Add Spreadtrum sc9836-uart driver support
Documentation/devicetree/bindings/arm/sprd.txt | 11 +
.../devicetree/bindings/serial/sprd-ua
On Tue, Jan 27, 2015 at 3:00 PM, Murali Karicheri wrote:
> Add of_pci_dma_configure() to allow updating the dma configuration
> of the pci device using the configuration from DT of the parent of
> the root bridge device. Use the newly added APIs
> pci_get/put_host_bridge_device() for implementing
On Tue, Jan 27, 2015 at 3:00 PM, Murali Karicheri wrote:
> Fix the dma-range size when the DT attribute is missing. i.e set size to
> dev->coherent_dma_mask + 1 instead of dev->coherent_dma_mask. Also add
> code to check invalid values of size configured in DT and log error.
>
> Cc: Joerg Roedel
On Tue, Jan 27, 2015 at 2:59 PM, Murali Karicheri wrote:
> Function of_iommu_configure() is called from of_dma_configure() to
> setup iommu ops using DT property. This API is currently used for
> platform devices for which DMA configuration (including iommu ops)
> may come from device's parent. To
Hi Roger,
On 01/28/2015 12:38 AM, Roger Quadros wrote:
> Chanwoo,
>
> On 27/01/15 03:54, Chanwoo Choi wrote:
>> Hi Roger,
>>
>> On 01/27/2015 01:27 AM, Roger Quadros wrote:
>>> Hi Chanwoo,
>>>
>>> All your comments are valid. Need some clarification on one comment.
>>>
>>> On 26/01/15 15:56, Chan
On Sat, 17.01.15 17:03, Zbigniew Jędrzejewski-Szmek (zbys...@in.waw.pl) wrote:
> On Sat, Jan 17, 2015 at 09:44:00AM +0100, Hans de Goede wrote:
> > We would like
> > udev to emit a signal (ABI to be discussed) when it is done
> > trying to load modules for everything which was already enumerated
>
Quoting Lee Jones (2015-01-26 03:14:00)
> Signed-off-by: Lee Jones
> ---
> .../devicetree/bindings/clock/st/st,clk-domain.txt | 34
> ++
> 1 file changed, 34 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/st/st,clk-domain.txt
>
> diff --git a/
Hi Christophe,
On Tue, Jan 27, 2015 at 11:16:32PM +0100, christophe.ricard wrote:
> The main reason for making an st21nfcb_hci_core is because the hci network
> initialization procedure is proprietary.
> It is almost using only NCI standard commands but some id's and commands
> could be proprietar
Hi Thomas,
2015-01-26 16:34 GMT+01:00 Thomas Gleixner :
> On Mon, 26 Jan 2015, Matthias Brugger wrote:
>> Applied to v3.20-next/arm64.
>> >
>> > Yingjoe Chen (1):
>> > irqchip: mtk-sysirq: Get irq number from register resource size
>
> I just queued that irqchip patch in irq/core
What I wa
On Thu, Jan 8, 2015 at 8:12 AM, Nikhil Devshatwar wrote:
> Current device tree compiler allows to define multiple labels when defining
> the device node the first time. Typically device nodes are defined in
> DTSI files. Now these nodes can be overriden for updating some of the
> properties. Typic
On Sun, Jan 25, 2015 at 08:08:55PM +0200, Baruch Siach wrote:
> Hi ARM SoC maintainers,
>
> On Wed, Jan 14, 2015 at 10:40:29AM +0200, Baruch Siach wrote:
> > This series adds initial support for the Conexant CX92755 SoC. The CX92755
> > is
> > one of the Digicolor series of SoCs, all sharing many
On Wed, Jan 14, 2015 at 10:40:33AM +0200, Baruch Siach wrote:
> Of the Digicolor SoCs series only CX92755 is currently supported.
>
> Acked-by: Arnd Bergmann
> Signed-off-by: Baruch Siach
> ---
> Documentation/devicetree/bindings/arm/digicolor.txt | 6 ++
> 1 file changed, 6 insertions(+)
>
On Wed, Jan 14, 2015 at 10:40:31AM +0200, Baruch Siach wrote:
> Use the USART peripheral as UART for low level debug. Only the UA0 port is
> currently supported.
>
> Acked-by: Arnd Bergmann
> Signed-off-by: Baruch Siach
> ---
> arch/arm/Kconfig.debug | 12 ++--
> arch/arm/in
On Wed, Jan 14, 2015 at 10:40:30AM +0200, Baruch Siach wrote:
> Add initial support for the Conexant CX92755 SoC. The CX92755 is one of the
> Digicolor series of SoCs, all sharing many of the same peripherals. The code
> was tested on the CX92755 evaluation kit, AKA Equinox.
>
> Acked-by: Arnd Ber
Hi,
On Wed, Jan 14, 2015 at 10:40:32AM +0200, Baruch Siach wrote:
> cx92755.dtsi describes CX92755 on chip peripherals. conexant_equinox.dts
> describes the Equinox evaluation board for the CX92755 SoC.
>
> Acked-by: Arnd Bergmann
> Signed-off-by: Baruch Siach
> ---
> arch/arm/boot/dts/Makefil
On Tuesday, January 27, 2015 at 11:23:33 PM, Rickard Strandqvist wrote:
> Wrong type in printf format string, requires 'int'
> but the argument type is 'unsigned int'
>
> This was found using a static code analysis program called cppcheck
>
> Signed-off-by: Rickard Strandqvist
Makes sense, than
On Tue, Jan 27, 2015 at 01:18:10AM +0100, Christophe Ricard wrote:
> Christophe Ricard (10):
> NFC: hci: Change event_received handler gate parameter to pipe
> NFC: hci: Add pipes table to reference them with a tuple {gate, host}
> NFC: hci: Change nfc_hci_send_response gate parameter to pipe
On Tuesday 27 January 2015 23:36:36 Arnd Bergmann wrote:
> On Tuesday 27 January 2015 14:19:09 Guenter Roeck wrote:
> > On Tue, Jan 27, 2015 at 10:29:49PM +0100, Arnd Bergmann wrote:
> > > On Tuesday 27 January 2015 12:52:29 Guenter Roeck wrote:
> > > > Driver does this (today):
> > > >
> > > >
On Tuesday 27 January 2015 14:19:09 Guenter Roeck wrote:
> On Tue, Jan 27, 2015 at 10:29:49PM +0100, Arnd Bergmann wrote:
> > On Tuesday 27 January 2015 12:52:29 Guenter Roeck wrote:
> > > Driver does this (today):
> > >
> > > drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
> > >
> > > Is
Hi!
> + - flash_fault - list of flash faults that may have occurred:
> + * led-over-voltage - flash controller voltage to the flash LED
> + has exceededthe limit specific to the flash controller
> + * flash-timeout-exceeded - the flash strobe was sti
On Tuesday 20 January 2015 10:53:36 Murali Karicheri wrote:
> On 01/19/2015 03:11 PM, David Miller wrote:
> > From: Murali Karicheri
> > Date: Thu, 15 Jan 2015 19:10:03 -0500
> >
> >> The Network Coprocessor (NetCP) is a hardware accelerator that processes
> >> Ethernet packets. NetCP has a gigabit
Wrong type in printf format string, requires 'int'
but the argument type is 'unsigned int'
This was found using a static code analysis program called cppcheck
Signed-off-by: Rickard Strandqvist
---
drivers/staging/iio/adc/mxs-lradc.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
On Tue, Jan 27, 2015 at 10:29:49PM +0100, Arnd Bergmann wrote:
> On Tuesday 27 January 2015 12:52:29 Guenter Roeck wrote:
> > Driver does this (today):
> >
> > drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
> >
> > Isn't that the name to use ? Just wondering.
>
> Just because the driver
Hi Samuel,
The main reason for making an st21nfcb_hci_core is because the hci
network initialization procedure is proprietary.
It is almost using only NCI standard commands but some id's and commands
could be proprietary.
I would ideally rely on the hci core framework but i run out of idea
w
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm
This patch adds the device tree binding for the Qualcomm Top Control and
Status Register device. The TCSR is comprised of a set of registers that
provide various control and status functions for attached peripherals.
Signed-off-by: Andy Gross
---
.../devicetree/bindings/mfd/qcom,tcsr.txt
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qc
This patch adds automatic configuration for the ADM CRCI muxing required to
support DMA operations for GSBI clients. The GSBI mode and instance determine
the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
works properly.
Signed-off-by: Andy Gross
---
.../devicetree/bind
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-msm8960.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qc
This patch adds TCSR support for use by the GSBI to automatically configure ADM
CRCI values based on the GSBI port configuration.
Signed-off-by: Andy Gross
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/arch/arm
This patch set adds support for automatic configuration of GSBI DMA CRCI values.
DMA operations require that the ADM CRCI mux values be properly configured in
the TCSR (Top Control and Status Register) block. During probing of a GSBI
device, the client mode must be declared and this can be used t
io_lpcpd is accessible from struct tpm_stm_dev.
struct st33zp24_platform_data is only valid when using static platform
configuration data, not when using dts.
Reviewed-by: Jason Gunthorpe
Signed-off-by: Christophe Ricard
---
drivers/char/tpm/tpm_i2c_stm_st33.c | 18 +++---
1 file ch
tpm_i2c_stm_st33 is a TIS 1.2 TPM with a core interface which can be used
by different phy such as i2c or spi. The core part is called st33zp24 which
is also the main part reference.
include/linux/platform_data/tpm_stm_st33.h is renamed consequently.
The driver is also split into an i2c phy in cha
st33zp24 TIS 1.2 support also SPI. It is using a proprietary protocol to
transport TIS data.
Reviewed-by: Jason Gunthorpe
Signed-off-by: Christophe Ricard
---
drivers/char/tpm/st33zp24/Kconfig| 10 +
drivers/char/tpm/st33zp24/Makefile | 3 +
drivers/char/tpm/st33zp24/i2c.c | 2 -
Reviewed-by: Jason Gunthorpe
Signed-off-by: Christophe Ricard
---
.../bindings/security/tpm/st33zp24-spi.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644
Documentation/devicetree/bindings/security/tpm/st33zp24-spi.txt
diff --git a/Documentation/devi
Hi,
The following patchset:
- propose a new architecture allowing to share a core st33zp24 data management
layer with different phy (i2c & spi). For st33zp24 both phy have a proprietary
transport
protocol. Both are relying on the TCG TIS protocol. At the end, it simplifies
the maintenance.
- Add
On Tuesday 27 January 2015 12:52:29 Guenter Roeck wrote:
> Driver does this (today):
>
> drvdata->rtc_clk = clk_get(&pdev->dev, "rtc");
>
> Isn't that the name to use ? Just wondering.
Just because the driver uses it at the moment does not mean it's the name
that the IP block uses.
clk
On Tuesday 27 January 2015 12:54:30 Guenter Roeck wrote:
> On Tue, Jan 27, 2015 at 09:15:37PM +0100, Arnd Bergmann wrote:
> > On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
> > > };
> > >
> > > +#ifdef CONFIG_OF
> > > +static const struct of_device_id jz4740_of_matches[] =
If there is a DT node available for the root bridge's parent device,
use the dma configuration from that device node. For example, keystone
PCI devices would require dma_pfn_offset to be set correctly in the
device structure of the pci device in order to have the correct dma mask.
The DT node will
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device. Use the newly added APIs
pci_get/put_host_bridge_device() for implementing this.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Wi
limit the device dma_mask to the min of default dma_mask and
mask calculate from the dma-range size.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Bjorn Helgaas
Cc: Will Deacon
Cc: Russell King
Cc: Arnd Bergmann
Cc: Suravee Suthikulpanit
Signed-off-by: Murali Karicheri
---
drive
Move of_dma_configure() to device.c so that same function can be re-used
for PCI devices to obtain DMA configuration from DT. Also add a second
argument so that for PCI, DT node of root bus host bridge can be used to
obtain the DMA configuration for the slave PCI device.
Cc: Joerg Roedel
Cc: Gran
Add a helper function to get/put the root bus's host bridge device.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Will Deacon
Cc: Russell King
Cc: Arnd Bergmann
Cc: Suravee Suthikulpanit
Acked-by: Bjorn Helgaas
Signed-off-by: Murali Karicheri
---
drivers/pci/host-bridge.c | 14
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev->coherent_dma_mask + 1 instead of dev->coherent_dma_mask. Also add
code to check invalid values of size configured in DT and log error.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Bjorn Helgaas
Cc: Will Dea
arm_iommu_create_mapping() has size parameter of size_t and
arm_setup_iommu_dma_ops() can take a value higher than that
when this is called from the of code. So limit the size to
SIZE_MAX.
Cc: Joerg Roedel
Cc: Grant Likely
Cc: Rob Herring
Cc: Bjorn Helgaas
Cc: Will Deacon
Cc: Russell King
Cc
PCI devices on Keystone doesn't have correct dma_pfn_offset set. This patch
add capability to set the dma configuration such as dma-mask, dma_pfn_offset,
and dma ops etc using the information from DT. The prior RFCs and discussions
are available at [1] and [2] below.
[2] : https://www.mail-archive
Function of_iommu_configure() is called from of_dma_configure() to
setup iommu ops using DT property. This API is currently used for
platform devices for which DMA configuration (including iommu ops)
may come from device's parent. To extend this functionality for PCI
devices, this API need to take
On Tue, Jan 27, 2015 at 09:15:37PM +0100, Arnd Bergmann wrote:
> On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
> > };
> >
> > +#ifdef CONFIG_OF
> > +static const struct of_device_id jz4740_of_matches[] = {
> > + { .compatible = "ingenic,jz4740-watchdog", },
> > +
On Tue, Jan 27, 2015 at 09:16:45PM +0100, Arnd Bergmann wrote:
> On Tuesday 27 January 2015 15:11:29 Zubair Lutfullah Kakakhel wrote:
> > +clocks: phandle to rtcclk
> > +clock-names: must be "rtc"
> > +
> > +Example:
> > +
> > +watchdog: jz47xx-watchdog@0x10002000 {
> > + compatible = "ingeni
On Tue, Jan 27, 2015 at 9:31 PM, Laurent Pinchart
wrote:
> + if (of_find_property(np, "groups", NULL) ||
> + of_find_property(np, "pins", NULL)) {
> + pmx->func_prop_name = "function";
> + pmx->groups_prop_name = "groups";
Hi Niklas,
Thank you for the patch.
On Sunday 18 January 2015 13:20:04 Niklas Söderlund wrote:
> Configure the pinmux on kzm9d to use the serial connector for uart1.
>
> Signed-off-by: Niklas Söderlund
Acked-by: Laurent Pinchart
> ---
> arch/arm/boot/dts/emev2-kzm9d.dts | 13 +
>
The "function", "pins" and "groups" pinmux and pinctrl properties have
been standardized. Support them in addition to the custom "renesas,*"
properties. New-style and old-style properties can't be mixed in DT.
Signed-off-by: Laurent Pinchart
---
.../bindings/pinctrl/renesas,pfc-pinctrl.txt
On 24/01/15 14:01, Markus Pargmann wrote:
> This is a conversion queue driver for the mx25 SoC. It uses the central
> ADC which is used by two seperate independent queues. This driver
> prepares different conversion configurations for each possible input.
> For a conversion it creates a conversionq
On Tuesday 27 January 2015 15:11:29 Zubair Lutfullah Kakakhel wrote:
> +clocks: phandle to rtcclk
> +clock-names: must be "rtc"
> +
> +Example:
> +
> +watchdog: jz47xx-watchdog@0x10002000 {
> + compatible = "ingenic,jz4780-watchdog";
> + reg = <0x10002000 0x100>;
> +
> + clocks =
On Tuesday 27 January 2015 15:11:30 Zubair Lutfullah Kakakhel wrote:
> };
>
> +#ifdef CONFIG_OF
> +static const struct of_device_id jz4740_of_matches[] = {
> + { .compatible = "ingenic,jz4740-watchdog", },
> + { /* sentinel */ }
> +};
> +#endif
> +
> static int jz4740_wdt_probe(stru
On Tuesday 27 January 2015 22:51:00 Suman Tripathi wrote:
>
> + sdhc0: sdhc@1c00 {
> + device_type = "sdhc";
> + compatible = "arasan,sdhci-8.9a";
> + reg = <0x0 0x1c00 0x0 0x100>;
> + int
On Tuesday 27 January 2015 22:50:59 Suman Tripathi wrote:
> @@ -174,6 +176,13 @@ static int sdhci_arasan_probe(struct platform_device
> *pdev)
> pltfm_host->priv = sdhci_arasan;
> pltfm_host->clk = clk_xin;
>
> + ret = xgene_ahbc_iommu_attach_device(&pdev->dev);
> + if
Quoting Ken Westfield (2015-01-22 13:41:22)
> On Mon, Jan 19, 2015 at 06:05:27PM -0800, Stephen Boyd wrote:
> > This patchset adds support for the low power audio subsystem (LPASS)
> > clock controller hardware. I split out the #define patch for IPQ so that
> > it can go through the clock tree and
From: Peter Rosin
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c | 452 ++--
sound/soc/codecs/pcm512x.h | 5
From: Peter Rosin
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c |2 +-
sound/soc/codecs/pcm512x.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index e5f2fb884bf3..874723c36d65 100644
--- a/s
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.
Add support for resets requiring a clock to be enabled when
asserting/deasserting
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 38840a812924..6b271645eb43 100644
--- a/arch/arm/configs/sunxi
Some SoCs have a total of 4 possible USB controllers. One such example
is the A80, which has one USB3 dual role device and 3 EHCI/OHCI pairs.
Add a common VBUS regulator for the last host controller.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 10 ++
The A80 has 3 EHCI/OHCI USB controllers.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 70
1 file changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index d7ebd9390b01..9483b15b
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80-optimus.dts | 60 +
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts
b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c4de9cb9a5f6..16d30bb3a872 100644
--- a/arch/arm/
Hi everyone,
This is v3 of the sun9i A80 USB host support series.
This series adds USB host controller (EHCI/OHCI) support for the Allwinner
A80 SoC. The A80 has 3 pairs of host controllers and USB PHYs. The PHYs,
unlike in previous SoCs, do not have low level control registers anymore.
As such,
On sun9i, there are 3 independent usb phys for EHCI/OHCI.
Add device nodes for them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 37 +
1 file changed, 37 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/su
The USB clocks originally shared code with the gates clocks, but had
additional reset controllers. Move these to a separate file. This will
allow us to add new support for slightly different USB clocks, such as
on the A80, without affecting gates clocks, and also facilitate the
migration of gates c
On sun9i we have a new PHY driver for USB.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index eec304487e6d..63fcc5522393 100644
--- a/arch/arm/con
The USB controller and phy clocks and resets have a separate address
block and driver. Add the nodes to represent them.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt |
From: Peter Rosin
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 7f45cc468fa1..33aa18c8c88e 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b
From: Peter Rosin
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post "PCM5142/PCM5242 DAC clock
From: Peter Rosin
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described for the PCM5122 chip in t
From: Peter Rosin
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..4c65eb9ab59b 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/cod
On Tue, Jan 27, 2015 at 04:27:20PM +0530, Bhuvanchandra DV wrote:
> devm_* API was supposed to be used only in probe function call.
> Memory is allocated at 'probe' and free automatically at 'remove'.
Applied, thanks. Please don't dump entire backtraces into your commit
logs - they're far too big
From: Peter Rosin
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
This is like snd_pcm_hw_constraint_list(), but for ranges ins
From: Peter Rosin
Hi!
[ Note that the dt change is in patch 5/7, for those only interested
in that particular bit. ]
This series implements BCLK master modes for the pcm512x driver. It has
only been tested with the pcm5142 chip, but they are from the same family
and should be compatible. I ha
On Tue, Jan 27, 2015 at 07:35:09PM +0100, Stefan Wahren wrote:
> > Mark Brown hat am 27. Januar 2015 um 01:16 geschrieben:
> > > okay i understand. But doesn't it need a extra driver to set the switching
> > > frequency because of the new compatible string?
> > I don't understand this bit at all
On Tue, Jan 27, 2015 at 11:13:08AM -0800, Sören Brinkmann wrote:
> On Tue, 2015-01-27 at 09:20AM -0600, Felipe Balbi wrote:
> > On Mon, Jan 26, 2015 at 05:45:29PM -0800, Soren Brinkmann wrote:
> > > A reset through a GPIO is optional. Don't fail probing when it is
> > > missing.
> > >
> > > Report
On Tue, 2015-01-27 at 09:20AM -0600, Felipe Balbi wrote:
> On Mon, Jan 26, 2015 at 05:45:29PM -0800, Soren Brinkmann wrote:
> > A reset through a GPIO is optional. Don't fail probing when it is
> > missing.
> >
> > Reported-by: Andreas Färber
> > Signed-off-by: Soren Brinkmann
> > ---
> > Hi And
On 01/27/2015 03:57 AM, Bhuvanchandra DV wrote:
devm_* API was supposed to be used only in probe function call.
Memory is allocated at 'probe' and free automatically at 'remove'.
Usage of devm_* functions outside probe sometimes leads to memory leak.
Avoid using devm_kzalloc in dspi_setup_transfe
On Fri, Jan 23, 2015 at 02:03:28PM +0900, Inha Song wrote:
> This patch add the sound machine driver for Trats2 board.
> The codec operate in master mode.
This looks like (and mostly should be) a DTified copy of the littlemill
driver. The major differences are the fact that this lacks jack
detect
On 01/27/2015 06:27 AM, Robin Murphy wrote:
Hi Murali,
On 23/01/15 22:32, Murali Karicheri wrote:
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev->coherent_dma_mask + 1 instead of dev->coherent_dma_mask. To detect
overflow when mask is set to max of u64, add a check
On Fri, Jan 23, 2015 at 02:03:29PM +0900, Inha Song wrote:
> + - samsung,audio-routing : A list of the connections between audio
> + components. each entry is a pair of strings, the first being the
> + connection's sink, the second being the connection's source
The list of valid components sh
On Tue, Jan 27, 2015 at 06:09:39PM +0100, Sylwester Nawrocki wrote:
> On 23/01/15 06:03, Inha Song wrote:
> > + priv->clk_mclk = of_clk_get_by_name(codec_node, "MCLK1");
> > + if (IS_ERR(priv->clk_mclk)) {
> > + dev_err(&pdev->dev, "Failed to get mclk clock\n");
> > + of_n
On 01/27/2015 01:42 PM, Bjorn Helgaas wrote:
On Tue, Jan 27, 2015 at 12:14 PM, Murali Karicheri wrote:
On 01/26/2015 06:59 PM, Bjorn Helgaas wrote:
On Mon, Jan 26, 2015 at 5:25 PM, Murali Karicheri
wrote:
On 01/23/2015 06:41 PM, Bjorn Helgaas wrote:
On Fri, Jan 23, 2015 at 05:32:37PM -05
On Tue, Jan 27, 2015 at 06:27:45PM +, Adam Sampson wrote:
> Add support for the LinkSprite pcDuino 3 Nano board. This is a low-cost
> Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM,
> 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and
> another for
On Tue, Jan 27, 2015 at 12:14 PM, Murali Karicheri wrote:
> On 01/26/2015 06:59 PM, Bjorn Helgaas wrote:
>>
>> On Mon, Jan 26, 2015 at 5:25 PM, Murali Karicheri
>> wrote:
>>>
>>> On 01/23/2015 06:41 PM, Bjorn Helgaas wrote:
On Fri, Jan 23, 2015 at 05:32:37PM -0500, Murali Karicheri
Hi Mark,
> Mark Brown hat am 27. Januar 2015 um 01:16 geschrieben:
>
>
> On Mon, Jan 26, 2015 at 08:46:45PM +0100, Stefan Wahren wrote:
>
> > > > Does a common property name exists for the switching frequency or would
> > > > it be vendor specific?
>
> > > As far as I know most regulators have fi
Add support for the LinkSprite pcDuino 3 Nano board. This is a low-cost
Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM,
4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and
another for power in, HDMI, SATA, 5V power for SATA devices, gigabit
Ethernet, an
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