On Tuesday 24 March 2015 01:09 AM, Nishanth Menon wrote:
From: Keerthy
Add bandgap and related thermal nodes. The patch adds 5 thermal
sensors. Only one cooling device for mpu as of now. The sensors are
the exact same on both dra72 and dra7. Introduce CPU, GPU, core nodes
for the moment as th
On 02/20, Mathieu Olivari wrote:
> This change is done as a follow-up to the following thread:
> https://lkml.org/lkml/2014/10/1/436
>
> qcom-wdt is currently assuming the presence of a dedicated node in DT
> to gets its configuration. However, on msm architecture, the watchdog is
> usually part o
On 03/26/2015 10:40 PM, Shubhrajyoti Datta wrote:
+
+static int dc_restart_handler(struct notifier_block *this, unsigned long
mode,
+ void *cmd)
+{
+ struct dc_wdt *wdt = container_of(this, struct dc_wdt,
restart_handler);
+
+
On 03/26/2015 12:59 AM, Baruch Siach wrote:
This commit add a driver for the watchdog functionality of the Conexant CX92755
SoC, from the Digicolor series of SoCs. Of 8 system timers provided by the
CX92755, the first one, timer A, can reset the chip when its counter reaches
zero. This driver use
Add a device tree binding documentation to the USB PHY hardware block on the
Conexant CX92755 SoC. The CX92755 is one of the Digicolor SoCs series. Other
SoCs in that series may share the same hardware block.
Signed-off-by: Baruch Siach
---
.../devicetree/bindings/phy/digicolor-usb-phy.txt
Add a driver for the USB PHY on the Conexant CX92755 SoC, from the Digicolor
series of SoCs. The PHY is connected to the on-chip chipidea usb2 host.
The hardware is somewhat similar to the phy-mxs-usb.c usb_phy, but it is
different enough to merit its own driver. Also, this driver uses the generic
On Thu, Mar 26, 2015 at 4:11 AM, Paul Kocialkowski wrote:
> Le jeudi 26 mars 2015 à 09:53 +0100, Hans de Goede a écrit :
>> Hi,
>>
>> On 25-03-15 23:35, Paul Kocialkowski wrote:
>> > Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
>> >> Hi,
>> >>
>> >> On 24-03-15 00:12, Rob Herring w
On Thu, Mar 26, 2015 at 02:22:26PM +, Russell King - ARM Linux wrote:
> On Thu, Mar 26, 2015 at 07:13:38PM +0800, Leo Yan wrote:
> > +static unsigned long hisi_stub_clk_recalc_rate(struct clk_hw *hw,
> > + unsigned long parent_rate)
> > +{
> ...
> > + BUG_ON(!stub_clk->lock);
> ...
hi Russell,
On Thu, Mar 26, 2015 at 02:18:34PM +, Russell King - ARM Linux wrote:
> On Thu, Mar 26, 2015 at 07:13:36PM +0800, Leo Yan wrote:
> > +struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
> > +int nr_clks)
> > +{
> > + struct
On Thu, Mar 26, 2015 at 1:59 PM, Sakari Ailus wrote:
> Hi Jacek,
>
> Jacek Anaszewski wrote:
>> Label is used for naming LED class devices. Since ePAPR
>> doesn't require uniqueness for label properties, it has to be
>> explicitly required in the LEDs common bindings documentation.
>>
>> Signed-of
On Thu, Mar 26, 2015 at 04:30:24PM -0700, Julius Werner wrote:
> The Rockchip SPI driver currently calculates its clock rate divisor by
> integer dividing the parent rate by the target rate, and then rounding
> the result up to the next even number (since the divisor must be
> even).
Applied both,
Julius,
On Thu, Mar 26, 2015 at 4:30 PM, Julius Werner wrote:
> We have found that we can sometimes see read failures on boards with
> high-capacitance SPI lines. It seems that the controller samples the Rx
> data line too early, and its register interface has an "Rx Sample Delay"
> setting to fi
Julius,
On Thu, Mar 26, 2015 at 4:30 PM, Julius Werner wrote:
> The Rockchip SPI driver currently calculates its clock rate divisor by
> integer dividing the parent rate by the target rate, and then rounding
> the result up to the next even number (since the divisor must be
> even).
>
> Clock rat
On 03/26/2015 10:54 PM, Lee Jones wrote:
> On Thu, 26 Mar 2015, Beomho Seo wrote:
>> On 03/24/2015 05:38 PM, Krzysztof Kozlowski wrote:
>>> 2015-03-24 9:01 GMT+01:00 Beomho Seo :
On 03/10/2015 10:44 PM, Beomho Seo wrote:
> On 03/09/2015 09:13 PM, Krzysztof Kozlowski wrote:
>> On pon, 2
On Thu, Mar 26, 2015 at 10:38:54PM +0100, Robert Jarzmik wrote:
> Greg Kroah-Hartman writes:
>
> > On Fri, Feb 20, 2015 at 05:02:57PM +0100, Robert Jarzmik wrote:
> >> If there is no solution, I'll fallback through arch/arm/plat-pxa, not very
> >> nice,
> >> but it has to land somewhere, I don't
The Rockchip SPI driver currently calculates its clock rate divisor by
integer dividing the parent rate by the target rate, and then rounding
the result up to the next even number (since the divisor must be
even).
Clock rate divisors should always be rounded up, so that the resulting
frequency is
We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.
This patch adds a new optional device tree
--
We have your donation reply for details
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Arun,
On Wed, Mar 25, 2015 at 05:04:57PM -0700, Arun Ramamurthy wrote:
>
>
> On 15-03-25 03:16 PM, Kishon Vijay Abraham I wrote:
> >Hi,
> >
> >On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
> >>Broadcom's Cygnus chip has a USB 2.0 host controller connected to
> >>three separate ph
On Sat, Mar 21, 2015 at 12:26:04PM +0100, Martin Kepplinger wrote:
> From: Martin Kepplinger
>
> The MMA8653FC is a low-power, three-axis, capacitive micromachined
> accelerometer with 10 bits of resolution with flexible user-programmable
> options.
>
> Embedded interrupt functions enable overal
2015-03-26 16:46 GMT+01:00 Russell King - ARM Linux :
> On Tue, Mar 24, 2015 at 02:23:38PM -0400, Peter Hurley wrote:
>> Hi Maxime,
>>
>> On 03/12/2015 05:55 PM, Maxime Coquelin wrote:
>> > +static unsigned int stm32_get_mctrl(struct uart_port *port)
>> > +{
>> > + /*
>> > +* This routine is
HI Peter
2015-03-24 19:23 GMT+01:00 Peter Hurley :
> Hi Maxime,
>
> On 03/12/2015 05:55 PM, Maxime Coquelin wrote:
>> From: Maxime Coquelin
>>
>> This drivers adds support to the STM32 USART controller, which is a
>> standard serial driver.
>
> Comments below.
Thanks for the review, please find
Greg Kroah-Hartman writes:
> On Fri, Feb 20, 2015 at 05:02:57PM +0100, Robert Jarzmik wrote:
>> If there is no solution, I'll fallback through arch/arm/plat-pxa, not very
>> nice,
>> but it has to land somewhere, I don't want lubbock to remain broken.
>
> drivers/platform/arm ?
Most certainly.
Hi Jacek,
Jacek Anaszewski wrote:
> Label is used for naming LED class devices. Since ePAPR
> doesn't require uniqueness for label properties, it has to be
> explicitly required in the LEDs common bindings documentation.
>
> Signed-off-by: Jacek Anaszewski
> Acked-by: Kyungmin Park
> Cc: Bryan
Hi Daniel,
Thanks for the review. Please find my answers below.
2015-03-26 10:50 GMT+01:00 Daniel Lezcano :
> On 03/12/2015 10:55 PM, Maxime Coquelin wrote:
>>
>> From: Maxime Coquelin
>>
>> This patch adds clocksource support for ARMv7-M's System timer,
>> also known as SysTick.
>>
>> Signed-
On Thu, 26 Mar 2015, Geert Uytterhoeven wrote:
> Hi Lee,
>
> On Thu, Mar 26, 2015 at 2:51 PM, Lee Jones wrote:
> > On Wed, 25 Mar 2015, Geert Uytterhoeven wrote:
> >> On Mon, Mar 9, 2015 at 10:28 AM, Lee Jones wrote:
> >> > On Fri, 06 Mar 2015, Mike Turquette wrote:
> >> >> This approach looks
* Eduardo Valentin [150324 08:17]:
> On Mon, Mar 23, 2015 at 02:39:39PM -0500, Nishanth Menon wrote:
> > BeagleBoard-X15 has capability for a fan and has an onboard TMP102
> > temperature sensor as well. This allows us to create a new thermal
> > zone (called, un-imaginatively "board"), and allows
* Sebastian Reichel [150321 13:20]:
> From: Sebastian Reichel
>
> This adds support for the N900's accelerometer to
> the Nokia N900 DTS file.
>
> Signed-off-by: Sebastian Reichel
This at least currently does not conflict with anything I have
queued, so I suggest you try to get Greg to take t
On Wed, Mar 25, 2015 at 1:41 AM, Scott Branden wrote:
> Hi Rob,
>
> On 15-03-22 06:20 PM, Rob Herring wrote:
>>
>> On 03/20/2015 08:06 PM, Scott Branden wrote:
>>>
>>> This patchset attempts to standardize the naming of dt-bindings
>>> documents based on the Broadcom vendor prefix of brcm.
>>>
>>>
On Thu, Mar 26, 2015 at 11:47 AM, Mark Brown wrote:
> In current -next of_graph.h fails to build due to it relying on
> linux/types.h without explicitly including it:
>
> ../include/linux/of_graph.h:43:71: error: unknown type name 'u32'
>
> caused by bfe446e37c4e (of: Add of_graph_get_port_by_id f
Hi Corentin,
Here is a quick review, there surely are a lot of other things I didn't
spot.
On Mon, 16 Mar 2015 20:01:22 +0100
LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support:
>
Hi,
On Wed, Mar 25, 2015 at 05:44:42PM +0100, Dr. H. Nikolaus Schaller wrote:
> Am 25.03.2015 um 16:21 schrieb Sebastian Reichel :
> > On Wed, Mar 25, 2015 at 08:59:14AM +0100, Dr. H. Nikolaus Schaller wrote:
> >> Am 25.03.2015 um 02:45 schrieb Sebastian Reichel :
> >>> On Tue, Mar 24, 2015 at 06:
* Kishon Vijay Abraham I [150317 04:25]:
> As per the TRMs of AM572x, OMAP4430, OMAP4460, OMAP543x, the value of
> SYNC2 must be set to 0x6 in order to ensure correct operation.
>
> So modified the SYNC2 value of OCP2SCP TIMING register to 0x6 in all the
> platforms that use OCP2SCP driver except
A small set to fix warnings from the kernel.
Note, the atmel_defconfig will require CONFIG_REGULATOR_GPIO
to be set.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majord
The SAM5D3 Xplained device tree is missing hte vqmmc node which is
tied to 3.3V on the board. Add this to avoid the kernel warning that
there is no vqmmc node.
atmel_mci f000.mmc: No vqmmc regulator found
Signed-off-by: Ben Dooks
--
CC: linux-arm-ker...@lists.infradead.org
CC: Andrew Victor
Add gpio regulator for vmmc0 and attach the vmmc for it to the mmc0
node on the SAM5D3 Xplained board. This will remove the following
warning from the kernel:
atmel_mci f000.mmc: No vmmc regulator found
Note, atmel_defconfig will need gpio regulator support enabled if this
is to be used prope
Hi Doug,
Any comment with v6 of the APM EDAC driver?
-Loc
On Mon, Mar 16, 2015 at 11:30 PM, Loc Ho wrote:
> This patch adds support for the APM X-Gene SoC EDAC driver for DT.
>
> v6:
> * Rebase to 4.0.0-rc3
> * Add memory scrub stub function and enable ARM64 EDAC support patch
> * Add bit defin
The mmc1 channel is not populated on the SAM5D3 Xplained board, however
it is enabled and therefore the driver is attaching to it.
The node configuration for mmc1 is missing, so add an mmc1 node in the
device tree so add the basic node, set it to default it to disabled. Also
add the vmmc and also
Am Donnerstag, den 26.03.2015, 09:47 -0700 schrieb Mark Brown:
> In current -next of_graph.h fails to build due to it relying on
> linux/types.h without explicitly including it:
>
> ../include/linux/of_graph.h:43:71: error: unknown type name 'u32'
>
> caused by bfe446e37c4e (of: Add of_graph_get_
Hi Lee,
On Thu, Mar 26, 2015 at 2:51 PM, Lee Jones wrote:
> On Wed, 25 Mar 2015, Geert Uytterhoeven wrote:
>> On Mon, Mar 9, 2015 at 10:28 AM, Lee Jones wrote:
>> > On Fri, 06 Mar 2015, Mike Turquette wrote:
>> >> This approach looks fine to me. In practice I think it is restricted to
>> >> hard
Hi Mark,
Thank you for the patch.
On Thursday 26 March 2015 09:47:55 Mark Brown wrote:
> In current -next of_graph.h fails to build due to it relying on
> linux/types.h without explicitly including it:
>
> ../include/linux/of_graph.h:43:71: error: unknown type name 'u32'
>
> caused by bfe446e37
From: Sjoerd Simons
When disabling the samsung PWM the output state remains at the level it
was in the end of a pwm cycle. In other words, calling pwm_disable when
at 100% duty will keep the output active, while at all other setting the
output will go/stay inactive. On top of that the samsung PWM
In current -next of_graph.h fails to build due to it relying on
linux/types.h without explicitly including it:
../include/linux/of_graph.h:43:71: error: unknown type name 'u32'
caused by bfe446e37c4e (of: Add of_graph_get_port_by_id function). Add
an explicit inclusion to fix this.
Signed-off-b
Add pwm-fan node to the OdroidXU3 board.
Tested on OdroidXU3 board.
Signed-off-by: Anand Moon
---
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
b/arch/arm/boot/dts/exynos5422-odroidxu3
update the cooling level for cpu0 to avoid following message.
root@odroidxu3:~# dmesg | grep ther
[0.241511] /thermal-zones/cpu-thermal/cooling-maps/map0:
could not get #cooling-cells for /cpus/cpu@0
Signed-off-by: Anand Moon
---
arch/arm/boot/dts/exynos5420.dtsi |
This commit enables TMU IP block on the Exynos5422 OdroidXU3
device.
Tested on OdroidXU3 board.
Signed-off-by: Anand Moon
---
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
b/a
Below changes depend on following patch.
https://patchwork.kernel.org/patch/5944061/
Update the pwm_config with duty then update the pwm_disable
to poweroff the cpu fan.
Tested on OdroidXU3 board.
Signed-off-by: Anand Moon
---
drivers/hwmon/pwm-fan.c | 10 --
1 file changed, 4 insertio
Move the registration of thermal sensors for tmu_cpu0 from exynos5420.dtsi
to exynos5-cpu-thermal.dtsi, to avoid duplicate registration of the sensors.
Tested on OdroidXU3 board.
Signed-off-by: Anand Moon
---
arch/arm/boot/dts/exynos5-cpu-thermal.dtsi | 58 ++
arch/a
This work depeds upon work done by Lukasz Majewski
and Sjoerd Simons regarding the pwm-fan.
-Anand Moon
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.ht
On 24/03/15 22:53, Mark Brown wrote:
On Tue, Mar 24, 2015 at 10:30:08PM +, Srinivas Kandagatla wrote:
+static ssize_t bin_attr_eeprom_write(struct file *filp, struct kobject *kobj,
+struct bin_attribute *attr,
+char *
On Tue, Mar 24, 2015 at 02:23:38PM -0400, Peter Hurley wrote:
> Hi Maxime,
>
> On 03/12/2015 05:55 PM, Maxime Coquelin wrote:
> > +static unsigned int stm32_get_mctrl(struct uart_port *port)
> > +{
> > + /*
> > +* This routine is used for geting signals of: DTR, DCD, DSR, RI,
> > +* and
On Thu, Mar 26, 2015 at 02:31:30PM +0200, Peter Ujfalusi wrote:
> On 03/26/2015 12:56 PM, Vinod Koul wrote:
> >> +#define TI_XBAR_OUTPUTS 127
> >> +#define TI_XBAR_INPUTS256
> > Ideally this should be moved to DT. Will next revision of this chip always
> > support these output and inputs?
>
On Thu, Mar 26, 2015 at 02:11:38PM +0200, Peter Ujfalusi wrote:
> On 03/26/2015 12:50 PM, Vinod Koul wrote:
> > On Wed, Mar 11, 2015 at 03:23:24PM +0200, Peter Ujfalusi wrote:
> >> DMA routers are transparent devices used to mux DMA requests from
> >> peripherals to DMA controllers. They are used w
On Tue, Mar 24, 2015 at 08:14:31PM +0800, Shawn Guo wrote:
> On Mon, Mar 02, 2015 at 08:03:54PM +, Russell King wrote:
> > Enable the commented out PCF8523 RTC support for Hummingboard pro
> > base boards.
> >
> > Signed-off-by: Russell King
> > ---
> > For acks please.
>
> Russell,
>
> Wha
* Peter Ujfalusi [150326 05:32]:
> On 03/26/2015 12:56 PM, Vinod Koul wrote:
> >> +
> >> +static void ti_dma_xbar_free(struct device *dev, void *route_data)
> >> +{
> >> + struct ti_dma_xbar_data *xbar = dev_get_drvdata(dev);
> >> + struct ti_dma_xbar_map *map = route_data;
> >> +
> >> + dev_db
The A10 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.
Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.
Signed-off-by: Hans de Goede
---
arch/arm/boot/
From: Maxime Ripard
The SRAM the EMAC is using might not have been mapped accordingly by the
bootloader, preventing the EMAC to work properly.
Ask for that SRAM to be mapped at probe time to make sure that this never
happens.
Signed-off-by: Maxime Ripard
[hdego...@redhat.com: Make sure SUNXI_S
Hi All,
Here is v2 of my cleaned up version of Maxime's sunxi SRAM controller driver.
Changes since v1:
- Make the SUNXI_SRAM Kconfig option hidden, enabled by default if ARCH_SUNXI
- Fix some typos in the comments in the dts file, both in the example in the
devicetree-binding documentation, as
The A13 / A10s has a few SRAM that can be mapped either to a device or to
the CPU, with the mapping being controlled by a SRAM controller.
Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.
Signed-off-by: Hans de Goede
---
arch/ar
From: Maxime Ripard
The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.
Since most of the time these SRAM won't be accessible by the CPU,
we can't use the mmio-sram driver and compatible.
Signed-off-by: Maxime Ripar
From: Maxime Ripard
The Allwinner SoCs have a handful of SRAM that can be either mapped to be
accessible by devices or the CPU.
That mapping is controlled by an SRAM controller, and that mapping might not be
set by the bootloader, for example if the device wasn't used at all, or if
we're using s
Hi,
On 24-03-15 16:22, Maxime Ripard wrote:
On Fri, Mar 20, 2015 at 07:52:49PM +0100, Hans de Goede wrote:
From: Maxime Ripard
The SRAM the EMAC is using might not have been mapped accordingly by the
bootloader, preventing the EMAC to work properly.
Ask for that SRAM to be mapped at probe ti
Hi,
On 24-03-15 16:20, Maxime Ripard wrote:
On Fri, Mar 20, 2015 at 07:52:46PM +0100, Hans de Goede wrote:
The A10 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.
Since most of the time these SRAM won't be accessible b
Hi,
On 24-03-15 16:19, Maxime Ripard wrote:
Hi,
On Fri, Mar 20, 2015 at 07:52:45PM +0100, Hans de Goede wrote:
From: Maxime Ripard
The Allwinner SoCs have a handful of SRAM that can be either mapped to be
accessible by devices or the CPU.
That mapping is controlled by an SRAM controller, an
On Thu, Mar 26, 2015 at 07:13:38PM +0800, Leo Yan wrote:
> +static unsigned long hisi_stub_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
...
> + BUG_ON(!stub_clk->lock);
...
> +static int hisi_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> +
On Thu, Mar 26, 2015 at 07:13:36PM +0800, Leo Yan wrote:
> +struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
> + int nr_clks)
> +{
> + struct hisi_clock_data *clk_data;
> + void __iomem *base;
> +
> + if (np) {
> +
On Fri, 20 Mar 2015, Jacek Anaszewski wrote:
> This patch adds device tree binding documentation for
> the flash cell of the Maxim max77693 multifunctional device.
>
> Signed-off-by: Jacek Anaszewski
> Signed-off-by: Andrzej Hajda
> Acked-by: Kyungmin Park
> Cc: Lee Jones
> Cc: Chanwoo Choi
Label is used for naming LED class devices. Since ePAPR
doesn't require uniqueness for label properties, it has to be
explicitly required in the LEDs common bindings documentation.
Signed-off-by: Jacek Anaszewski
Acked-by: Kyungmin Park
Cc: Bryan Wu
Cc: Richard Purdie
Cc: Sakari Ailus
Cc: dev
On Thu, 26 Mar 2015, Beomho Seo wrote:
> On 03/24/2015 05:38 PM, Krzysztof Kozlowski wrote:
> > 2015-03-24 9:01 GMT+01:00 Beomho Seo :
> >> On 03/10/2015 10:44 PM, Beomho Seo wrote:
> >>> On 03/09/2015 09:13 PM, Krzysztof Kozlowski wrote:
> On pon, 2015-03-09 at 20:46 +0900, Beomho Seo wrote:
On Wed, 25 Mar 2015, Geert Uytterhoeven wrote:
> Hi Lee,
>
> On Mon, Mar 9, 2015 at 10:28 AM, Lee Jones wrote:
> > On Fri, 06 Mar 2015, Mike Turquette wrote:
> >> Quoting Lee Jones (2015-03-04 04:00:03)
> >> > Mike,
> >> >
> >> > Do you want me to resend this set with Robert's Reviewed-by applie
On 03/24/2015 05:38 PM, Krzysztof Kozlowski wrote:
> 2015-03-24 9:01 GMT+01:00 Beomho Seo :
>> On 03/10/2015 10:44 PM, Beomho Seo wrote:
>>> On 03/09/2015 09:13 PM, Krzysztof Kozlowski wrote:
On pon, 2015-03-09 at 20:46 +0900, Beomho Seo wrote:
> On 03/09/2015 08:02 PM, Krzysztof Kozlowski
On 03/26/2015 12:57 PM, Vinod Koul wrote:
> On Wed, Mar 11, 2015 at 03:23:27PM +0200, Peter Ujfalusi wrote:
>> Instead of magic numbers in the code, use define for number of logical DMA
>> channels and DMA requests.
>>
>> Signed-off-by: Peter Ujfalusi
>> ---
>> drivers/dma/omap-dma.c | 7 +--
On 03/26/2015 12:56 PM, Vinod Koul wrote:
>> +#define TI_XBAR_OUTPUTS 127
>> +#define TI_XBAR_INPUTS 256
> Ideally this should be moved to DT. Will next revision of this chip always
> support these output and inputs?
They are coming from DT. I'm using these as fall back values in case we
On 03/26/2015 12:50 PM, Vinod Koul wrote:
> On Wed, Mar 11, 2015 at 03:23:24PM +0200, Peter Ujfalusi wrote:
>> DMA routers are transparent devices used to mux DMA requests from
>> peripherals to DMA controllers. They are used when the SoC integrates more
>> devices with DMA requests then their cont
On 26/03/15 11:49, Russell King - ARM Linux wrote:
On Thu, Mar 26, 2015 at 11:43:21AM +, Sudeep Holla wrote:
I tried using this driver and found that AMBA driver expects apb_clk
without which probe fails. Though your example have it, it's not
explicit from the binding. Also AMBA binding ex
On Thu, Mar 26, 2015 at 11:43:21AM +, Sudeep Holla wrote:
> I tried using this driver and found that AMBA driver expects apb_clk
> without which probe fails. Though your example have it, it's not
> explicit from the binding. Also AMBA binding expects the primecell id in
> the binding.
That's o
On 04/03/15 11:01, Vincent Yang wrote:
From: Jassi Brar
Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
Signed-off-by: Jassi Brar
Signed-off-by: Andy Green
Signed-off-by: Vincent Yang
Signed-off-by: Tetsuya Nuriya
---
.../devicetree/bindings/mailbox/arm-mhu.txt
MIC must be initilized by MIPI DSI when it is being bound.
Signed-off-by: Hyungwon Hwang
---
Changes for v2:
- None
Changes for v3:
- None
.../devicetree/bindings/video/exynos_dsim.txt | 23 ++---
drivers/gpu/drm/exynos/exynos_drm_dsi.c| 24 ++
This patch adds support for Exynos5433 mipi dsi.
Signed-off-by: Hyungwon Hwang
---
Changes for v2:
- change the author of "drm/exynos: dsi: add support for Exynos5433 SoC" to
Hyungwon Hwang by the previous author's will
Changes for v3:
- Separated from the patch "drm/exynos: dsi: add support f
On some board, TE GPIO should be configured properly thoughout pinctrl driver
as an wakeup interrupt. So this gpio should be configurable in the board's DT,
not being requested as a input pin.
Signed-off-by: Hyungwon Hwang
---
Changes for v2:
- None
Changes for v3:
- None
drivers/gpu/drm/exy
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly.
Signed-off-by: Hyungwon Hwang
---
Changes for v3:
- Newly added
.../devicetree/bindings/video/exynos_dsim.txt
This patchset is based on the git(branch name: exynos-drm-next) which is
maintained by Inki Dae.
https://kernel.googlesource.com/pub/scm/linux/kernel/git/...
This patchset adds 2 new device drivers, decon and mic, and adds support for
Exynos5433 mipi dsi. To enable display in a Exynos5433 board, d
MIC(Mobile image compressor) is newly added IP in Exynos5433. MIC
resides between decon and mipi dsim, and compresses frame data by 50%.
With dsi, not display port, to send frame data to the panel, the
bandwidth is not enough. That is why this compressor is introduced.
Signed-off-by: Hyungwon Hwan
This patch makes the driver use arrays for clocks, register address,
and values. By doing this, it becomes easier to add support for another
SoC.
Signed-off-by: Hyungwon Hwang
---
Changes for v3:
- Separated from the patch "drm/exynos: dsi: add support for Exynos5433 SoC"
in version 2.
drivers
From: Joonyoung Shim
DECON(Display and Enhancement Controller) is new IP replacing FIMD in
Exynos5433. This patch adds Exynos5433 decon driver.
Signed-off-by: Joonyoung Shim
Signed-off-by: Hyungwon Hwang
---
Changes for v2:
- change file names and variable names of decon to represnt exynos543
When there are multiple ports or multiple endpoints in a port, they have to be
distinguished by the value of reg property. It is common. The drivers can get
the specific endpoint in the specific port via this function. Now the drivers
have to implement this code in themselves or have to force the o
Document the new compatible for stub clock driver which is used for CPU
and DDR's dynamic frequency scaling.
Signed-off-by: Leo Yan
---
.../devicetree/bindings/clock/hisi,stub-clock.txt | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bi
In the old clk init function, it will read the register base address
from dts and allocate the clk data structures. But for the some cases,
the clock driver don't need init the reg's base address, which will
directly access mmio region with syscon.
So for clock's initialization, this patch adds on
Add stub clock register function, so can easily enable stub clock for
platforms.
Signed-off-by: Leo Yan
---
drivers/clk/hisilicon/clk.c | 29 +
drivers/clk/hisilicon/clk.h | 12
2 files changed, 41 insertions(+)
diff --git a/drivers/clk/hisilicon/clk.c b
On hisilicon platform, there have some clocks which can directly send
messages to power controller to change frequency; this includes cpu and
ddr's clocks.
For dynamic frequency scaling, firstly need write the frequency value
to sram region, and then write the communication register to trigger
pow
This series adds support for hisilicon stub clock driver. On hi6220,
the bootloader needs load the firmware image and set info for OPPs;
after run into kernel, the stub clock driver is used to communicate
w/t firmware for cpu dynamic frequency scaling. So finally s/w will
simply write request in sr
On Wed, Mar 11, 2015 at 03:23:27PM +0200, Peter Ujfalusi wrote:
> Instead of magic numbers in the code, use define for number of logical DMA
> channels and DMA requests.
>
> Signed-off-by: Peter Ujfalusi
> ---
> drivers/dma/omap-dma.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-
On Wed, Mar 11, 2015 at 03:23:26PM +0200, Peter Ujfalusi wrote:
> The DRA7x has more peripherals with DMA requests than the sDMA can handle:
> 205 vs 127. All DMA requests are routed through the DMA crossbar, which can
> be configured to route selected incoming DMA requests to specific sDMA
> reque
On Wed, Mar 11, 2015 at 03:23:24PM +0200, Peter Ujfalusi wrote:
> DMA routers are transparent devices used to mux DMA requests from
> peripherals to DMA controllers. They are used when the SoC integrates more
> devices with DMA requests then their controller can handle.
> DRA7x is one example of su
Implemented CPU hotplug on e500mc, e5500 and e6500, and support
multiple threads mode and 64-bits mode.
For e6500 with two threads, if one thread is online, it can
enable/disable the other thread in the same core. If two threads of
one core are offline, the core will enter the PH20 state (a low po
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
Signed-off-by: Chenhui
Dear Daniel,
On Wed, 18 Mar 2015 09:52:33 +
Daniel Stone wrote:
> Hi,
>
> On 18 March 2015 at 08:16, Hyungwon Hwang
> wrote:
> > +#define REG(dsi, reg) ((dsi)->reg_base +
> > dsi->driver_data->regs[(reg)])
>
> This seems like a good change in general, but please split it up: it
> makes b
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all cach
In sleep mode, the clocks of e500 cores and unused IP blocks is
turned off. The IP blocks which are allowed to wake up the processor
are still running.
The sleep mode is equal to the Standby state in Linux. Use the
command to enter sleep mode:
echo standby > /sys/power/state
Signed-off-by: Chen
Hi Clément,
On Mon, Mar 09, 2015 at 11:12:02AM +0100, clement.perroch...@effinnov.com wrote:
> From: Clément Perrochaud
>
> This patch brings support for the NXP-NCI NFC controllers family.
>
> It has been successfully tested on the following SoC boards:
> - BeagleBone
> - BeagleBone Black
>
1 - 100 of 119 matches
Mail list logo
