For device resource PREF bit setting under bridge 64-bit pref resource,
we need to make sure only set PREF for 64bit resource, so set
IORESOUCE_MEM_64 for 64bit resource during OF device resource flags
parsing.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96261
Link: https://bugzilla.kernel.o
Thanks, Klimov,
You are right. I will fix it in next patches.
On Tue, Aug 18, 2015 at 03:12:02AM +0300, Alexey Klimov wrote:
> Date: Tue, 18 Aug 2015 03:12:02 +0300
> From: Alexey Klimov
> To: Kenneth Lee
> CC: robh...@kernel.org, pawel.m...@arm.com, Mark Rutland
> , ijc+devicet...@hellion.org
On 08/21/2015 03:30 PM, Shawn Lin wrote:
> On 2015/8/21 14:27, Jaehoon Chung wrote:
>> Hi, Shawn.
>>
>> Is this based on Ulf's repository?
>
>
> no, it's based on "https://github.com/jh80chung/dw-mmc.git
> tags/dw-mmc-for-ulf-v4.2" ：）
Oh..I will rebase to Ulf's next branch on this weekend.
Then
On 2015/8/21 14:27, Jaehoon Chung wrote:
Hi, Shawn.
Is this based on Ulf's repository?
no, it's based on "https://github.com/jh80chung/dw-mmc.git
tags/dw-mmc-for-ulf-v4.2" ：）
On 08/20/2015 05:43 PM, Shawn Lin wrote:
DesignWare MMC Controller can supports two types of DMA
mode: external
Hi, Shawn.
Is this based on Ulf's repository?
On 08/20/2015 05:43 PM, Shawn Lin wrote:
> DesignWare MMC Controller can supports two types of DMA
> mode: external dma and internal dma. We get a RK312x platform
> integrated dw_mmc and ARM pl330 dma controller. This patch add
> edmac ops to support
On 08/20/2015 05:18 PM, Thierry Reding wrote:
On Thu, Aug 20, 2015 at 09:46:14AM +0530, Archit Taneja wrote:
Hi Thierry, Lucas,
On 08/19/2015 08:32 PM, Thierry Reding wrote:
On Wed, Aug 19, 2015 at 04:52:24PM +0200, Lucas Stach wrote:
Am Mittwoch, den 19.08.2015, 16:34 +0200 schrieb Thierr
On Tuesday, August 18, 2015 at 04:47:35 AM, Brian Norris wrote:
Hi!
[...]
> > The only bizzare thing is this stuff above ^ . If I want to pass for
> > example "m25p,fast-read" to the SPI NOR connected to this controller, I
> > have to set
>
> Do we really want to extend m25p80 properties like '
On Thursday, August 20, 2015 at 06:06:49 PM, vikas wrote:
> Hi,
Hi!
[...]
> >>> It's the location of the SRAM fifo. Also direct mode location I think,
> >>> if that were ever used.
> >>
> >> Hmm...It is the base address of NOR flash. SRAM is not memory mapped.
> >
> > Huh ? I am inclined to t
On Tuesday, August 18, 2015 at 04:34:53 AM, vikas wrote:
> Hi Marek,
Hi,
[...]
> > +#define CQSPI_POLL_IDLE_RETRY 3
> > +
> > +#define CQSPI_REG_SRAM_RESV_WORDS 2
> > +#define CQSPI_REG_SRAM_PARTITION_WR1
>
> remove unused macros.
>
> > +#define CQSPI_
DS26522 is used for tdm, configured by SPI bus.
Add nodes under spi node to t104xd4rdb.dtsi.
Signed-off-by: Zhao Qiang
---
Documentation/devicetree/bindings/net/maxim,ds26522.txt | 13 +
arch/powerpc/boot/dts/t104xd4rdb.dtsi | 10 ++
2 files changed, 23 inse
On Wed, Aug 19, 2015 at 02:49:26PM +0900, Masahiro Yamada wrote:
> This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings
> document says that the bits[15:8] of the 3rd cell of the interrupts
> property represents PPI interrupt CPU mask. Because the timer
> interrupts are wired to all of
On Fri, Aug 21, 2015 at 4:37 AM, Brian Norris
wrote:
> On Thu, Aug 20, 2015 at 05:18:14PM +0800, Viet Nga Dao wrote:
>> You might misunderstand the hardware problem i mention here. This soft
>> IP controller is able to provide the ID for our Altera EPCS/EPCQ flash
>> chips, which are non JEDEC chi
On 20.08.2015 20:34, Pankaj Dubey wrote:
> Hi Krzysztof,
>
> Sorry for delay in reply, as I got busy in some other official
> assignments and could not take this series further at that time.
>
> On Wednesday 27 May 2015 05:22 PM, Krzysztof Kozlowski wrote:
>> W dniu 29.04.2015 o 17:38, Pankaj Dub
On Thu, Aug 20, 2015 at 11:19:11PM +0300, Sergei Shtylyov wrote:
> On 08/20/2015 10:04 PM, Sergei Shtylyov wrote:
>
> >>>Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> >>>'renesas-devel-20150819-v4.2-rc7' tag. Here we add the VIN and ADV7180
> >>>video decoder device
On Thu, Aug 20, 2015 at 05:41:30PM +0530, Vignesh R wrote:
>
>
> On 08/19/2015 11:38 PM, Michael Welling wrote:
> > On Wed, Aug 12, 2015 at 01:44:22PM -0500, Michael Welling wrote:
> >> On Wed, Aug 12, 2015 at 11:56:36AM +0530, Vignesh R wrote:
> >>> Hi Michael,
> >>>
> >>> + Dmitry
> >>>
> >>> O
On Thu, Aug 20, 2015 at 08:23:27AM +0200, Hans de Goede wrote:
> Hi,
>
> On 08/19/2015 05:17 PM, Maxime Ripard wrote:
> >On Fri, Aug 07, 2015 at 05:22:34PM +0200, Hans de Goede wrote:
> >>We've everything we need to support the gmac on Colombus, turn it on.
> >>
> >>Signed-off-by: Hans de Goede
>
On Thursday, August 20, 2015 at 10:19:25 PM, Brian Norris wrote:
> On Thu, Aug 20, 2015 at 12:06:36PM +0200, Alexander Stein wrote:
> > On Thursday 20 August 2015 10:03:38, Marek Vasut wrote:
> > > > +Example:
> > > > +
> > > > + quadspi_controller_0: quadspi@0x180014a0 {
> >
On Thu, Aug 20, 2015 at 12:37:29PM +0100, Jens Wiklander wrote:
> On Wed, Aug 19, 2015 at 05:50:09PM +0100, Will Deacon wrote:
> > On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote:
> > > Adds helpers to do SMC based on ARM SMC Calling Convention.
> > > CONFIG_HAVE_SMCCC is enabled for
On Thu, Aug 20, 2015 at 11:18:50PM +0200, Maxime Ripard wrote:
> at the driver level. And I'm not really sure that we can do much more
> at the framework level either, except maybe handling the timeout
> directly (but then the drivers would have to handle the recovering
> after a timeout too).
We
On Thu, Aug 20, 2015 at 11:58:39PM +0800, Chen-Yu Tsai wrote:
> >> +Child nodes:
> >> +
> >> +An RSB controller node can contain zero or more child nodes representing
> >> +slave devices on the bus. Child 'reg' properties are specified as a
> >> +runtime address, hardware address pair. The hardwar
On Thu, Aug 20, 2015 at 09:45:07PM +0200, Michal Suchanek wrote:
> On 20 August 2015 at 16:48, Maxime Ripard
> wrote:
> > On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
> >> When the maximum transfer speed is not set for a SPI slave the value
> >> remains 0 and the code in sunxi
On Thu, Aug 20, 2015 at 02:08:30PM -0700, Mark Brown wrote:
> On Thu, Aug 20, 2015 at 09:34:33PM +0200, Maxime Ripard wrote:
> > On Thu, Aug 20, 2015 at 11:41:32AM -0700, Mark Brown wrote:
> > > On Thu, Aug 20, 2015 at 02:19:45PM -, Michal Suchanek wrote:
>
> > > > drivers/spi/spi-sun4i.c | 1
On Thu, Aug 20, 2015 at 09:34:33PM +0200, Maxime Ripard wrote:
> On Thu, Aug 20, 2015 at 11:41:32AM -0700, Mark Brown wrote:
> > On Thu, Aug 20, 2015 at 02:19:45PM -, Michal Suchanek wrote:
> > > drivers/spi/spi-sun4i.c | 10 +-
> > > drivers/spi/spi-sun6i.c | 10 +-
> > Are w
On Thu, Aug 20, 2015 at 11:42:18AM +0200, Marek Vasut wrote:
> On Thursday, August 20, 2015 at 11:18:14 AM, Viet Nga Dao wrote:
> > You might misunderstand the hardware problem i mention here. This soft
> > IP controller is able to provide the ID for our Altera EPCS/EPCQ flash
> > chips, which are
On Thu, Aug 20, 2015 at 05:18:14PM +0800, Viet Nga Dao wrote:
> You might misunderstand the hardware problem i mention here. This soft
> IP controller is able to provide the ID for our Altera EPCS/EPCQ flash
> chips, which are non JEDEC chips. As from EPCQ device data sheet
> (https://www.altera.co
On Thu, Aug 20, 2015 at 12:06:36PM +0200, Alexander Stein wrote:
> On Thursday 20 August 2015 10:03:38, Marek Vasut wrote:
> > > +Example:
> > > +
> > > + quadspi_controller_0: quadspi@0x180014a0 {
> > > + compatible = "altr,quadspi-1.0";
> > > +
On 08/20/2015 10:04 PM, Sergei Shtylyov wrote:
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20150819-v4.2-rc7' tag. Here we add the VIN and ADV7180
video decoder device tree support on the R8A7794/SILK board. The patchset
requires previously posted S
Hi Robert,
On Thu, Aug 20, 2015 at 05:25:59PM +0200, Robert Baldyga wrote:
> Hello,
>
> This patchset adds driver for NFC chip Samsung S3FWRN5. First two patches
> are touching NCI core due to some non-standard chip behaviour.
>
> The first one adds post_setup() handler, which is called after NC
Hi Geert,
On Thursday 20 August 2015 09:43:34 Geert Uytterhoeven wrote:
> On Wed, Aug 19, 2015 at 11:29 PM, Laurent Pinchart wrote:
> >> > Also, while you're thinking about the perfect clock binding, please do
> >> > consider dropping clock-output-names if you can. Specifying clock-names
> >> > al
On 20 August 2015 at 16:48, Maxime Ripard
wrote:
> On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
>> When the maximum transfer speed is not set for a SPI slave the value
>> remains 0 and the code in sunxi SPI divides by it. Use an arbitrary
>> speed instead in that case.
>>
>> Si
Verified event and buffer polling works concurrently on the same trigger
with hi-8435.
The buffer interface part for hi-8435 was not sent.
On 20.08.2015 22:37, Vladimir Barinov wrote:
Support triggered events.
This is useful for chips that don't have their own interrupt sources.
It allows to u
Support triggered events.
This is useful for chips that don't have their own interrupt sources.
It allows to use generic/standalone iio triggers for those drivers.
Signed-off-by: Vladimir Barinov
---
Changes in version 2:
- initially added
Changes in version 3:
- fixed grammar in patch descripti
Add Holt Integrated Circuits, Inc. to the list of device tree vendor
prefixes
Signed-off-by: Vladimir Barinov
---
Changes in version 2:
- none
Changes in version 3:
- none
Changes in version 4:
- none
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
d
Add Holt threshold detector driver for HI-8435 chip
Signed-off-by: Vladimir Barinov
---
Changes in version 2:
- Added file sysfs-bus-iio-adc-hi8435
- Changed naming from "discrete ADC" to "threshold detector"
- Replaced swab16p/swab32p with be16_to_cpup/be32_to_cpup
- Made *_show and *_store func
These bindings can be used to register Holt HI-8435 threshold detector
Signed-off-by: Vladimir Barinov
---
Changes in version 2:
- renamed file name hi-843x.txt to hi8435.txt
- removed hi-8436,hi-8436,hi-8437
- removed holt,debounce-soft field
- renamed holt,debounc-soft-delay to holt,debounce-in
Hello,
This adds the folowing:
- Support triggered events
- Add Holt vendor prefix
- Holt threshold detector driver for HI-8435 chip
- Document HI-8435 DT bindings
PDF file can be found here:
http://www.holtic.com/products/3081-hi-8435.aspx
Vladimir Barinov (4):
[1/4] iio: Support triggered even
On Thu, Aug 20, 2015 at 11:41:32AM -0700, Mark Brown wrote:
> On Thu, Aug 20, 2015 at 02:19:45PM -, Michal Suchanek wrote:
>
> > drivers/spi/spi-sun4i.c | 10 +-
> > drivers/spi/spi-sun6i.c | 10 +-
>
> Are we *sure* we can't work on merging these drivers :(
Those are two dif
On 08/20/2015 09:54 PM, Simon Horman wrote:
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20150819-v4.2-rc7' tag. Here we add the VIN and ADV7180
video decoder device tree support on the R8A7794/SILK board. The patchset
requires previously posted SILK
On Thu, Aug 20, 2015 at 02:19:46PM -, Emilio López wrote:
> Signed-off-by: Emilio López
> Tested-by: Michal Suchanek
Also, if you're sending on a patch from someone else you must add a
Signed-off-by, see SubmittingPatches.
signature.asc
Description: Digital signature
On Thu, Aug 20, 2015 at 02:19:46PM -, Emilio López wrote:
> - sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
> + if (sun4i_spi_can_dma(master, spi, tfr) && desc_rx) {
> + /* The receive transfer should be the last one to finish */
> + dma_wait_for_async_tx(desc_r
On Thu, Aug 20, 2015 at 01:20:42AM +0300, Sergei Shtylyov wrote:
> Hello.
>
>Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-20150819-v4.2-rc7' tag. Here we add the VIN and ADV7180
> video decoder device tree support on the R8A7794/SILK board. The patch
On Thu, Aug 20, 2015 at 01:08:33AM +0300, Sergei Shtylyov wrote:
> On 08/20/2015 12:57 AM, Sergei Shtylyov wrote:
>
> >Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
> >'renesas-devel-20150819-v4.2-rc7' tag. Here we add the I2C device tree
> >support
> >for the R8A779
On Thu, Aug 20, 2015 at 02:19:45PM -, Michal Suchanek wrote:
> drivers/spi/spi-sun4i.c | 10 +-
> drivers/spi/spi-sun6i.c | 10 +-
Are we *sure* we can't work on merging these drivers :(
signature.asc
Description: Digital signature
On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
> When the maximum transfer speed is not set for a SPI slave the value
> remains 0 and the code in sunxi SPI divides by it. Use an arbitrary
> speed instead in that case.
You should always be using the transfer speed that is defined
On 08/20/2015 12:23 PM, Mark Rutland wrote:
> Hi,
>
>> +/ {
>> +compatible = "altr,socfpga-stratix10";
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>
> I would recommend that you make your root #address-cells and #size-cells equal
> to 2, as that will simplify matters later if/whe
On Thu, Aug 20, 2015 at 05:19:09PM +0800, Leilk Liu wrote:
> This patch revises littery coding style according to comments.
I can't understand this commit log, sorry - what are the comments that
are being addressed?
> - reg_val |= (((high_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET);
> -
Add a very minimalistic set of Northstar Plus Device Tree files which
describes the SoC and the BCM958625 implementation. The perpherials
described are:
ARM Cortex A9 CPU
2 8250 UARTs
ARM GIC
PL310 L2 Cache
ARM A9 Global timer
Signed-off-by: Jon Mason
Signed-off-by: Kapil Hali
Reviewed-by: Ray
Add the documentation for the Broadcom Northstar Plus device tree
bindings.
Signed-off-by: Jon Mason
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
---
.../devicetree/bindings/arm/bcm/brcm,nsp.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Document
This patch series adds support for the Broadcom Northstar Plus family of
SoCs. NSP is a Cortex A9 based SoC under the Broadcom iProc family.
Jon Mason (5):
dt-bindings: Create Documentation for NSP DT bindings
ARM: NSP: add minimal Northstar Plus device tree
ARM: NSP: Add basic support for
Watchdog driver for Broadcom 7038 and newer chips.
Signed-off-by: Justin Chen
---
drivers/watchdog/Kconfig | 8 ++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/bcm7038_wdt.c | 253 +
3 files changed, 262 insertions(+)
create mode 10064
Add device tree binding docmentation for the watchdog hardware block
on bcm7038 and newer SoCs.
Signed-off-by: Justin Chen
---
.../devicetree/bindings/watchdog/brcm,bcm7038-wdt.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/w
This driver is for a watchdog block contained in all Broadcom Set-top
Box chips since BCM7038. BCM7038 was made public during the 2004 CES,
and since then, many chips use this watchdog block including some cable
modem chips.
Patch 1: watchdog device tree binding documentation
Patch 2: watchdog dr
Hi,
> +/ {
> + compatible = "altr,socfpga-stratix10";
> + #address-cells = <1>;
> + #size-cells = <1>;
I would recommend that you make your root #address-cells and #size-cells equal
to 2, as that will simplify matters later if/when you need to add anything
beyond the first 4GB for som
On Wed, Aug 19, 2015 at 12:20:04PM +0800, Chen-Yu Tsai wrote:
> Reduced Serial Bus (RSB) is an Allwinner proprietery interface
> used to communicate with PMICs and other peripheral ICs.
> drivers/rsb/Kconfig| 11 ++
> drivers/rsb/Makefile | 4 +
> drivers/rsb/rsb-core.c | 511
> +++
On Thu, Aug 20, 2015 at 09:59:27AM +0800, Chen-Yu Tsai wrote:
> On Thu, Aug 20, 2015 at 12:32 AM, Mark Brown wrote:
> > This is flagged as something that is specific to the Allwinner SoCs.
> > Why add generic regmap support rather than just implement the regmap
> > reg_read() and reg_write() in a
On Thu, Aug 20, 2015 at 09:52:46AM -0500, Pledge Roy-R01356 wrote:
> I guess my point isn't getting through - channel-id and cell-index are
> too independent concepts that are coincidentally the same. Cell-index
> is only used by u-boot and is used to determine the portal number. It
> is absolute
Hi,
On 08/19/2015 09:03 PM, Marek Vasut wrote:
> On Tuesday, August 18, 2015 at 10:18:33 PM, vikas wrote:
>> Hi,
>>
>> On 08/18/2015 12:03 PM, Graham Moore wrote:
>>> Hi all,
>>>
>>> On 08/18/2015 12:48 AM, Vikas MANOCHA wrote:
>>>
>>> [...]
>>>
>>> +Required properties:
>>> +- compatible
On Thu, Aug 20, 2015 at 11:08 PM, Maxime Ripard
wrote:
> Hi,
>
> Thanks a lot for working on this.
>
> On Wed, Aug 19, 2015 at 12:20:02PM +0800, Chen-Yu Tsai wrote:
>> Reduced Serial Bus is a proprietary 2-line push-pull serial bus
>> supporting multiple slave devices.
>>
>> It was developed by Al
On 08/20/2015 09:46 AM, Chee Nouk Phoo wrote:
> From: Chee Nouk Phoon
>
> Altera Modular ADC is soft IP that wraps the hardened ADC block in a Max1
> device. It can be configured to dual ADC mode that supports two channel
> synchronous sampling or independent single ADCs. ADC sampled values will
Hi,
On Wed, Aug 19, 2015 at 06:43:16PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> The A20-SOM-EVB is a reference design of a 2-layer board for the
> A20-SOM.
> It expands the features of A20-SOM by adding VGA connector, HDMI
> connector, audio In/Out, LCD connector, 2 Mpix came
Add the devicetree descriptor for the Analog Devices AXI-DMAC DMA
controller. This is a soft peripheral used in FPGAs and the bindings
describe how it is connected to the system (clock, interrupt, memory map)
as well as the configuration options that were used when the peripheral was
instantiated.
Add support for the Analog Devices AXI-DMAC DMA controller. This controller
is a soft peripheral that can be instantiated in a FPGA and is often used
in Analog Devices' reference designs for FPGA platforms.
The peripheral has various configuration options that can be selected at
synthesis time and
Some drivers require non-standard configuration after NCI_CORE_INIT
request, because they need to know ndev->manufact_specific_info or
ndev->manufact_id. This patch adds post_setup handler allowing to do
such custom configuration.
Signed-off-by: Robert Baldyga
---
include/net/nfc/nci_core.h | 1
Add driver for Samsung S3FWRN5 NFC controller.
S3FWRN5 is using NCI protocol and I2C communication interface.
Signed-off-by: Robert Baldyga
---
.../devicetree/bindings/net/nfc/s3fwrn5.txt| 27 ++
MAINTAINERS| 6 +
drivers/nfc/Kconfig
Hello,
This patchset adds driver for NFC chip Samsung S3FWRN5. First two patches
are touching NCI core due to some non-standard chip behaviour.
The first one adds post_setup() handler, which is called after NCI_CORE_INIT
request. It's because we need to read current firmware version from
ndev->m
Some drivers needs to have ability to reinit NCI core, for example after
updating firmware in setup() of post_setup() callback. This patch makes
nci_core_reset() and nci_core_init() functions public, to make it possible.
Signed-off-by: Robert Baldyga
---
include/net/nfc/nci_core.h | 2 ++
net/n
Hi,
Thanks a lot for working on this.
On Wed, Aug 19, 2015 at 12:20:02PM +0800, Chen-Yu Tsai wrote:
> Reduced Serial Bus is a proprietary 2-line push-pull serial bus
> supporting multiple slave devices.
>
> It was developed by Allwinner, Inc. and used by Allwinner and X-Powers,
> Inc. for their
On Fri, Aug 14, 2015 at 04:44:36PM +0200, Hans de Goede wrote:
> From: Ralph Benadski
>
> Enable the otg/drc usb controller on the cubieboard2.
>
> Note this board has the otg-vbus connected directly to the 5v-dcc of
> the board, so there is no vbus0 regulator, nor vbus0-det.
>
> Signed-off-by:
On Thu, Aug 20, 2015 at 09:36:33AM +0200, Hans de Goede wrote:
> Hi,
>
> On 08/20/2015 08:45 AM, Maxime Ripard wrote:
> >On Fri, Aug 14, 2015 at 04:44:35PM +0200, Hans de Goede wrote:
> >>From: Jelle van der Waa
> >>
> >>Enable the otg/drc usb controller on the pcDuino 3.
> >>
> >>Note this board
On Thu, Aug 20, 2015 at 02:19:47PM -, Michal Suchanek wrote:
> According to datasheet some pins are available on A10s only while others
> are shared with A13.
>
> Signed-off-by: Michal Suchanek
> ---
> This time add all spi pins and make the CS pins separate as is seen with
> current sun4i DT
On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
> Only SPI0 is enabled. The schematic denotes it as the only SPI bus.
> Other SPI pins are reserved for different peripherals.
>
> Signed-off-by: Michal Suchanek
What device is connected to the other end?
> ---
> arch/arm/boot/dt
On Thu, Aug 20, 2015 at 02:19:46PM -, Emilio López wrote:
> From: Emilio López
>
> This patch adds support for 64 byte or bigger transfers on the
> sun4i SPI controller. Said transfers will be performed via DMA.
>
> Signed-off-by: Emilio López
> Tested-by: Michal Suchanek
This should have
On Thu, Aug 20, 2015 at 2:23 PM, Hans de Goede wrote:
> Hi,
>
> On 08/19/2015 05:17 PM, Maxime Ripard wrote:
>>
>> On Fri, Aug 07, 2015 at 05:22:34PM +0200, Hans de Goede wrote:
>>>
>>> We've everything we need to support the gmac on Colombus, turn it on.
>>>
>>> Signed-off-by: Hans de Goede
>>
>
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, August 19, 2015 5:30 PM
> To: Pledge Roy-R01356
> Cc: linuxppc-...@lists.ozlabs.org; devicetree@vger.kernel.org; Bucur
> Madalin-Cristian-B32716; Wang Haiying-R54964
> Subject: Re: [PATCH 1/2] powerpc/qman: Change fsl,qman-
On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
> When testing SPI without DMA I noticed that filling the FIFO on the
> spi controller causes timeout.
>
> Always leave room for one byte in the FIFO.
>
> Signed-off-by: Michal Suchanek
> ---
> drivers/spi/spi-sun4i.c | 6 +-
>
On Thu, Aug 20, 2015 at 02:19:46PM -, Michal Suchanek wrote:
> When the maximum transfer speed is not set for a SPI slave the value
> remains 0 and the code in sunxi SPI divides by it. Use an arbitrary
> speed instead in that case.
>
> Signed-off-by: Michal Suchanek
spi->max_speed_hz is set
On Thu, Aug 20, 2015 at 02:19:45PM -, Michal Suchanek wrote:
> The trasfer timeout is fixed at 1000 ms. Reading a 4Mbyte flash over
> 1MHz SPI bus takes way longer than that. Calculate the timeout from the
> actual time the transfer is supposed to take and multiply by 2 for good
> measure.
>
>
On 08/17/2015 04:10 PM, Yingjoe Chen wrote:
On Thu, 2015-08-13 at 10:35 +0200, Daniel Lezcano wrote:
On 07/22/2015 10:14 AM, Yingjoe Chen wrote:
Spurious mtk timer interrupt is noticed at boot and cause kernel
crash. It seems if GPT is enabled, it will latch irq status even
when its IRQ is disa
On 20 August 2015 at 16:19, Emilio López wrote:
> From: Emilio López
Something went wrong with overriding the headers
Sorry
Michal
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Hi Yiping,
Thanks for review, please see below comments.
On Thu, Aug 20, 2015 at 01:42:58PM +0800, YiPing Xu wrote:
> On 2015/8/20 10:53, Leo Yan wrote:
> >Add driver for Hi6220 mailbox, the mailbox communicates with MCU; for
> >sending data, it can support two methods for low level implementatio
2015-08-17 15:42 GMT+08:00 Lee Jones :
> On Mon, 17 Aug 2015, Barry Song wrote:
>
>> 2015-07-22 21:04 GMT+08:00 Lee Jones :
>> > Lots of platforms contain clocks which if turned off would prove fatal.
>> > The only way to recover from these catastrophic failures is to restart
>> > the board(s). No
Hi,
On Monday 03 August 2015 05:56 PM, Kishon Vijay Abraham I wrote:
> Changes from v1:
> *) return on -EPROBE_DEFER and other fatal errors. (Don't return only
>if the return value is -ENODEV)
> *) Remove the beagle x15 dts patch. It can be part of a different
>series.
> *) Avoid using reg
On 24.07.2015 13:52, Wolfram Sang wrote:
At the begin of my work on this patchset I even denied clock disable call if
slave is registered (to minimize code that can affect transfer).
I hacked something like this, but it seems it was not enough.
If only slave mode is used, then this logic is
On 08/19/2015 11:38 PM, Michael Welling wrote:
> On Wed, Aug 12, 2015 at 01:44:22PM -0500, Michael Welling wrote:
>> On Wed, Aug 12, 2015 at 11:56:36AM +0530, Vignesh R wrote:
>>> Hi Michael,
>>>
>>> + Dmitry
>>>
>>> On 08/12/2015 12:15 AM, Michael Welling wrote:
Adds a device tree parameter
Hi Krzysztof,
On Wednesday 27 May 2015 04:51 PM, Krzysztof Kozlowski wrote:
2015-04-29 17:38 GMT+09:00 Pankaj Dubey :
This patch adds exynos-srom binding information for SROM Controller
driver on Exynos SoCs.
CC: Rob Herring
CC: Mark Rutland
CC: Ian Campbell
Signed-off-by: Pankaj Dubey
---
Hi,
On Wednesday 27 May 2015 05:32 PM, Krzysztof Kozlowski wrote:
W dniu 29.04.2015 o 17:38, Pankaj Dubey pisze:
Add SROM device node for exynos4.
Subject prefix: "ARM: dts:"
Ok.
CC: Rob Herring
CC: Mark Rutland
CC: Ian Campbell
Signed-off-by: Pankaj Dubey
---
arch/arm/boot/dts/exy
On Wed, Aug 19, 2015 at 05:50:09PM +0100, Will Deacon wrote:
> On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote:
> > Adds helpers to do SMC based on ARM SMC Calling Convention.
> > CONFIG_HAVE_SMCCC is enabled for architectures that may support
> > the SMC instruction. It's the respon
Hi Krzysztof,
On Wednesday 27 May 2015 05:26 PM, Krzysztof Kozlowski wrote:
W dniu 29.04.2015 o 17:38, Pankaj Dubey pisze:
As now we have dedicated driver for SROM controller, it will take care
of saving register banks during S2R so we can safely remove these
settings from mach-exynos.
Signed-
On 08/19/2015 06:50 PM, Will Deacon wrote:
> On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote:
>> Adds helpers to do SMC based on ARM SMC Calling Convention.
>> CONFIG_HAVE_SMCCC is enabled for architectures that may support
>> the SMC instruction. It's the responsibility of the calle
Hi Krzysztof,
Sorry for delay in reply, as I got busy in some other official
assignments and could not take this series further at that time.
On Wednesday 27 May 2015 05:22 PM, Krzysztof Kozlowski wrote:
W dniu 29.04.2015 o 17:38, Pankaj Dubey pisze:
This patch adds Exynos SROM controller dr
Hi Lucas
Again many thanks for explaining and for your time.
I got your point now and I have dug a bit better in the PCI_DOMAINS code.
However I have a question...see inline below
> -Original Message-
> From: Lucas Stach [mailto:l.st...@pengutronix.de]
> Sent: Thursday, August 20, 2015
This patch fixes the an locking issue where client callback performs
further submission.
Signed-off-by: Rameshwar Prasad Sahu
---
drivers/dma/xgene-dma.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/
Hi Ravi,
I'm wondering is your e-mail come from eDP thread ? cause I see lots of
cc guys some as eDP emails :)
And for your question, I am not sure I understand rightly. Do you mean
that your ".ko" module not in
the same directory with driver source code?
If it's your question, I think you
Add support for UPISEMI us5182d als and proximity sensor.
Supports raw readings.
Data sheet for this device can be found here:
http://www.upi-semi.com/temp/uS5182D-DS-P0103-temp.pdf
Signed-off-by: Adriana Reus
---
Changes since v5:
* fixed typos (thank you, Peter)
drivers/iio/light/Kconfig
Added entries in i2c/vendor-prefixes for the us5182d als and proximity sensor.
Also added a documentation file for this sensor's properties.
Signed-off-by: Adriana Reus
---
.../devicetree/bindings/iio/light/us5182d.txt | 23 ++
.../devicetree/bindings/vendor-prefixes.txt
This series adds basic support for this als and proximity sensor
and devicetree docs.
Adriana Reus (2):
iio: light: Add support for UPISEMI uS5182d als and proximity sensor
devicetree: Add documentation for UPISEMI us5182d ALS and Proximity
sensor
.../devicetree/bindings/iio/light/us5182
Hello Marek,
On Thursday 20 August 2015 10:03:38, Marek Vasut wrote:
> > +Example:
> > +
> > + quadspi_controller_0: quadspi@0x180014a0 {
> > + compatible = "altr,quadspi-1.0";
> > + reg = <0x180014a0 0x0020>,
> > +
On Thursday, August 20, 2015 at 11:18:14 AM, Viet Nga Dao wrote:
Hi,
[...]
> >> That is why we decided to upstream the
> >> driver. If the hardware fix, there might not need to have any changes
> >> in driver to support or if yes, it will be just minor.
> >
> > If the hardware can do proper REA
> Add support for UPISEMI us5182d als and proximity sensor.
> Supports raw readings.
> Data sheet for this device can be found here:
> http://www.upi-semi.com/temp/uS5182D-DS-P0103-temp.pdf
nitpicking below
> Signed-off-by: Adriana Reus
> ---
> Changes since v4:
> * Added a comment explainin
From: Chee Nouk Phoon
Altera Modular ADC is soft IP that wraps the hardened ADC block in a Max1
device. It can be configured to dual ADC mode that supports two channel
synchronous sampling or independent single ADCs. ADC sampled values will be
written into memory slots in sequence determined by a
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