Hi Irina,
[auto build test ERROR on v4.3-rc4 -- if it's inappropriate base, please ignore]
config: x86_64-randconfig-h0-10110617 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/in
Jisheng,
On Fri, Oct 09, 2015 at 07:56:43PM +0800, Jisheng Zhang wrote:
> This series adds support for Marvell berlin4ct pin-controller, allowing
> to configure the pin muxing from the device tree.
For the whole series,
Acked-by: Antoine Tenart
Thanks!
Antoine
>
> Since v4:
> - drop ARCH_B
Hi Jisheng,
Please keep Acked-by tags when you submit a new version of a series.
Thanks,
Antoine
On Fri, Oct 09, 2015 at 07:56:43PM +0800, Jisheng Zhang wrote:
> This series adds support for Marvell berlin4ct pin-controller, allowing
> to configure the pin muxing from the device tree.
>
> Sinc
Hi Jisheng,
On Fri, Oct 09, 2015 at 05:22:38PM +0800, Jisheng Zhang wrote:
> On Fri, 9 Oct 2015 11:03:53 +0200
> Antoine Tenart wrote:
> >
> > Finally you can move the OF dependency to the PINCTRL_BERLIN config as
> > all Berlin pinctrl drivers depends on it.
>
> PINCTRL_BERLIN isn't user visib
The power configuration on this board is the same as the pcDuino v3.
This will enable frequency/voltage scaling over the standard A20
operating points from 144 MHz to 960 MHz.
Tested using cpufreq-ljt-stress-test on two pcDuino v3 Nano boards; also
tested successfully with voltages reduced by 0.02
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Chang
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Ch
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (T
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7G
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the connect
This phy driver is binded with the Rockchip DisplayPort
driver, here are the brief properties:
edp_phy: edp-phy@ff770274 {
compatible = "rockchip,rk3288-dp-phy";
rockchip,grf = <&grf>;
clocks = <&cru SCLK_EDP_24M>;
clock-names
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
num
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compati
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Signed-off-by: Yakir
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
fr
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix the wrong code in previous series, an
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
contro
On 10/03/2015 12:22 AM, Jon Mason wrote:
> Add the 4708, 4709, and 953012k SVKs to the the documentation for the
> Broadcom Northstar device tree bindings.
>
> Signed-off-by: Jon Mason
> ---
> Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt | 7 +++
> 1 file changed, 7 insertions(
On 10/03/2015 12:22 AM, Jon Mason wrote:
> Add device tree files for Broadcom Northstar based SVKs. Since the
> bcm5301x.dtsi already exists, all that is necessary is the dts files to
> enable the UARTs (and specify the RAM size for the 4708/9). With these
> files, the SVKs are able to boot to sh
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
On 10/07/2015 01:05 PM, Yakir Yang wrote:
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
On 10/07/2015 11:02 AM, Yakir Yang wrote:
On 10/07/2015 04:46 PM, Javier Martinez Can
On Sat, Oct 10, 2015 at 8:52 PM, Adam Sampson wrote:
> The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
> single RT9701GB regulator, which has its enable input tied to the A20's
> PD2 pin, pulled up to 3v3 via a 10k resistor.
>
> However, the script.bin that shipped with the de
The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
single RT9701GB regulator, which has its enable input tied to the A20's
PD2 pin, pulled up to 3v3 via a 10k resistor.
However, the script.bin that shipped with the device listed PH11 and PH3
as Vbus control pins for the two USB p
Chen-Yu Tsai writes:
> Since Siarhei spotted the issue, maybe add a Reported-by tag where credit
> is due?
Will do.
>> ®_ahci_5v {
>> + pinctrl-names = "default";
[twice]
>
> This is already in sunxi-common-regulators.dtsi.
> No need to add it again.
OK -- fixed. v2 incoming.
Thanks,
On 10/10/2015 04:29 AM, Stefan Agner wrote:
> Many boards use an alias in the stdout-path specification along
> with console options after a colon (e.g. serial0:115200n8). When
> using earlycon, this specification currently does not work. While
> fdt_path_offset supports alias resolution, it does n
Hi Maxime,
I wanted to discuss this with you at ELCE, but I forgot.
I still believe that just setting the regulator to always-on
is the best option, see the end of the quoted mail why I think
that the other options are not a good idea.
I would really like to see this resolved...
On 22-09-15 17
The correct core clock of spdif is SPDIF_GCLK, which is added to
clock tree. So the dts also need to be updated.
Signed-off-by: Shengjiu Wang
---
arch/arm/boot/dts/imx6qdl.dtsi | 12 ++--
arch/arm/boot/dts/imx6sl.dtsi | 16
arch/arm/boot/dts/imx6sx.dtsi | 2 +-
3 file
Correct SPDIF clock setting issue in clock tree, the SPDIF_GCLK is also
one clock of SPDIF, which is missed before.
We found an issue that imx can't enter low power mode with spdif
if IMX6x_CLK_SPDIF is used as the core clock of spdif. Because
spdif driver will register IMX6x_CLK_SPDIF clock to re
Add SPDIF_GCLK clock in clock tree
Shengjiu Wang (2):
clk: imx6: Add SPDIF_GCLK clock in clock tree
ARM: dts: imx6: change the core clock of spdif
Changes in v3:
- refine the commit logs.
arch/arm/boot/dts/imx6qdl.dtsi| 12 ++--
arch/arm/boot/dts/imx6sl.dtsi
sclk_mipidsi_24m is the gating of mipi dsi phy.
Signed-off-by: Chris Zhong
---
drivers/clk/rockchip/clk-rk3288.c | 2 +-
include/dt-bindings/clock/rk3288-cru.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk
This tv080wum-nl0 panel is a mipi panel, it can use in MIPI_TX socket
of rk3288 evb board.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288-evb.dtsi | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
b/arch/arm/boo
Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Chris Zhong
---
arch/arm/boot/dts/rk3288.dtsi | 39 +++
1 file changed, 39 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk
From: Liu Ying
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying
Signed-off-by: Chris Zhong
---
.../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++
1 file changed, 76 insertions(+)
cre
add device tree bindings for rk3288 specific Synopsys DW MIPI DSI driver
Signed-off-by: Chris Zhong
---
.../bindings/video/dw_mipi_dsi_rockchip.txt| 56 ++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/video/dw_mipi_dsi_rockc
The rk3288 MIPI DSI is a Synopsys DesignWare MIPI DSI host controller
IP. This series adds support for a Synopsys DesignWare MIPI DSI host
controller DRM bridge driver and a rockchip MIPI DSI specific DRM
driver.
This series also includes a DRM panel driver for BOE TV080WUM-NL0 panel.
This panel o
Many boards use an alias in the stdout-path specification along
with console options after a colon (e.g. serial0:115200n8). When
using earlycon, this specification currently does not work. While
fdt_path_offset supports alias resolution, it does not remove the
console options by itself. Use the fdt
updates the bindings documents and dtsi file according to the review
comments from Rob Herring
Signed-off-by: huangdaode
Signed-off-by: yankejian
---
Documentation/devicetree/bindings/net/hisilicon-hns-mdio.txt | 2 +-
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 8 +++-
Hi Arnd,
2015-10-06 15:22 GMT+01:00 Arnd Bergmann :
> On Tuesday 06 October 2015 16:20:23 Arnd Bergmann wrote:
>> On Friday 18 September 2015 13:37:31 Masahiro Yamada wrote:
>> > Hi Olof,
>> >
>> > Now Linux 4.3-rc1 is out, so I am back to this.
>> >
>> > 1/3: add outer cache support
>> > 2/3: re
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