Hi Sinan,
[auto build test ERROR on v4.4-rc5]
[also build test ERROR on next-20151218]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-driver/20151218-010637
config: sparc64-allmodconfig (attached as .config)
reproduce:
wget
https
Hi Sinan,
[auto build test ERROR on v4.4-rc5]
[also build test ERROR on next-20151218]
url:
https://github.com/0day-ci/linux/commits/Sinan-Kaya/dma-add-Qualcomm-Technologies-HIDMA-driver/20151218-010637
config: sparc-allyesconfig (attached as .config)
reproduce:
wget
https
On Fri, 2015-12-18 at 21:58 -0600, Rob Herring wrote:
> On Tue, Dec 15, 2015 at 10:26:21PM +0300, Sergei Ianovich wrote:
> > +Example:
> > +
> > + fpga: fpga@1706 {
>
> Nothing else in the fpga? In any case, this node should be named
> interrupt-controller@1706.
>
> > + compa
On Thu, Dec 17, 2015 at 11:55:28AM -0600, Rob Herring wrote:
> On Tue, Dec 8, 2015 at 2:47 AM, Sudip Mukherjee
> wrote:
> > We are having build failure with linux-next for sparc allmodconfig with
> > the error messages:
> >
> > drivers/built-in.o: In function `meson6_timer_init':
> > meson6_timer.
On Tue, Dec 15, 2015 at 11:01:34PM +0100, Peter Rosin wrote:
> From: Peter Rosin
>
> Signed-off-by: Peter Rosin
> ---
> .../devicetree/bindings/gpio/gpio-sx150x.txt | 3 +-
For the binding:
Acked-by: Rob Herring
> drivers/gpio/gpio-sx150x.c | 53
> +++
On Thu, Dec 17, 2015 at 10:21:50PM +0800, Caesar Wang wrote:
> This patchset is the initiation version to try work
> for kylin board.
>
> Signed-off-by: Caesar Wang
> ---
>
> Documentation/devicetree/bindings/arm/rockchip.txt | 4 +
> arch/arm/boot/dts/Makefile | 1 +
On Fri, Dec 18, 2015 at 01:47:14AM +0300, Sergei Shtylyov wrote:
> Maxim Integrated MAX3355E chip integrates a charge pump and comparators to
> enable a system with an integrated USB OTG dual-role transceiver to
> function as an USB OTG dual-role device. In addition to sensing/controlling
> Vbus, t
On Tue, Dec 15, 2015 at 03:35:57PM -0800, Eric Anholt wrote:
> These will be used for enabling UART1, SPI1, and SPI2.
>
> Signed-off-by: Eric Anholt
> ---
>
> v2: Make the binding cover both the IRQ and clock enable registers.
>
> .../bindings/clock/brcm,bcm2835-aux-clock.txt | 31
>
On Wed, Dec 16, 2015 at 01:55:13PM +, Mans Rullgard wrote:
> This adds a binding for the Wolfson WM8974 mono audio codec.
>
> Signed-off-by: Mans Rullgard
> ---
> Sending this patch again, this time including Mark Brown.
> ---
> Documentation/devicetree/bindings/sound/wlf,wm8974.txt | 15 +++
On Thu, Dec 17, 2015 at 12:40:26PM +0100, Marcus Weseloh wrote:
> Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
> SPI slave devices to set a wait time between the transmission of words.
>
> Signed-off-by: Marcus Weseloh
> ---
> Documentation/devicetree/bindings/spi/sp
On Wed, Dec 16, 2015 at 01:51:50PM +0900, Simon Horman wrote:
> This extends the documentation of compatibility strings a little to
> include the SoC names.
>
> Signed-off-by: Simon Horman
> Acked-by: Kuninori Morimoto
>
> ---
> v3
> * Split into separate patch
> ---
> Documentation/devicetree
On Tue, Dec 15, 2015 at 11:52:10AM -0800, Tim Bird wrote:
> Add a binding for the regulator which controls the OTG chargepath switch.
> The OTG switch gets its power from pm8941_5vs1, and that should be
> expressed as a usb_otg_in-supply property in the DT node for the
> charger driver. The regula
On Tue, Dec 15, 2015 at 10:26:21PM +0300, Sergei Ianovich wrote:
> ICP DAS LP-8x4x contains FPGA chip. The chip functions as an interrupt
> source providing 16 additional interrupts among other things. The
> interrupt lines are muxed to a GPIO pin of a 2nd level PXA-GPIO
> interrupt controller. GPI
On Wed, Dec 16, 2015 at 01:31:30PM +, Måns Rullgård wrote:
> Mark,
>
> This is the 1/1 you were missing.
>
> Am I the only one who is annoyed by scripts/get_maintainer.pl not
> returning all the addresses it should in cases like this? Is there some
> trick I'm missing?
Documentation/devicet
On Wed, Dec 16, 2015 at 11:51:59AM +0900, Yoshihiro Shimoda wrote:
> R-Car H3 has USB3.0 peripheral controllers. This controller's has the
> following features:
> - Supports super, high and full speed
> - Contains 30 pipes for bulk or interrupt transfer
> - Contains dedicated DMA controller
>
>
On Wed, Dec 16, 2015 at 03:55:10PM -0800, Eric Anholt wrote:
> Signed-off-by: Eric Anholt
> ---
> Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4
> 1 file changed, 4 insertions(+)
Acked-by: Rob Herring
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On Thu, Dec 17, 2015 at 05:50:00PM +0800, Songjun Wu wrote:
> DT binding documentation for this new ASoC driver.
>
> Signed-off-by: Songjun Wu
> ---
>
> Changes in v2: None
>
> .../devicetree/bindings/sound/atmel-pdmic.txt | 55
>
> 1 file changed, 55 insertions(+)
On Wed, Dec 16, 2015 at 07:44:18PM +0100, Wolfram Sang wrote:
> From: Wolfram Sang
>
> We need this binding because some I2C master drivers will need to adapt
> their PM settings for the arbitration circuitry. I skipped the "i2c-"
> prefix because I can imagine to be useful outside of i2c.
>
> S
On Wed, Dec 16, 2015 at 01:51:51PM +0900, Simon Horman wrote:
> Add fallback compatibility strings for R-Car Gen2 and Gen3.
> This is in keeping with the fallback scheme being adopted wherever
> appropriate for drivers for Renesas SoCs.
>
> Signed-off-by: Simon Horman
> Acked-by: Kuninori Morimot
On Thu, Dec 17, 2015 at 02:59:09AM +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> Signed-off-by: Kuninori Morimoto
> ---
> .../devicetree/bindings/sound/renesas,rsnd.txt | 40
> ++
> 1 file changed, 40 insertions(+)
Acked-by: Rob Herring
--
To unsubs
On Thu, Dec 17, 2015 at 03:00:10AM +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> This patch adds Multi channel support on Renesas R-Car sound.
> This patch is tested on Salvator-X board, but it can't use
> Multi channel, because supported format is different between
> codec chi
On Thu, Dec 17, 2015 at 11:45:19AM +0800, Mark Yao wrote:
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian Campbell
> Cc: Kumar Gala
> Cc: devicetree@vger.kernel.org
>
> Signed-off-by: Mark Yao
Acked-by: Rob Herring
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On Thu, Dec 17, 2015 at 02:59:31AM +, Kuninori Morimoto wrote:
> From: Kuninori Morimoto
>
> Signed-off-by: Kuninori Morimoto
> ---
> .../devicetree/bindings/sound/renesas,rsnd.txt| 19
> +++
> 1 file changed, 19 insertions(+)
Acked-by: Rob Herring
--
To unsubscri
On Thu, Dec 17, 2015 at 05:58:47PM +0100, Marc Titinger wrote:
> From: Kumar Gala
>
> The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
> on Qualcomm MSM platforms to determine which device tree should be
> utilized and passed to the kernel.
>
> Cc:
> Signed-off-by: Kumar
On Thu, Dec 17, 2015 at 12:01:17PM -0500, Sinan Kaya wrote:
> Add documentation for the Qualcomm Technologies HIDMA driver.
>
> Signed-off-by: Sinan Kaya
> ---
> .../devicetree/bindings/dma/qcom_hidma_mgmt.txt| 79
> ++
> 1 file changed, 79 insertions(+)
> create mode 1
On Fri, Dec 18, 2015 at 04:09:39PM +0800, Yong Wu wrote:
> This patch add mediatek iommu dts binding document.
>
> Signed-off-by: Yong Wu
Acked-by: Rob Herring
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the body of a message to majord...@vger.kernel.org
More maj
On Fri, Dec 18, 2015 at 12:25:51AM +, Kuninori Morimoto wrote:
>
> From: Kuninori Morimoto
>
> This patch enables to use thermal-zone on DT if it was calles as
> "renesas,rcar-thermal-gen2".
> Previous style (= non thermal-zone) is still supported by
> "renesas,rcar-thermal" to keep compatib
On Fri, Dec 18, 2015 at 05:33:56PM +0800, Peter Chen wrote:
> Add dt-binding documentation for generic onboard USB device.
As has already been mentioned, please following the existing USB device
binding convention. We can debate whether the kernel driver is tied into
existing USB drivers or sepa
On Fri, Dec 18, 2015 at 09:30:49PM +0800, Vishnu Patekar wrote:
> Allwinner A83T is octa-core cortex-a7 based SoC.
> It's clock control unit and prcm, pinmux are different from previous sun8i
> series.
> Its processor cores are arragned in two clusters 4 cores each,
> similar to A80.
>
> Signed-of
On Fri, Dec 18, 2015 at 11:33 PM, Mark Rutland wrote:
> On Fri, Dec 18, 2015 at 09:00:18PM +0530, Ganapatrao Kulkarni wrote:
>> Hi Mark,
>>
>> On Fri, Dec 18, 2015 at 7:48 PM, Mark Rutland wrote:
>> >> +- distance-matrix
>> >> + This property defines a matrix to describe the relative distances
>
On 17.12.2015 07:57, Peter Chen wrote:
> On Wed, Dec 16, 2015 at 09:05:35PM +0100, Maciej S. Szmigiero wrote:
>> Hi Fabio,
>> Hi Peter,
>>
>> On 16.12.2015 11:11, Fabio Estevam wrote:
>>> Hi Peter,
>>>
>>> On Wed, Dec 16, 2015 at 2:11 AM, Peter Chen
>>> wrote:
>>>
Thanks, Fabio, but I am cur
Maxim Integrated MAX3355E chip integrates a charge pump and comparators to
enable a system with an integrated USB OTG dual-role transceiver to
function as an USB OTG dual-role device. In addition to sensing/controlling
Vbus, the chip also passes thru the ID signal from the USB OTG connector.
On som
On Fri, Dec 18, 2015 at 11:02:40AM +0800, Bayi Cheng wrote:
> Move write data register before excute command to avoid
> missing first byte write to nor flash
>
> Signed-off-by: Bayi Cheng
> ---
> the previous patch didn't drop the Change-Id
Applied to l2-mtd.git
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On Tuesday 15 December 2015 00:58:26 Rafael J. Wysocki wrote:
> On Thursday, November 26, 2015 05:21:11 PM Jia Hongtao wrote:
> > Register the qoriq cpufreq driver as a cooling device, based on the
> > thermal device tree framework. When temperature crosses the passive trip
> > point cpufreq is use
Hello.
On 12/19/2015 12:37 AM, Jon Mason wrote:
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason
---
a
On Friday 18 December 2015 16:37:56 Jon Mason wrote:
> + cru: cru@1800c184 {
> + compatible = "syscon";
> + reg = <0x1800c184 0xc>;
> + };
It's unusual for a device to start at such an odd address. Are you sure
it's not a larger device starting at 0x1800c000
Hi,
On Fri, Dec 18, 2015 at 09:30:50PM +0800, Vishnu Patekar wrote:
> Allwinner A83T is new octa-core cortex-a7 SOC.
> This adds the basic dtsi, the clocks differs from
> earlier sun8i SOCs.
>
> Signed-off-by: Vishnu Patekar
> ---
> arch/arm/boot/dts/sun8i-a83t.dtsi | 206
> +++
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 15 ---
Add the ability to reboot via a reset of the processor. This is
achieved via a write of 0x39 to the CRU Reset Register. Unfortunately,
this only resets the core and not the other IP blocks. So if possible,
other methods should be used on the individual boards.
Signed-off-by: Jon Mason
---
arc
Add I2C support to the bcm5301x Device Tree. Since no driver changes
are needed to enable this hardware, only the device tree changes are
required to make this functional.
Signed-off-by: Jon Mason
---
arch/arm/boot/dts/bcm5301x.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/a
On Fri, Dec 18, 2015 at 11:52:22AM +0300, Aleksei Mamlin wrote:
> Add a backlight for controlling the lcd panel backlight on Wexler TAB7200
> tablet
>
> Signed-off-by: Aleksei Mamlin
This one doesn't apply (probably because of some dependency on the
first patch).
Thanks!
Maxime
--
Maxime Rip
On Fri, Dec 18, 2015 at 11:52:08AM +0300, Aleksei Mamlin wrote:
> Wexler TAB7200 tablet use channel 0 of the PWM controller for backlight
> dimming
>
> Signed-off-by: Aleksei Mamlin
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http:/
Hi,
On Fri, Dec 18, 2015 at 11:51:50AM +0300, Aleksei Mamlin wrote:
> Add a node for the Goodix GT911 touchscreen found on the Wexler TAB7200 tablet
>
> Signed-off-by: Aleksei Mamlin
> ---
> arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 19 +++
> 1 file changed, 19 insertions
On Fri, Dec 11, 2015 at 07:43:59PM +0100, Hans de Goede wrote:
> The pov protab2-ips9 tablet uses the A10's integrated audio codec,
> enable it.
>
> Signed-off-by: Hans de Goede
Applied 3 and 4. Thanks!
I have a bad network connection for the next two weeks though, so I'm
not quite sure whether
On 12/18/2015 10:02 PM, Damien Riegel wrote:
> On Fri, Dec 18, 2015 at 09:41:47PM +0100, Marc Kleine-Budde wrote:
>> On 12/18/2015 09:17 PM, Damien Riegel wrote:
>>> Technologic Systems provides an IP compatible with the SJA1000,
>>> instantiated in an FPGA. Because of some bus widths issue, access
On Fri, Dec 18, 2015 at 09:41:47PM +0100, Marc Kleine-Budde wrote:
> On 12/18/2015 09:17 PM, Damien Riegel wrote:
> > Technologic Systems provides an IP compatible with the SJA1000,
> > instantiated in an FPGA. Because of some bus widths issue, access to
> > registers is made through a "window" tha
On Mon, Dec 14, 2015 at 05:07:47PM +0100, Hans de Goede wrote:
> >>+static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
> >>+struct snd_kcontrol *k, int event)
> >>+{
> >>+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
> >>+
> >>+
On Thu, Dec 17, 2015 at 12:40:26PM +0100, Marcus Weseloh wrote:
> Adds a new property "spi-word-wait-ns" to the spi-bus binding that allows
> SPI slave devices to set a wait time between the transmission of words.
>
> Signed-off-by: Marcus Weseloh
Reviewed-by: Maxime Ripard
Thanks!
Maxime
--
Hi,
On Thu, Dec 17, 2015 at 12:40:27PM +0100, Marcus Weseloh wrote:
> Modifies the sun4i SPI master driver to make use of the
> "spi-word-wait-ns" property. This specific SPI controller needs 3 clock
> cycles to set up the delay, which makes the minimum non-zero wait time
> on this hardware 4 cloc
On Wed, Dec 16, 2015 at 12:21:48PM +0100, Philipp Zabel wrote:
> Hi Maxime,
>
> Am Mittwoch, den 16.12.2015, 11:29 +0100 schrieb Maxime Ripard:
> > On Mon, Dec 14, 2015 at 10:50:55AM +0100, Philipp Zabel wrote:
> > > Am Montag, den 14.12.2015, 10:36 +0100 schrieb Maxime Ripard:
> > > > Hi,
> > > >
On 12/18/2015 09:17 PM, Damien Riegel wrote:
> Technologic Systems provides an IP compatible with the SJA1000,
> instantiated in an FPGA. Because of some bus widths issue, access to
> registers is made through a "window" that works like this:
>
> base + 0x0: address to read/write
> base +
This commit adds documentation for the Technologic Systems version of
SJA1000. The difference with the NXP version is in the way the registers
are accessed.
Signed-off-by: Damien Riegel
---
Documentation/devicetree/bindings/net/can/sja1000.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
Technologic Systems provides an IP compatible with the SJA1000,
instantiated in an FPGA. Because of some bus widths issue, access to
registers is made through a "window" that works like this:
base + 0x0: address to read/write
base + 0x2: 8-bit register value
This commit adds a new compati
This commit adds support for the TS-4800 interrupt controller. This
controller is instantiated in a companion FPGA, and multiplex interrupts
for other FPGA IPs.
As this component is external to the SoC, the SoC might need to reserve
pins, so this controller is implemented as a platform driver and
This is an interrupt-controller implemented in an FPGA, to multiplex
interrupts generated from other IPs. The FPGA usually uses a GPIO as a
parent interrupt controller to notify that one of the multiplexed
interrupts has triggered.
Signed-off-by: Damien Riegel
---
.../bindings/interrupt-controll
On Thu, Oct 15, 2015 at 12:37:23PM -0500, Franklin S Cooper Jr wrote:
> NAND DMA prefetch has been broken for awhile and seems to have only
> worked for SDMA based devices
>
> This patchset fixes DMA prefetch to work on both EDMA and SDMA devices
>
> Test on:
> am335x gp evm
> am437x gp evm
> am3
On Fri, Dec 18, 2015 at 09:00:18PM +0530, Ganapatrao Kulkarni wrote:
> Hi Mark,
>
> On Fri, Dec 18, 2015 at 7:48 PM, Mark Rutland wrote:
> >> +- distance-matrix
> >> + This property defines a matrix to describe the relative distances
> >> + between all numa nodes.
> >> + It is represented as a
On 18/12/15 08:09, Yong Wu wrote:
This patch adds support for mediatek m4u (MultiMedia Memory Management
Unit).
Signed-off-by: Yong Wu
---
drivers/iommu/Kconfig | 14 +
drivers/iommu/Makefile| 1 +
drivers/iommu/mtk_iommu.c | 734 ++
3
This commit adds LCD support for the TS-4800. The panel is an Okaya
RS800480T-7X0WQ and the timings have been extracted from Technologic
Systems' tree.
Signed-off-by: Damien Riegel
---
arch/arm/boot/dts/imx51-ts4800.dts | 109 +
1 file changed, 109 insertions(
This commit enables the touchscreen on TS-4800, using the ts4800-ts
driver.
Signed-off-by: Damien Riegel
---
arch/arm/boot/dts/imx51-ts4800.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts
b/arch/arm/boot/dts/imx51-ts4800.dts
index 4951ebd..e5e9bd
* Vignesh R [151217 21:51]:
>
>
> On 12/18/2015 12:15 AM, Tony Lindgren wrote:
> > * Rob Herring [151211 07:10]:
> >> On Fri, Dec 11, 2015 at 09:39:59AM +0530, Vignesh R wrote:
> >>> Add qspi memory mapped region entries for DRA7xx based SoCs. Also,
> >>> update the binding documents for the co
On Mon, Dec 14, 2015 at 03:42:07PM -0700, Joshua Henderson wrote:
dt/bindings: ... is preferred for the subject.
> This adds support for the Microchip PIC32 platform along with the
> specific variant PIC32MZDA on a PIC32MZDA Starter Kit.
>
> Signed-off-by: Joshua Henderson
> Cc: Ralf Baechle
On Mon, Dec 14, 2015 at 03:42:05PM -0700, Joshua Henderson wrote:
> From: Purna Chandra Mandal
>
> Document the devicetree bindings for the clock driver found on Microchip
> PIC32 class devices.
>
> Signed-off-by: Purna Chandra Mandal
> Signed-off-by: Joshua Henderson
> Cc: Ralf Baechle
A co
On Fri, 18 Dec 2015, Peter Chen wrote:
> On Fri, Dec 18, 2015 at 12:13 AM, Alan Stern
> wrote:
> > It's not clear (to me, anyway) how this is meant to work. USB is a
> > completely discoverable bus: There is no way to represent devices
> > statically; they have to be discovered. But a device
Hi Mark,
On Fri, Dec 18, 2015 at 7:48 PM, Mark Rutland wrote:
> Hi,
>
>> +==
>> +2 - numa-node-id
>> +==
>> +
>> +For the purpose of identificat
On Fri, 2015-12-11 at 17:07 +0800, Biao Huang wrote:
> Add mt2701 support using mediatek common pinctrl driver.
> MT2701 have some special pins need an extra setting register
> than other ICs, so adding this support to common code.
>
> Signed-off-by: Biao Huang
> ---
> drivers/pinctrl/mediatek/K
Hi,
> +==
> +2 - numa-node-id
> +==
> +
> +For the purpose of identification, each NUMA node is associated with a unique
> +token known as a node
On Fri, Dec 18, 2015 at 6:08 PM, Stanimir Varbanov
wrote:
> There is no guarantees that enabling ATU will hit the hardware
> immediately, and subsequent accesses to configuration / IO spaces
> are reliable. So fixing this by read back PCIE_ATU_CR2 register
> just after writing.
>
> Without such a
Hello.
On 12/18/2015 4:14 AM, Chanwoo Choi wrote:
Except for just one comment below, Looks good to me.
Acked-by: Chanwoo Choi
I'll wait for a few days to get the review from DT maintainer
before applying it on extcon-next branch.
On 2015년 12월 18일 07:47, Sergei Shtylyov wrote:
Maxim Inte
Hi Luka,
Did you have the time to look at those issues ?
Yoann
Le 06/11/2015 17:05, Yoann Sculo a écrit :
Hi Luka,
I tested your patch on the GoFlex Home.
+gpio-leds {
+compatible = "gpio-leds";
+
+health {
+label = "status:green:health";
+gpios =
Hi Simon,
On Thu, Dec 10, 2015 at 8:02 AM, Simon Horman wrote:
> On Tue, Dec 08, 2015 at 06:54:05PM +0100, Geert Uytterhoeven wrote:
>> This patch series updates the console parameters in the DTSes for
>> various Renesas ARM boards.
>>
>> - For all of them, the serial port config is added to
>>
* Vinod Koul [151217 21:14]:
> On Thu, Dec 17, 2015 at 09:48:44AM -0800, Tony Lindgren wrote:
> > * Peter Ujfalusi [151217 05:33]:
> > > Hi,
> > >
> > > Changes since v1:
> > > - Updated to use the non 16bit arrays [1]
> > > - send the two patch as a series
> > >
> > > [1]
> > > As it has been
On 18/12/15 13:33, Geert Uytterhoeven wrote:
Hi Dirk,
On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme wrote:
On 18.12.2015 12:03, Geert Uytterhoeven wrote:
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
From: Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node
Hi Stanimir,
[auto build test WARNING on next-20151218]
[also build test WARNING on v4.4-rc5]
[cannot apply to pci/next robh/for-next v4.4-rc5 v4.4-rc4 v4.4-rc3]
url:
https://github.com/0day-ci/linux/commits/Stanimir-Varbanov/Qualcomm-PCIe-driver-and-designware-fixes/20151218-205427
drivers/pci/host/pcie-qcom.c:188:1-3: WARNING: PTR_ERR_OR_ZERO can be used
drivers/pci/host/pcie-qcom.c:220:1-3: WARNING: PTR_ERR_OR_ZERO can be used
Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR
Generated by: scripts/coccinelle/api/ptr_ret.cocci
CC: Stanimir Varbanov
Signed-off-b
Hello.
On 12/18/2015 3:19 AM, Krzysztof Kozlowski wrote:
[...]
Please pass the source through recent coccicheck and fix the findings.
Has it been included in the kernel source somewhere already?
The rules detecting the unnecessary owner should be there for some time
(sice 4.2 or 4.1?).
Hi Dirk,
On Fri, Dec 18, 2015 at 12:56 PM, Dirk Behme wrote:
> On 18.12.2015 12:03, Geert Uytterhoeven wrote:
>> On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
>>> From: Geert Uytterhoeven
>>>
>>> Add device nodes for the L2 caches, and link the CPU node to its L2
>>> cache node.
>>>
>>> Th
Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.
Signed-off-by: Vishnu Patekar
---
Documentation/arm/sunxi/README | 1
H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.
A83T patches are tested on this board.
It has UART, ethernet, USB, HDMI, etc ports on it.
For FEL mode it needs USB A-A(Male) cable. I used uart0 which
is multiplexed to microsd pins PF2 a
Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.
Signed-off-by: Vishnu Patekar
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 206 ++
1 file changed, 206 insertions(+)
create mode 100644 arch/arm/bo
This patch series adds very basic support for Allwinner A83T SOC.
Clock, peripherals, smp support will be added later.
Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two cluster
From: Stanimir Varbanov
The PCIe driver reuse the Designware common code for host
and MSI initialization, and also program the Qualcomm
application specific registers.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Stanimir Varbanov
---
MAINTAINERS |7 +
drivers/pci/host
From: Stanimir Varbanov
Document Qualcomm PCIe driver devicetree bindings.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Stanimir Varbanov
Acked-by: Rob Herring
---
.../devicetree/bindings/pci/qcom,pcie.txt | 233
1 file changed, 233 insertions(+)
create mod
There is no guarantees that enabling ATU will hit the hardware
immediately, and subsequent accesses to configuration / IO spaces
are reliable. So fixing this by read back PCIE_ATU_CR2 register
just after writing.
Without such a fix the PCI device enumeration during kernel boot
is not reliable, and
Add the pcie dt node so that it can probe and used.
Signed-off-by: Stanimir Varbanov
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index
Enable pcie dt node and fill pcie dt node with regulator, pinctrl
and reset gpio, to use the pcie on the ifc6410 board.
Signed-off-by: Stanimir Varbanov
---
arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/
Hi,
I'm sending v5 with following changes:
- in 1/5 - replace wmb() call with PCIE_ATU_CR2 register read.
- in 3/5 - addressed comments from Born Helgaas about usage of a
standard PCI capabilities register names and rename link training
function to the way that other Designware based drivers use.
Hi Geert,
On 18.12.2015 12:02, Geert Uytterhoeven wrote:
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
From: Takeshi Kihara
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Signed-off-by: Takeshi Kihara
Signed-off-
On 18.12.2015 12:03, Geert Uytterhoeven wrote:
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
From: Geert Uytterhoeven
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB
Hello.
On 12/18/2015 1:21 PM, Kishon Vijay Abraham I wrote:
Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm/boot/dts/dra7.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/a
Hi Brian,
I will be on vacation till 2016 January, 4th.
I will try to answer your questions as soon as possible.
Best regards,
Cyrille
Le 18/12/2015 02:55, Brian Norris a écrit :
> Hi Cyrille,
>
> On Mon, Dec 07, 2015 at 03:09:10PM +0100, Cyrille Pitchen wrote:
>> The quad (or dual) mode of a
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
> From: Geert Uytterhoeven
>
> Add device nodes for the L2 caches, and link the CPU node to its L2
> cache node.
>
> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
> 128 KiB x 16 ways).
>
> The L2 cache for the C
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme wrote:
> From: Takeshi Kihara
>
> This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
> cores (4 x Cortex-A57 + 4 x Cortex-A53).
>
> Signed-off-by: Takeshi Kihara
> Signed-off-by: Dirk Behme
Thanks, I can confirm this works
On Fri, Dec 18, 2015 at 11:08:26AM +0100, Alexander Aring wrote:
> Hi Eric,
>
> On Wed, Dec 16, 2015 at 03:55:07PM -0800, Eric Anholt wrote:
> > This is a major rewrite of the previous Raspberry Pi 2 submission.
> > SMP support is now included, and the DT includes are cleaned up to
> > avoid massi
On Fri, Dec 18, 2015 at 10:06:48AM +0100, Arnd Bergmann wrote:
> On Friday 18 December 2015 08:35:32 Wolfram Sang wrote:
> > >
> > > It seems to me that we have some consensus around:
> > >
> > > compatible = "renesas,r1ex24002", "24c02";
> >
> > Thinking again, "generic,24c02" or "generic
Hi,
On Tuesday 15 December 2015 06:52 PM, Sergei Shtylyov wrote:
> Hello.
>
> On 12/15/2015 12:39 PM, Kishon Vijay Abraham I wrote:
>
>> Add new device tree node for the control module register space where
>> PCIe registers are present.
>>
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> ar
Hi,
On Tuesday 15 December 2015 08:56 PM, Tony Lindgren wrote:
> * Kishon Vijay Abraham I [151215 04:47]:
>> On Tuesday 15 December 2015 05:25 PM, Arnd Bergmann wrote:
>
> Can you explain here what the conversion is good for? Why do you
> prefer the syscon mapping over a high-level dr
Hi Yong,
[auto build test ERROR on tegra/for-next]
[also build test ERROR on v4.4-rc5]
[cannot apply to iommu/next next-20151217]
url:
https://github.com/0day-ci/linux/commits/Yong-Wu/MT8173-IOMMU-SUPPORT/20151218-161550
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux for
Hi Eric,
On Wed, Dec 16, 2015 at 03:55:07PM -0800, Eric Anholt wrote:
> This is a major rewrite of the previous Raspberry Pi 2 submission.
> SMP support is now included, and the DT includes are cleaned up to
> avoid massive duplication.
>
> The branch (based on 4.4-rc5, to get the USB regression
Hi Eric,
On Wed, Dec 16, 2015 at 03:55:11PM -0800, Eric Anholt wrote:
> The set of peripherals remained constant across bcm2835 (Raspberry Pi
> 1) and bcm2836 (Raspberry Pi 2), but the CPU was swapped out. Split
> the files so that we can include just peripheral setup in 2836.
>
> Signed-off-by:
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