On 11 September 2014 16:11, Arnd Bergmann wrote:
> On Thursday 11 September 2014 15:50:49 Naveen Krishna Chatradhi wrote:
>> + aliases {
>> + serial0 = &serial_0;
>> + serial1 = &serial_1;
>> + serial2 = &serial_2;
>> + serial3 = &seria
On 9 September 2014 08:58, wrote:
> Naveen Krishna Chatradhi wrote:
>>
>> Add initial device tree nodes for EXYNOS7 SoC and board dts file
>> to support Espresso board based on Exynos7 SoC.
>>
>> Signed-off-by: Naveen Krishna Chatradhi
>> Cc: Rob Herring
>> Cc: Catalin Marinas
>> ---
>> arch/
Hi Mark,
On 27 August 2014 16:39, Mark Rutland wrote:
> Hi,
>
> On Wed, Aug 27, 2014 at 10:44:20AM +0100, Naveen Krishna Chatradhi wrote:
>> From: Alim Akhtar
>>
>> This patch adds the necessary Kconfig entries to enable
>> support for the ARMv8 based Exynos7 SoC.
>>
>> Signed-off-by: Alim Akhta
Hi Olof,
On 28 August 2014 09:26, Olof Johansson wrote:
> Hi,
>
> On Wed, Aug 27, 2014 at 03:14:18PM +0530, Naveen Krishna Chatradhi wrote:
>> Add initial device tree nodes for EXYNOS7 SoC.
>> Also, includes the dt-binding definitions for clock ids.
>
> Uh, no -- it just adds the dtsi.
Ok. Will
Hi Tomasz,
On 27 August 2014 17:00, Tomasz Figa wrote:
> Hi Naveen,
>
> Please see my comments inline.
>
> On 27.08.2014 11:44, Naveen Krishna Chatradhi wrote:
>> Add initial device tree nodes for EXYNOS7 SoC.
>> Also, includes the dt-binding definitions for clock ids.
>>
>> Signed-off-by: Naveen
Hi Olof,
On 28 August 2014 09:33, Olof Johansson wrote:
> On Wed, Aug 27, 2014 at 03:15:40PM +0530, Naveen Krishna Chatradhi wrote:
>> The i2c-exynos5.c driver can be reused for the HSI2C controller
>> on Exynos7 SoCs from Samsung.
>>
>> This patch adds the Kconfig dependency to choose i2c-exynos
Hi Mark,
On 27 August 2014 16:12, Mark Rutland wrote:
> Hi Naveen,
>
> On Wed, Aug 27, 2014 at 10:44:18AM +0100, Naveen Krishna Chatradhi wrote:
>> Add initial device tree nodes for EXYNOS7 SoC.
>> Also, includes the dt-binding definitions for clock ids.
>
> Fallout from a rebase? That latter par
Hello Olof,
On 28 August 2014 09:30, Olof Johansson wrote:
> Hi,
>
> On Wed, Aug 27, 2014 at 03:14:19PM +0530, Naveen Krishna Chatradhi wrote:
>> This patch adds initial dts file for the Espresso board
>> based on Exynos7 from Samsung.
>>
>> Signed-off-by: Naveen Krishna Chatradhi
>> Cc: Rob Her
Hello Tomasz,
On 27 August 2014 16:44, Tomasz Figa wrote:
> Hi Naveen,
>
> Please see my comments inline.
>
> On 27.08.2014 11:44, Naveen Krishna Chatradhi wrote:
>> Add the required pin configuration support to EXYNOS7
>
> [snip]
>
>> +/ {
>> + /* ALIVE block @1058 */
>> + pinctrl@10
Hello All,
On 18 July 2014 15:43, Naveen Krishna Ch wrote:
> Hello Arnd,
>
> On 18 July 2014 15:08, Arnd Bergmann wrote:
>> On Friday 18 July 2014 14:59:42 Chanwoo Choi wrote:
>>> This patchset support Exynos3250 ADC (Analog Digital Converter) because
>>> Exynos
Hello Arnd,
On 18 July 2014 15:08, Arnd Bergmann wrote:
> On Friday 18 July 2014 14:59:42 Chanwoo Choi wrote:
>> This patchset support Exynos3250 ADC (Analog Digital Converter) because
>> Exynos3250 has additional special clock for ADC IP.
>>
>
> by coincidence, I have just looked at the same dri
Hello Arnd,
On 18 July 2014 15:12, Arnd Bergmann wrote:
> On Friday 18 July 2014 14:59:43 Chanwoo Choi wrote:
>> This patchset add 'exynos_adc_data' structure which includes some functions
>> to control ADC operation and specific data according to ADC version (v1 or
>> v2).
>>
>
> This new struc
Hello Sachin,
On 17 July 2014 17:24, Sachin Kamat wrote:
> Hi Naveen,
>
> On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
> wrote:
>> This patch updates the IIO based ADC driver to use syscon and regmap
>> APIs to access and use PMU registers instead of remapping the PMU
>> registers i
Hello Jonathan,
On 15 July 2014 23:45, Jonathan Cameron wrote:
> On 15/07/14 19:13, Jonathan Cameron wrote:
>>
>> On 11/07/14 10:06, Naveen Krishna Chatradhi wrote:
>>>
>>> This patch does the following
>>> 1. Use the syscon and Regmap API instead of ioremappaing the
>>> ADC_PHY register from
Hello Kukjin,
On 25 June 2014 19:42, Guenter Roeck wrote:
> On 06/25/2014 03:57 AM, Kukjin Kim wrote:
>>
>> Naveen Krishna Chatradhi wrote:
>>>
>>>
>> + Jean Delvare, Guenter Roeck
>>
>> I'm adding maintainers for drivers/hwmon/ntc* but I'm not sure.
>>
>> Hi,
>>
>> This series looks good to me.
Hello Mark,
On 16 July 2014 21:32, Mark Brown wrote:
> On Wed, Jul 16, 2014 at 05:19:06PM +0200, Javier Martinez Canillas wrote:
>
>> The feedback from Naveen's series was that the patches did not
>> provide a clear explanation about the rationale and goal of both
>> the series as a whole and the
Hello Javier,
On 16 July 2014 20:49, Javier Martinez Canillas
wrote:
> Hello Mark,
>
> The s3c64xx SPI driver DT binding is currently broken. Commit
> 3146bee ("spi: s3c64xx: Added provision for dedicated cs pin")
> added a new "cs-gpio" property and made it a requirement in
> order to make the d
Hello Tomasz,
On 15 July 2014 22:25, Tomasz Figa wrote:
> Hi Naveen,
>
> On 14.07.2014 07:41, Naveen Krishna Chatradhi wrote:
>> Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
>>
>> spi-s3c64xx.c driver expects
>> 1. chip select gpios from "cs-gpio"(singular) under the
>>
Hello Mark,
On 15 July 2014 00:45, Mark Brown wrote:
> On Tue, Jul 15, 2014 at 12:31:32AM +0530, Naveen Krishna Ch wrote:
>
>> in this case spi-s3c64xx.c will continue to ignore the generic SPI "cs-gpios"
>> implementation.
>
>> I'm willing to implement
Hello Mark,
On 14 July 2014 22:55, Mark Brown wrote:
> On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
>
>> @@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
>> spi->controller_data = cs;
>> }
>>
>> + /* For the non-DT plat
Hello Sachin,
On 11 July 2014 14:47, Sachin Kamat wrote:
> Hi Naveen,
>
> On Fri, Jul 11, 2014 at 2:36 PM, Naveen Krishna Chatradhi
> wrote:
>> The DT bindings in exynos-adc.txt applies to the ADC
>> driver (exynos-adc.c) developed based on IIO framework.
>>
>> The bindings are more appropriate
Hello Mark,
On 7 July 2014 13:02, Mark Brown wrote:
> On Mon, Jul 07, 2014 at 11:51:38AM +0530, Naveen Krishna Ch wrote:
>> On 2 July 2014 22:26, Mark Brown wrote:
>> > On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
>
>> >> Hence, spi-
Hello Mark,
Thanks for the review.
On 2 July 2014 22:26, Mark Brown wrote:
> On Fri, Jun 13, 2014 at 09:29:50AM +0530, Naveen Krishna Chatradhi wrote:
>
>> Hence, spi-s3c64xx.c is broken since "Jun 21 11:26:12 2013" and
>> considering the time with no compliants about the breakage.
>
> I'm not c
Hello Doug and Kukjin,
On 26 June 2014 21:16, Doug Anderson wrote:
> Naveen,
>
> On Thu, Jun 26, 2014 at 5:19 AM, Naveen Krishna Chatradhi
> wrote:
>> Exynos5250 based Snow board has 4 NTC thermistors to measure
>> temperatures at various points on the board.
>>
>> IIO based ADC becomes the pare
Hello Javier,
On 26 June 2014 20:51, Javier Martinez Canillas wrote:
> Hello Naveen,
>
> On Thu, Jun 26, 2014 at 2:19 PM, Naveen Krishna Chatradhi
> wrote:
>> This patchset does the following
>> 1. Create a common dtsi file cros-exynos-peach.dtsi for
>>exynos5420-peach-pit.dts and exynos5800
Hello Javier,
On 26 June 2014 00:33, Javier Martinez Canillas
wrote:
> MAX77802 is a PMIC that contains 10 high efficiency Buck regulators,
> 32 Low-dropout (LDO) regulators, two 32kHz buffered clock outputs,
> a Real-Time-Clock (RTC) and a I2C interface to program the individual
> regulators, cl
Hello Kukjin,
On 26 June 2014 11:46, Naveen Krishna Ch wrote:
> Doug,
>
> On 26 June 2014 02:10, Doug Anderson wrote:
>> Naveen,
>>
>> On Tue, Jun 24, 2014 at 11:29 PM, Naveen Krishna Chatradhi
>> wrote:
>>> Exynos5420 based Peach PIT board has 4 NTC
Hello Doug, Kukjin,
On 26 June 2014 11:46, Naveen Krishna Ch wrote:
> Doug,
>
> On 26 June 2014 02:10, Doug Anderson wrote:
>> Naveen,
>>
>> On Tue, Jun 24, 2014 at 11:29 PM, Naveen Krishna Chatradhi
>> wrote:
>>> Exynos5420 based Peach
Doug,
On 26 June 2014 02:10, Doug Anderson wrote:
> Naveen,
>
> On Tue, Jun 24, 2014 at 11:29 PM, Naveen Krishna Chatradhi
> wrote:
>> Exynos5420 based Peach PIT board has 4 NTC thermistors to measure
>> temperatures at various points on the board.
>>
>> IIO based ADC becomes the parent and NTC
Hello Javier,
On 25 June 2014 16:06, Javier Martinez Canillas wrote:
> Hello Naveen,
>
> On Wed, Jun 25, 2014 at 8:29 AM, Naveen Krishna Chatradhi
> wrote:
>> Murata Manufacturing Co., Ltd is the vendor for
>> NTC (Negative Temperature coefficient) based Thermistors.
>> But, the driver extensive
Doug,
On 25 June 2014 03:24, Doug Anderson wrote:
> Naveen,
>
> On Tue, Jun 24, 2014 at 5:19 AM, Naveen Krishna Chatradhi
> wrote:
>> Exynos5420 based Peach PIT and Exynos5800 based PI boards have
>> 4 NTC thermistors to measure temperatures at various points on the
>> board.
>>
>> IIO based ADC
Hello Mark,
On 24 June 2014 19:03, Mark Rutland wrote:
> On Tue, Jun 24, 2014 at 01:19:15PM +0100, Naveen Krishna Chatradhi wrote:
>> As Murata is the Manufactures the NTC thermistors. The vendor
>> name in the compatibility is preposed to change to "murata, ncpXXX"
>>
>> This patch uses the new
Hello Mark,
On 24 June 2014 19:02, Mark Rutland wrote:
> On Tue, Jun 24, 2014 at 01:19:14PM +0100, Naveen Krishna Chatradhi wrote:
>> Murata Manufacturing Co., Ltd is the vendor for
>> NTC (Negative Temperature coefficient) based Thermistors.
>> But, the driver extensively uses "NTC" as the vendo
Hello Mark,
On 24 June 2014 19:00, Mark Rutland wrote:
> On Tue, Jun 24, 2014 at 01:19:13PM +0100, Naveen Krishna Chatradhi wrote:
>> Add Murata Manufacturing Co., Ltd. to the list of device tree
>> vendor prefixes.
>>
>> Murata manufactures NTC (Negative Temperature Coefficient) based
>> Thermis
Hello Mark,
On 21 June 2014 15:21, Mark Brown wrote:
> On Fri, Jun 20, 2014 at 02:18:08PM -0700, Doug Anderson wrote:
>
>> Is one of you two planning to apply (parts 1 and 2)? I know that
>> Kukjin needs to handle the part 3 (the .dts files)...
>
>> Ideally it seems like it could go to 3.16 sinc
Hello Tomasz,
On 20 June 2014 06:00, Tomasz Figa wrote:
> On 20.06.2014 02:28, Chanwoo Choi wrote:
>> On 06/20/2014 09:24 AM, Tomasz Figa wrote:
>>> On 20.06.2014 02:22, Chanwoo Choi wrote:
Hi Tomasz,
On 06/18/2014 04:58 PM, Tomasz Figa wrote:
> Hi Chanwoo,
>
> On 18.06
Hello Chanwoo,
On 18 June 2014 07:51, Chanwoo Choi wrote:
> This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
> special clock ('sclk_tsadc') for ADC which provide clock to internal ADC.
>
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmin Park
Changes look good to m
Hello Chanwoo,
On 18 June 2014 07:50, Chanwoo Choi wrote:
> This patchset add 'exynos_adc_ops' structure which includes some functions
> to control ADC operation according to ADC version (v1 or v2).
>
> Signed-off-by: Chanwoo Choi
> Acked-by: Kyungmin Park
This is a good piece of change, Thank
Hello Javier,
On 12 June 2014 19:36, Javier Martinez Canillas
wrote:
> Hello Naveen,
>
> On 06/12/2014 03:13 PM, Naveen Krishna Chatradhi wrote:
>> Use controller_data structure only for the Non Device tree platforms.
>> For Device tree platforms, always derive the chipselect info from
>> DT nod
Hello Javier,
On 12 June 2014 19:30, Javier Martinez Canillas
wrote:
> Hello Naveen,
>
> On 06/12/2014 03:13 PM, Naveen Krishna Chatradhi wrote:
>> Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
>>
>> spi-s3c64xx.c driver expects
>> 1. chip select gpios from "cs-gpio"(singula
Hello Tomasz,
On 11 June 2014 23:20, Tomasz Figa wrote:
> On 11.06.2014 19:27, Javier Martinez Canillas wrote:
>> On 06/11/2014 01:38 PM, Naveen Krishna Ch wrote:
>>> On 11 June 2014 16:43, Javier Martinez Canillas
>>> wrote:
>>>> On 06/11/2014 0
Hello Javier,
On 11 June 2014 16:43, Javier Martinez Canillas
wrote:
> Hello Naveen,
>
> Thanks a lot for your patches and sorry that I didn't review your prior two
> versions but I didn't have the time yesterday.
>
> On 06/11/2014 08:31 AM, Naveen Krishna Chatradhi wrote:
>> Currently, spi-s3c64
Hello Javier,
On 11 June 2014 16:51, Javier Martinez Canillas
wrote:
> Hello Naveen,
>
> On 06/11/2014 08:31 AM, Naveen Krishna Chatradhi wrote:
>> This patch moves the "cs-gpio" field from "controller-data" child
>> node to under the spi device node.
>>
>
> Your patch looks good to me but I thin
Hello Tomasz,
On 11 June 2014 01:19, Tomasz Figa wrote:
> Hi Naveen,
>
> On 10.06.2014 12:08, Naveen Krishna Chatradhi wrote:
>> Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
>> defined under "controller-data" node under each slave node.
>
> [snip]
>
>> @@ -85,6 +83,7 @@ Example
Hello Doug,
On 10 June 2014 23:56, Doug Anderson wrote:
> Naveen,
>
> Not a full review, but a few quick things I happened to notice:
>
> On Tue, Jun 10, 2014 at 3:08 AM, Naveen Krishna Chatradhi
> wrote:
>> @@ -94,7 +93,6 @@ Example:
>> spi-max-frequency = <1>;
>>
>>
Hello Sylwester,
Thanks for the review.
On 10 June 2014 16:09, Sylwester Nawrocki wrote:
> On 10/06/14 12:08, Naveen Krishna Chatradhi wrote:
>> Currently, spi-s3c64xx.c needs "cs-gpio" chip select GPIO to be
>> defined under "controller-data" node under each slave node.
>>
>> &spi_x {
>> c
Hello Tomasz,
On 20 March 2014 00:58, Tomasz Figa wrote:
> Hi Leela,
>
>
> On 19.03.2014 12:19, Leela Krishna Amudala wrote:
>>
>> Hi All,
>>
>> I didn't see this series in mainline, Any comments for this ?
>
>
> Naveen had posted v12 of this series and I believe all the patches got my
> Reviewed
Hello Mark,
On 10 February 2014 16:37, Mark Rutland wrote:
> On Mon, Feb 10, 2014 at 10:50:01AM +0000, Naveen Krishna Ch wrote:
>> Hello Mark,
>>
>> On 10 February 2014 16:03, Mark Rutland wrote:
>> > On Thu, Nov 07, 2013 at 12:42:34PM +, Naveen Krishna Chatra
Hello Mark,
On 10 February 2014 16:03, Mark Rutland wrote:
> On Thu, Nov 07, 2013 at 12:42:34PM +, Naveen Krishna Chatradhi wrote:
>> On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
>> the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
>> should be
Hello All,
On 19 December 2013 11:36, Naveen Krishna Chatradhi
wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "re
Hello All,
On 19 December 2013 17:04, Tomasz Figa wrote:
> On Thursday 19 of December 2013 11:36:31 Naveen Krishna Chatradhi wrote:
>> Exynos5420 has 5 TMU channels, the TRIMINFO register is
>> misplaced for TMU channels 2, 3 and 4
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIM
Hello All,
On 2 January 2014 11:37, Zhang Rui wrote:
> On Thu, 2013-11-07 at 18:12 +0530, Naveen Krishna Chatradhi wrote:
>> On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
>> the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
>> should be acompanied by
Hello All,
On 2 January 2014 08:03, Zhang Rui wrote:
> On Thu, 2013-12-19 at 11:35 +0530, Naveen Krishna Chatradhi wrote:
>> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
>> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
>> Currently, inten_rise_shi
Hello Tomasz,
On 18 December 2013 21:20, Tomasz Figa wrote:
> Hi Naveen,
>
> On Tuesday 10 of December 2013 12:12:25 Naveen Krishna Chatradhi wrote:
>> Exynos5420 has 5 TMU channels, the TRIMINFO register is
>> misplaced for TMU channels 2, 3 and 4
>> TRIMINFO at 0x1006c000 contains data for TMU
Hello All,
On 19 November 2013 18:35, Naveen Krishna Chatradhi
wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a contains data for TMU channel 4
> TRIMINFO at 0
Hello All,
On 19 November 2013 18:34, Naveen Krishna Chatradhi
wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "re
Hello All,
On 12 November 2013 12:05, Naveen Krishna Chatradhi
wrote:
> This patchset does a little clean up of the existing code
> 1. [v9] thermal: samsung: replace inten_ bit fields with intclr_
> 2. [v9] thermal: samsung: change base_common to more meaningful base_second
>
> adds support for
Hello All,
On 12 November 2013 12:06, Naveen Krishna Chatradhi
wrote:
> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
>
Hello All,
On 12 November 2013 12:06, Naveen Krishna Chatradhi
wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "re
Hello All,
On 12 November 2013 12:07, Naveen Krishna Chatradhi
wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a contains data for TMU channel 4
> TRIMINFO at 0
Hello All,
On 12 November 2013 12:07, Naveen Krishna Chatradhi
wrote:
> Exynos5420 SoC has per core thermal management unit.
> 5 TMU channels 4 for CPUs and 5th for GPU.
>
> This patch adds the device tree nodes to the DT device list.
>
> Nodes carry the misplaced second base address and the seco
Hello Tomasz,
On 7 November 2013 20:39, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 11:23:32 Naveen Krishna Chatradhi wrote:
>> This patch adds the neccessary register changes and arch information
>> to support Exynos5420 SoCs
>> Exynos5420 has 5 TMU channels one for each
Hello Tomasz,
On 7 November 2013 22:15, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 22:02:10 Naveen Krishna Ch wrote:
>> Hello Tomasz,
>>
>> On 7 November 2013 19:53, Tomasz Figa wrote:
>> > Hi Naveen,
>> >
>> > O
Hello Tomasz,
On 7 November 2013 19:53, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
>> Exynos5420 SoC has per core thermal management unit.
>> 5 TMU channels 4 for CPUs and 5th for GPU.
>>
>> This patch adds the device tree nodes to
On 7 November 2013 19:48, Tomasz Figa wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 18:12:34 Naveen Krishna Chatradhi wrote:
>> On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
>> the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
>> should be a
On 7 November 2013 18:52, Naveen Krishna Chatradhi
wrote:
> Exynos5420 SoC has 7 High speed I2C channels, This patch adds
> the device tree nodes to the DT device list.
>
> Signed-off-by: Naveen Krishna Chatradhi
> Signed-off-by: Andrew Bresticker
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 9
Hi Bartlomiej,
On 7 November 2013 16:18, Bartlomiej Zolnierkiewicz
wrote:
>
> Hi,
>
> On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote:
>> On Exynos5250, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT register
Hello Bartlomiej,
My reply is very long delayed sorry.
On 17 October 2013 15:33, Bartlomiej Zolnierkiewicz
wrote:
>
> Hi Naveen,
>
> On Thursday, October 17, 2013 08:41:13 AM Naveen Krishna Chatradhi wrote:
>> On Exynos5250, the FALL interrupt related en, status and clear bits are
>> available a
On 23 October 2013 07:14, Chanwoo Choi wrote:
> This patch fix typo of property name from 'pullup-uV' to 'pullup-uv'.
> The ntc_thermistor.c use 'pullup-uv' when parsing dt data.
>
> Signed-off-by: Chanwoo Choi
Thanks for the correction.
Acked-by: Naveen Krishna Chatradhi
> ---
> Documentatio
On 14 October 2013 21:31, Bartlomiej Zolnierkiewicz
wrote:
> On Monday, October 14, 2013 10:18:03 AM Eduardo Valentin wrote:
>> On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
>> >
>> > Hi,
>> >
>> > On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
>> >> Hi Naveen,
>> >>
>> >>
Hello Bartlomiej,
On 3 October 2013 18:12, Bartlomiej Zolnierkiewicz
wrote:
>
> Hi,
>
> I would like to see few minor cleanup changes, please see below:
Sure.
>
> On Thursday, October 03, 2013 05:31:42 PM Naveen Krishna Ch wrote:
>> On 4 September 2013 09:53, Naveen Kri
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