On 03/12/15 11:52, Brian Norris wrote:
> Hi,
>
> On Thu, Dec 03, 2015 at 11:38:14AM +0530, Roger Quadros wrote:
>> On 03/12/15 10:39, Brian Norris wrote:
>>> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>>>> We do a couple of things in this
Brian,
On 03/12/15 10:39, Brian Norris wrote:
> Hi,
>
> On Fri, Sep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>> Hi,
>>
>> We do a couple of things in this series which result in
>> cleaner device tree implementation, faster perfomance and
>> multi
Brian,
On 03/12/15 09:59, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Oct 06, 2015 at 01:35:48PM +0300, Roger Quadros wrote:
>> Move NAND specific device tree parsing to NAND driver.
>>
>> The NAND controller node must have a compatible id, register space
>>
Brian,
On 02/12/15 08:56, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Dec 01, 2015 at 04:41:16PM +0200, Roger Quadros wrote:
>> On 30/11/15 21:54, Brian Norris wrote:
>>> On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote:
>>>> On 26/10/15 23:23, B
Hi Brian,
On 30/11/15 21:54, Brian Norris wrote:
> Hi Roger,
>
> On Tue, Oct 27, 2015 at 11:37:03AM +0200, Roger Quadros wrote:
>> On 26/10/15 23:23, Brian Norris wrote:
>>> I'm not too familiar with OMAP platforms, and I might have missed out on
>>> prior
Brian,
On 27/10/15 11:37, Roger Quadros wrote:
> Hi Brian,
>
> On 26/10/15 23:23, Brian Norris wrote:
>> Hi Roger,
>>
>> I'm not too familiar with OMAP platforms, and I might have missed out on
>> prior discussions/context, so please forgive if I'm ask
Hi,
On 25/08/15 17:50, Ulf Hansson wrote:
> On 3 August 2015 at 14:26, Kishon Vijay Abraham I wrote:
>> From: Roger Quadros
>>
>> For platforms that doesn't have explicit regulator control in MMC,
>> populate voltage-ranges in MMC device tree node and us
ep 18, 2015 at 05:53:22PM +0300, Roger Quadros wrote:
>> - Remove NAND IRQ handling from omap-gpmc driver, share the GPMC IRQ
>> with the omap2-nand driver and handle NAND IRQ events in the NAND driver.
>> This causes performance increase when using prefetch-irq mode.
>> 30%
Boris,
On 27/10/15 10:12, Boris Brezillon wrote:
> Hi Roger,
>
> On Tue, 27 Oct 2015 10:03:02 +0200
> Roger Quadros wrote:
>
>> On 26/10/15 22:49, Brian Norris wrote:
>>>
>>> Others have been looking at using GPIOs for the ready/busy pin too. At a
>>
On 26/10/15 22:49, Brian Norris wrote:
> + others
>
> A few comments below.
>
> On Fri, Sep 18, 2015 at 05:53:40PM +0300, Roger Quadros wrote:
>> The GPMC WAIT pin status are now available over gpiolib.
>> Update the omap_dev_ready() function to use gpio instead of
On 21/10/15 18:20, Tony Lindgren wrote:
> * Roger Quadros [151021 01:31]:
>> On 19/10/15 10:08, Roger Quadros wrote:
>>> On 17/10/15 00:25, Tony Lindgren wrote:
>>>> * Roger Quadros [151006 04:13]:
>>>>>
>>>>> Fine. The updated s
On 19/10/15 10:08, Roger Quadros wrote:
> On 17/10/15 00:25, Tony Lindgren wrote:
>> * Roger Quadros [151006 04:13]:
>>>
>>> Fine. The updated series is now at
>>>
>>> g...@github.com:rogerq/linux.git
>>> * [new branch] for-v4.4/gpmc-v
On 17/10/15 00:25, Tony Lindgren wrote:
> * Roger Quadros [151006 04:13]:
>>
>> Fine. The updated series is now at
>>
>> g...@github.com:rogerq/linux.git
>> * [new branch] for-v4.4/gpmc-v4
>
> Looks like it produces some build errors, this
> am37x gp evm
>
> This patchset depends on Roger Quadros recent v4 GPMC/NAND patchset
> https://github.com/rogerq/linux.git
> branch: for-v4.4/gpmc-v4
>
> Franklin S Cooper Jr (5):
> mtd: nand: omap2: Support parsing dma channel information from DT
> mtd: nand: omap2:
WingMan,
On 15/10/15 17:27, WingMan Kwok wrote:
> This patch adds the required PCI serdes bindings whcih can then be
> enabled by setting the corresponding statuses to "ok" in order to
> configure and start the PCI serdes.
>
> This patch depends on the updates to the Keystone PCIe host driver
> a
On 14/10/15 23:03, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 01:13 PM, Tony Lindgren wrote:
>> * Franklin S Cooper Jr. [151014 09:27]:
>>>
>>> On 10/14/2015 11:18 AM, Tony Lindgren wrote:
>>>> * Franklin S Cooper Jr. [151014 07:37]:
>
On 14/10/15 16:34, Franklin S Cooper Jr. wrote:
>
>
> On 09/18/2015 09:53 AM, Roger Quadros wrote:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>&g
On 14/10/15 16:26, Franklin S Cooper Jr. wrote:
>
>
> On 10/14/2015 06:52 AM, Roger Quadros wrote:
>> Franklin,
>>
>> On 14/10/15 14:36, Roger Quadros wrote:
>>> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>>>> Switch from dma_request_channel to
Franklin,
On 14/10/15 14:36, Roger Quadros wrote:
> On 13/10/15 04:38, Franklin S Cooper Jr wrote:
>> Switch from dma_request_channel to allow passing dma channel
>> information from DT rather than hardcoding a value.
>>
>> Signed-off-by: Franklin S Cooper Jr
&
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add additional details to the gpmc and nand documentation to clarify
> what is needed to enable nand dma prefetch.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt | 7
> ++-
>
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Add dma channel information to the gpmc. Although not enabled by
> default this will allow prefetch-dma to be used.
>
> Signed-off-by: Franklin S Cooper Jr
> ---
> arch/arm/boot/dts/am33xx.dtsi | 2 ++
> arch/arm/boot/dts/am4372.dtsi | 2 ++
> arc
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> The prefetch engine sends a dma request once a FIFO threshold has
> been met. No other requests are received until the previous request
> is handled.
>
> Starting an edma transfer (dma_async_issue_pending) results in any
> previous event for the dma
On 13/10/15 04:38, Franklin S Cooper Jr wrote:
> Switch from dma_request_channel to allow passing dma channel
> information from DT rather than hardcoding a value.
>
> Signed-off-by: Franklin S Cooper Jr
Acked-by: Roger Quadros
> ---
> drivers/mtd/nand/omap2.c | 4 +++-
&g
Vignesh,
On 14/10/15 12:12, Vignesh R wrote:
>
>
> On 10/14/2015 02:16 PM, Roger Quadros wrote:
>
>>
>> On 14/10/15 08:52, Vignesh R wrote:
>>> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
>>> state via pinctrl and IO d
: Roger Quadros
---
v4: Applied Tony's patch to fix broken ethernet on torpedo.
updated v4 series available at
g...@github.com:rogerq/linux.git
* [branch] for-v4.4/gpmc-v4
arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts | 3 ++-
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
+Dave
On 14/10/15 08:52, Vignesh R wrote:
> On am437x-gp-evm, pixcir_i2c_ts can wakeup the system from lower power
> state via pinctrl and IO daisy chain using generic wakeirq framework.
> With commit 3fffd1283927 ("i2c: allow specifying separate wakeup
> interrupt in device tree") i2c core allows
Tony,
On 13/10/15 18:18, Tony Lindgren wrote:
> * Roger Quadros [151012 23:33]:
>> On 13/10/15 03:43, Tony Lindgren wrote:
>>> * Roger Quadros [150918 08:00]:
>>>> Add compatible id, GPMC register resource and interrupt
>>>> resource to NAND contr
Ben,
On 13/10/15 11:23, Ben Dooks wrote:
> On 12/10/15 20:19, Tony Lindgren wrote:
>> * Ben Dooks [151012 11:22]:
>>> On 12/10/15 18:45, Tony Lindgren wrote:
* Ben Dooks [151012 10:38]:
> The AM3715 OHCI controller will not function without the EHCI
> unit's 120m fclk being enabled.
On 13/10/15 03:43, Tony Lindgren wrote:
> * Roger Quadros [150918 08:00]:
>> Add compatible id, GPMC register resource and interrupt
>> resource to NAND controller nodes.
>>
>> The GPMC driver now implements gpiochip and irqchip so
>> enable gpio-controller an
On 06/10/15 14:01, Tony Lindgren wrote:
> * Roger Quadros [151006 03:32]:
>> On 06/10/15 13:05, Roger Quadros wrote:
>>> On 06/10/15 13:00, Tony Lindgren wrote:
>>>> * Roger Quadros [151006 02:59]:
>>>>> On 06/10/15 11:33, Tony Lindgren wrote:
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
v4: Warn if using older incompatible DT i.e. compatible property not present
in nand node.
arch/arm/mach
On 06/10/15 13:05, Roger Quadros wrote:
> On 06/10/15 13:00, Tony Lindgren wrote:
>> * Roger Quadros [151006 02:59]:
>>> On 06/10/15 11:33, Tony Lindgren wrote:
>>>> Does build and boot and use NAND work throughtout the series?
>>>> Otherwise we'll
On 06/10/15 13:00, Tony Lindgren wrote:
> * Roger Quadros [151006 02:59]:
>> On 06/10/15 11:33, Tony Lindgren wrote:
>>> Does build and boot and use NAND work throughtout the series?
>>> Otherwise we'll have hard time bisecting anything..
>>
>&g
On 06/10/15 11:33, Tony Lindgren wrote:
> * Roger Quadros [150930 04:04]:
>> Tony,
>>
>> On 18/09/15 17:53, Roger Quadros wrote:
>>> Hi,
>>>
>>> We do a couple of things in this series which result in
>>> cleaner device tree implementation
Tony,
On 18/09/15 17:53, Roger Quadros wrote:
> Hi,
>
> We do a couple of things in this series which result in
> cleaner device tree implementation, faster perfomance and
> multi-platform support. As an added bonus we get new GPI/Interrupt pins
> for use in the system.
>
&
Brian/David,
On 18/09/15 17:53, Roger Quadros wrote:
> Hi,
>
> We do a couple of things in this series which result in
> cleaner device tree implementation, faster perfomance and
> multi-platform support. As an added bonus we get new GPI/Interrupt pins
> for use in the system.
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 ---
include/linux/platform_data/gpmc-omap.h | 137
2 files changed, 137
,
-roger
Changelog:
v3:
-Fixed and tested NAND using legacy boot on omap3-beagle.
-Support rising and falling edge interrupts on WAITpins.
-Update DT node of all gpmc users.
Roger Quadros (27):
ARM: OMAP2+: gpmc: Add platform data
ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform
gpmc_nand_regs. This API will be called by the OMAP NAND driver
to access the necessary bits in GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 21
include/linux/omap-gpmc.h | 49 --
2 files changed, 68
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index a80c53e
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --gi
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 f
write speed is 6537 KiB/s
[ 36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s
Test results on dra7-evm using mtd_speedtest.ko
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 65 +++-
1 file changed, 31 insertions(+), 34
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 130
The WAIT pins support either rising or falling edge interrupts
so add irqchip support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 132 +
1 file changed, 132 insertions(+)
diff --git a/drivers/memory/omap
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand
: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 5 -
arch/arm/boot/dts/dra7.dtsi | 4
arch/arm/boot/dts/dra72-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index a6c82e5..8a31161
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux
: Roger Quadros
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 3 +++
arch/arm/boot/dts/am335x-evm.dts | 3 +++
arch/arm/boot/dts/am335x-igep0033.dtsi | 3 +++
arch/arm/boot/dts/am33xx.dtsi | 4
4 files changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra72
d was unchanged at 9941 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am437x-gp-evm.dts | 3 +--
arch/arm/boot/dts/am43x-epos-evm.dts | 3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arc
: Roger Quadros
---
arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 7 +--
arch/arm/boot/dts/omap3-beagle.dts | 2 ++
arch/arm/boot/dts/omap3-cm-t3x.dtsi| 5 -
arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 3 +++
arch/arm/boot/dts/omap3-evm-37xx.dts | 7
Make gpmc node gpio+interrupt capable.
Add compatible id, interrupt and wait pin to NAND node.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dm8168-evm.dts | 7 ---
arch/arm/boot/dts/dm816x.dtsi| 4
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot
: Roger Quadros
---
arch/arm/boot/dts/am4372.dtsi| 4
arch/arm/boot/dts/am437x-gp-evm.dts | 5 -
arch/arm/boot/dts/am43x-epos-evm.dts | 5 -
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index
d was unchanged at 5100 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/am335x-chilisom.dtsi | 4 +---
arch/arm/boot/dts/am335x-evm.dts | 4 +---
arch/arm/boot/dts/am335x-igep0033.dtsi | 4 +---
3 files changed, 3 insertions(+), 9 deletions(-)
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 163
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
+Tony, Tomi, linux-omap
Hi Pavel,
On 25/08/15 16:39, Pavel Pisa wrote:
> Hello everybody,
>
> I have been asked to help with Linux on Myir Rico board.
> I have decided to try actual stable kernel from Ti tree
>
> git://git.ti.com/ti-linux-kernel/ti-linux-kernel.git
> branch ti-linux-4.1.
On 13/08/15 11:36, Tony Lindgren wrote:
> * Roger Quadros [150813 00:17]:
>> On 11/08/15 15:48, Tony Lindgren wrote:
>>>
>>> OK. Yeah let's make sure no regressions are caused by this.. We also
>>> still have the omap3 legacy booting around, have you chec
On 07/08/15 12:12, Roger Quadros wrote:
> OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
> input if not used for memory wait state insertion.
>
> The first user will be the OMAP NAND chip to get the NAND
> read/busy status using gpiolib.
>
> Signed-
On 07/08/15 12:12, Roger Quadros wrote:
> Instead of accessing the gpmc_status register directly start
> using the gpmc_nand_ops->nand_writebuffer_empty() helper
> to check write buffer empty status.
>
> Signed-off-by: Roger Quadros
> ---
> drivers/mtd/nand/omap2.c | 1
On 11/08/15 15:48, Tony Lindgren wrote:
> * Roger Quadros [150807 02:15]:
>> Hi,
>>
>> We do a couple of things in this series which result in
>> cleaner device tree implementation, faster perfomance and
>> multi-platform support. As an added bonus we get new GPI
Add device_timings, gpmc_timings and gpmc_setting to
gpmc platform data.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 134 --
include/linux/platform_data/gpmc-omap.h | 139
2 files changed, 139 insertions
Add a platform data structure for GPMC. It contains all the necessary
platform information that needs to be passed from platform init code
to GPMC driver.
Signed-off-by: Roger Quadros
---
include/linux/omap-gpmc.h | 3 +--
include/linux/platform_data/gpmc-omap.h | 30
gpmc_nand_regs. This API will be called by the OMAP NAND driver
to access the necessary bits in GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 21 +
include/linux/omap-gpmc.h | 42 --
2 files changed, 61
This is needed by OMAP NAND driver to poll the empty status
of the writebuffer.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c
index 79d78ab
Deprecate nand register passing via platform data and use
gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 2 --
drivers/mtd/nand/omap2.c | 9 -
include/linux/platform_data/mtd-nand-omap2.h | 4 +++-
3
Instead of accessing the gpmc_status register directly start
using the gpmc_nand_ops->nand_writebuffer_empty() helper
to check write buffer empty status.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --gi
NAND IRQs will now be managed directly in the OMAP NAND driver
so remove the IRQchip model.
Another patch will add back GPIO-IRQchip code to handle the
WAITPIN interrupts.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 4 +-
drivers/memory/omap-gpmc.c | 164
Provide functions to enable/disable NAND IRQs, get
NAND event status and clear NAND events.
The NAND events of interest are TERMCOUNT and FIFOEVENT.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 50 ++
include/linux/omap-gpmc.h | 4
Add compatible id and interrupts. The NAND interrupts are
provided by the GPMC controller node.
Signed-off-by: Roger Quadros
---
Documentation/devicetree/bindings/mtd/gpmc-nand.txt | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree
Copy all the platform data parameters to the driver's local data
structure 'omap_nand_info' and use it in the entire driver. This will
make it easer for device tree migration.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 26 ++
1 f
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
TODO: For now only dra7-evm and omap3-beagle are fixed.
Once series is reviewed I'll update this patch to
fix all omap boards.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts
Move NAND specific device tree parsing to NAND driver.
The NAND controller node must have a compatible id, register space
resource and interrupt resource.
Signed-off-by: Roger Quadros
---
arch/arm/mach-omap2/gpmc-nand.c | 5 +-
drivers/memory/omap-gpmc.c | 135
If the device attached to GPMC wants to use the WAIT pin
for WAIT monitoring then we reserve it internally for
exclusive use.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/memory
We have been preventing mapping GPMC children in the
first 1MB but really it has to be the first 16MB as
the minimum GPMC partition size is 16MB.
Also print an error message if CS mapping fails
due to DT requesting address outside the GPMC
map.
Signed-off-by: Roger Quadros
---
drivers/memory
omap-gpmc.c is a memory controller so move the binding to the
right place.
Signed-off-by: Roger Quadros
---
.../bindings/{bus/ti-gpmc.txt => memory-controllers/omap-gpmc.txt}| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{bus/ti-gpmc.
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose
input if not used for memory wait state insertion.
The first user will be the OMAP NAND chip to get the NAND
read/busy status using gpiolib.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 122
The WAIT pins support falling edge interrupts so add irqchip
support to the gpiochip model.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/drivers/memory/omap-gpmc.c b/drivers
The GPMC driver now implements gpiochip and irqchip so
enable gpio-controller and interrupt-controller properties.
With this the interrupt parent of NAND node changes so fix it
accordingly.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra7.dtsi
The GPMC WAIT pin status are now available over gpiolib.
Update the omap_dev_ready() function to use gpio instead of
directly accessing GPMC register space.
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 29 +---
include/linux
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros
---
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra72
GPMC_STATUS register is private to the GPMC module and must not be
accessed directly by NAND driver through the gpmc_regs.
They must use gpmc_omap_get_nand_ops() instead.
Signed-off-by: Roger Quadros
---
drivers/memory/omap-gpmc.c | 2 +-
include/linux/platform_data/mtd-nand
write speed is 6537 KiB/s
[ 36.444842] mtd_speedtest: eraseblock read speed is 10680 KiB/s
Test results on dra7-evm using mtd_speedtest.ko
Signed-off-by: Roger Quadros
---
drivers/mtd/nand/omap2.c | 63 +++-
1 file changed, 30 insertions(+), 33
oards when the series is in a shape to be accepted.
cheers,
-roger
This is done in patches 1 to 14
Roger Quadros (22):
ARM: OMAP2+: gpmc: Add platform data
ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform data
memory: omap-gpmc: Introduce GPMC to NAND interface
mtd: nand: omap2
On 05/08/15 17:18, Kishon Vijay Abraham I wrote:
> Hi Roger,
>
> On Wednesday 05 August 2015 01:55 PM, Roger Quadros wrote:
>> On 05/08/15 11:23, Roger Quadros wrote:
>>>
>>> On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
>>>> The USB2 PHY2 has a
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
> Deprecate using phy-omap-control driver to power on/off the PHY,
> and use *syscon* framework to do the same. This handles
> powering on/off the PHY for the USB2 PHYs used in various TI SoCs.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Doc
On 05/08/15 11:23, Roger Quadros wrote:
>
> On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
>> The USB2 PHY2 has a different register map compared to USB2 PHY1
>> to power on/off the PHY. In order to handle it, add a new
>> "compatible" string.
>>
On 04/08/15 18:20, Kishon Vijay Abraham I wrote:
> The USB2 PHY2 has a different register map compared to USB2 PHY1
> to power on/off the PHY. In order to handle it, add a new
> "compatible" string.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> Documentation/devicetree/bindings/phy/ti-phy.t
On 05/08/15 11:02, Roger Quadros wrote:
> Kishon,
>
> On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
>> Add "syscon-otghs" property and remove the deprecated "ctrl-module"
>> property from MUSB devicetree node.
>>
>> Since "omap_contr
00 0x7ff>;
> @@ -872,7 +866,7 @@
> multipoint = <1>;
> num-eps = <16>;
> ram-bits = <12>;
> - ctrl-module = <&omap_control_usbotg>;
> +
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
> Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
> property from USB PHY dt node.
>
> Since "omap_control_usb2phy" devicetree node is no longer used,
> remove it.
>
> Sign
On 04/08/15 18:30, Kishon Vijay Abraham I wrote:
> Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
> property from SATA PHY node.
>
> Since "omap_control_sata" devicetree node is no longer used, remove it.
>
> Signed-
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