On Wed, Dec 23, 2015 at 06:28:15PM +0530, Rameshswar Prasad Sahu wrote:
> From: Rameshwar Prasad Sahu
>
> For interrupt controller that doesn't support irq_disable and hardware
> with level interrupt, an extra interrupt can be pending. This patch fixes
> the issue by setting IRQ_DISABLE_UNLAZY fl
On Wed, Jan 06, 2016 at 11:05:02AM +0100, Thomas Gleixner wrote:
> On Wed, 6 Jan 2016, Vinod Koul wrote:
> > On Wed, Jan 06, 2016 at 02:51:07PM +0530, Rameshwar Sahu wrote:
> > > >> @@ -1610,6 +1611,7 @@ static int xgene_dma_request_irqs(struct
> > > >> xgen
On Wed, Jan 06, 2016 at 02:51:07PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Wed, Jan 6, 2016 at 2:43 PM, Vinod Koul wrote:
> > On Wed, Dec 23, 2015 at 06:28:15PM +0530, Rameshswar Prasad Sahu wrote:
> >> From: Rameshwar Prasad Sahu
> >>
> >> For
On Wed, Dec 23, 2015 at 06:28:15PM +0530, Rameshswar Prasad Sahu wrote:
> From: Rameshwar Prasad Sahu
>
> For interrupt controller that doesn't support irq_disable and hardware
> with level interrupt, an extra interrupt can be pending. This patch fixes
> the issue by setting IRQ_DISABLE_UNLAZY fl
On Mon, Jan 04, 2016 at 08:37:30PM +0200, Andy Shevchenko wrote:
> > +static int set_priority(struct hidma_mgmt_dev *mdev, unsigned int i, u64
> > val)
> > +{
> > + u64 tmp;
> > + int rc;
> > +
> > + if (i > mdev->dma_channels)
>
> Shouldn't be >= ? I somehow missed that.
Ther
On Sun, Jan 03, 2016 at 07:09:23PM -0500, Sinan Kaya wrote:
> Hi Vinod,
>
> >
>
> Can I have your ACK on your series if you are OK?
Why ACK, shouldn't this be merged thru dmaengine tree? I would need ack on
DT patches first :)
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On Thu, Dec 17, 2015 at 09:48:44AM -0800, Tony Lindgren wrote:
> * Peter Ujfalusi [151217 05:33]:
> > Hi,
> >
> > Changes since v1:
> > - Updated to use the non 16bit arrays [1]
> > - send the two patch as a series
> >
> > [1]
> > As it has been discussed earlier:
> > https://www.mail-archive.co
On Wed, Dec 02, 2015 at 02:53:54PM +0900, Simon Horman wrote:
> In general Renesas hardware is not documented to the extent where the
> relationship between IP blocks on different SoCs can be assumed although
> they may appear to operate the same way. Furthermore the documentation
> typically does
On Wed, Dec 09, 2015 at 01:10:18PM +0200, Peter Ujfalusi wrote:
> Hi Arnd, Vinod,
>
> As Arnd suggested, the two patch from the following series:
> https://www.mail-archive.com/linux-omap@vger.kernel.org/msg122201.html
>
> plus Acked-by from Arnd is available for pull if you prefer that way.
Sor
On Wed, Dec 09, 2015 at 12:12:27PM -0800, Tony Lindgren wrote:
> * Peter Ujfalusi [151209 00:19]:
> > Hi,
> >
> > Based on the discussion regarding to (convert am33xx to use the new eDMA
> > bindings):
> > https://www.mail-archive.com/linux-omap@vger.kernel.org/msg122117.html
> >
> > This two pa
On Fri, Oct 30, 2015 at 10:00:35AM +0200, Peter Ujfalusi wrote:
> Hi,
>
> Changes since v1:
> - Fixed issue introduced by the bitops patch: wrong error check, also switch
> to
> use find_first_zero_bit() instead of find_next_zero_bit()
>
> Cover letter:
>
> This series depends on the eDMA wor
On Wed, Nov 18, 2015 at 04:51:54PM +0100, Arnd Bergmann wrote:
> On Wednesday 18 November 2015 17:43:04 Andy Shevchenko wrote:
> > >
> > > I assume that the sst-firmware.c case is a mistake, it should just use a
> > > plain DMA_SLAVE and not DMA_MEMCPY.
> >
> > Other way around.
> >
>
> Ok, I se
On Thu, Nov 12, 2015 at 10:53:59AM +0900, Simon Horman wrote:
> In general Renesas hardware is not documented to the extent where the
> relationship between IP blocks on different SoCs can be assumed although
> they may appear to operate the same way. Furthermore the documentation
> typically does
On Tue, Nov 03, 2015 at 12:28:10PM +0200, Peter Ujfalusi wrote:
> of_dma_request_slave_channel should return either pointer for valid
> dma_chan or ERR_PTR() error code, NULL is not expected to be returned.
Applied, thanks
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On Fri, Oct 16, 2015 at 03:59:15PM +0200, M'boumba Cedric Madianga wrote:
> This patch adds STM32 DMA bindings for STM32F429.
I need an ACK from ARM folks on this one, and I suspect this might need
rebase on 4.4-rc1
>
> Signed-off-by: M'boumba Cedric Madianga
> ---
> arch/arm/boot/dts/stm32f42
On Fri, Oct 16, 2015 at 03:59:16PM +0200, M'boumba Cedric Madianga wrote:
> This patch adds STM32 DMA support in stm32_defconfig file
This seems okay, so went ahead and applied
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On Fri, Oct 16, 2015 at 03:59:14PM +0200, M'boumba Cedric Madianga wrote:
> This patch adds support for the STM32 DMA controller.
>
Applied, thanks
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More major
On Fri, Oct 16, 2015 at 03:59:13PM +0200, M'boumba Cedric Madianga wrote:
> This patch adds documentation of device tree bindings for the STM32 dma
> controller.
>
Applied, thanks
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On Wed, Nov 04, 2015 at 10:33:27AM -0600, Felipe Balbi wrote:
> Peter Ujfalusi writes:
>
> > The eDMA3 TPTC does not need any software configuration, but it is a
> > separate IP block in the SoC. In order the omap hwmod core to be able to
> > handle the TPTC resources correctly in regards of PM w
On Mon, Nov 02, 2015 at 05:46:05PM +0200, Peter Ujfalusi wrote:
> > Okay I have reverted the two and applied the edma patch sent, can you please
> > verify topic/edma_fix before I merge it and send my PULL request.
>
> The branch looks good. Thank you!
> It would have been great if the DTS changes
On Mon, Nov 02, 2015 at 02:13:01PM +0200, Peter Ujfalusi wrote:
> Vinod,
>
> On 11/02/2015 12:04 PM, Vinod Koul wrote:
> > On Mon, Nov 02, 2015 at 01:21:19AM -0800, Olof Johansson wrote:
> >> Hi,
> >>
> >> 1) This seems to have broken BBB in -next
On Mon, Nov 02, 2015 at 12:11:00PM +0200, Peter Ujfalusi wrote:
> In Linux we do not have driver for TPTCs of eDMA3 since there is no need to
> do any configuration within TPTC for the eDMA3 to be operational. All
> configuration is via the TPCC.
> To prevent the omap_device_late_idle() to disable
On Mon, Nov 02, 2015 at 01:21:19AM -0800, Olof Johansson wrote:
> Hi,
>
> 1) This seems to have broken BBB in -next for me, bisected down to this patch.
>
> For bootlog:
> http://arm-soc.lixom.net/bootlogs/next/next-20151102/bbb-arm-omap2plus_defconfig.html
>
> 2) Please avoid merging DT/platfor
On Tue, Oct 27, 2015 at 11:42:57PM +0300, Alexander Popov wrote:
> >> Hello,
> >>
> >> I've done my best to fix the issues pointed by Timur Tabi and Vinod Koul.
> >> Could I have a feedback please?
> >
> > I dont see to have v4 in my list :( Ca
peripheral devices on LocalPlus Bus.
>
> > Changes in v4:
> > - the race condition is fixed;
> > - plenty of style fixes are made;
> > - devm_* functions and EPROBE_DEFER are used in probe().
>
> Hello,
>
> I've done my best to fix the issues pointed by Tim
On Fri, Oct 16, 2015 at 10:17:58AM +0300, Peter Ujfalusi wrote:
> Hi,
>
> Changes since v1:
> - Comments in the memcpy optimization patch extended
> - The crossbar patch has been improved:
> - debug prints changed
> - fallback xbar parameters now type specific as the fallback values for DRA7
>
On Wed, Oct 14, 2015 at 05:41:26PM +0200, M'boumba Cedric Madianga wrote:
> 2015-10-14 17:28 GMT+02:00 Daniel Thompson :
> > On 14/10/15 16:26, M'boumba Cedric Madianga wrote:
> >>
> >> 2015-10-14 16:24 GMT+02:00 Daniel Thompson :
> >>>
> >>>
> >>> Hmnnn...
> >>>
> >>> The dmaengine framework will
On Wed, Oct 14, 2015 at 06:02:18PM +0300, Peter Ujfalusi wrote:
> On 10/14/2015 05:41 PM, Vinod Koul wrote:
> > On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
> >> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
> >> *edma_prep_dma_memc
On Wed, Oct 14, 2015 at 07:25:07PM +0530, Rameshwar Prasad Sahu wrote:
> The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other
> computations. But the bandwidth of the entire DMA engine is shared
> among all channels. This patch re-configures operations availability
> such that one ca
On Wed, Oct 14, 2015 at 04:12:21PM +0300, Peter Ujfalusi wrote:
> The DMA event crossbar on AM33xx/AM43xx is different from the one found in
> DRA7x family.
> Instead of a single event crossbar it has 64 identical mux attached to each
> eDMA event line. When the 0 event mux is selected, the default
On Wed, Oct 14, 2015 at 04:12:13PM +0300, Peter Ujfalusi wrote:
> @@ -1320,41 +1317,92 @@ static struct dma_async_tx_descriptor
> *edma_prep_dma_memcpy(
> struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
> size_t len, unsigned long tx_flags)
> {
> - int ret;
> + int ret
On Wed, Oct 14, 2015 at 03:07:16PM +0200, M'boumba Cedric Madianga wrote:
> >> +static inline uint32_t stm32_dma_read(struct stm32_dma_device *dmadev,
> >> u32 reg)
> >
> > this and few other could be made more readable
>
> Ok, I could replace uint32_t by u32. Is it what you expect ?
> For others
On Tue, Oct 13, 2015 at 04:05:25PM +0200, M'boumba Cedric Madianga wrote:
> +#define STM32_DMA_LISR 0x /* DMA Low Int Status
> Reg */
> +#define STM32_DMA_HISR 0x0004 /* DMA High Int Status
> Reg */
> +#define STM32_DMA_LIFCR 0x
On Fri, Oct 09, 2015 at 10:08:32PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Fri, Oct 9, 2015 at 9:42 PM, Vinod Koul wrote:
> > On Thu, Oct 08, 2015 at 02:36:57PM +0530, Rameshwar Prasad Sahu wrote:
> >> The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and
On Thu, Oct 08, 2015 at 02:36:57PM +0530, Rameshwar Prasad Sahu wrote:
> The DMA engine supports memory copy, RAID5 XOR, RAID6 PQ, and other
> computations. But the bandwidth of the entire DMA engine is shared
> among all channels. This patch re-configures operations availability
> such that one ca
On Thu, Sep 24, 2015 at 08:28:57PM +0300, Alexander Popov wrote:
> Initialize Freescale MPC512x DMA driver with subsys_initcall()
> to allow the depending drivers to call dma_request_slave_channel()
> during their probe.
Why can't we use defered probe ? I have been asking people to not move init
l
On Fri, Sep 11, 2015 at 03:14:28PM +0100, Peter Griffin wrote:
> +#define ST_FDMA_PM (&st_fdma_pm)
> +#else
> +#define ST_FDMA_PM NULL
> +#endif
Pls use PM helpers you dont need to do this
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On Fri, Sep 11, 2015 at 03:14:27PM +0100, Peter Griffin wrote:
> This patch adds the code to load the xp70 fdma firmware
> using the asynchronous request_firmware_nowait call
> so as not to delay bootup of builtin code.
Okay we need to check here. Can the driver be built in, if so this is not
the
On Fri, Sep 11, 2015 at 03:14:26PM +0100, Peter Griffin wrote:
> +static char *fdma_clk_name[CLK_MAX_NUM] = {
> + [CLK_SLIM] = "fdma_slim",
> + [CLK_HI]= "fdma_hi",
> + [CLK_LOW] = "fdma_low",
> + [CLK_IC]= "fdma_ic",
> +};
why do we want to have this so
On Fri, Sep 11, 2015 at 01:53:52PM +0800, Yuan Yao wrote:
> +Examples:
> +
> + qdma: qdma@839 {
> + compatible = "fsl,ls-qdma";
> + reg = <0x0 0x838 0x0 0x2>;
> + interrupts = ,
> + ;
> + interrupt-names =
On Wed, Sep 16, 2015 at 01:33:23PM +0530, Rameshwar Prasad Sahu wrote:
> This patch fixes an over flow issue with the TX ring descriptor. Each
> descriptor is 32B in size and an operation requires 2 of these
> descriptors.
Applied, thanks
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On Thu, Aug 27, 2015 at 09:19:18PM +0530, Anurag Kumar Vulisha wrote:
> This VDMA is a soft ip, which can be programmed to support
> 32 bit addressing or greater than 32 bit addressing.
>
> When the VDMA ip is configured for 32 bit address space the
> transfer start address is specified by a sing
On Mon, Aug 24, 2015 at 02:22:49PM +0100, Jon Hunter wrote:
>
> On 24/08/15 10:22, Vinod Koul wrote:
> > On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
> >>
> >> On 23/08/15 15:17, Vinod Koul wrote:
> >>> On Tue, Aug 18,
On Mon, Aug 24, 2015 at 09:55:03AM +0100, Jon Hunter wrote:
> >> +static int tegra_adma_get_xfer_params(struct tegra_dma_channel *tdc,
> >> +struct tegra_adma_chan_regs *ch_regs,
> >> +enum dma_transfer_direction direction)
> >> +{
> >
On Mon, Aug 24, 2015 at 09:47:13AM +0100, Jon Hunter wrote:
>
> On 23/08/15 15:17, Vinod Koul wrote:
> > On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> >
> >> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> >>int
On Tue, Aug 18, 2015 at 02:49:15PM +0100, Jon Hunter wrote:
> +#define AHUB_TO_MEMORY 2
> +#define MEMORY_TO_AHUB 4
namespace this aptly as well
> +static void tegra_adma_stop(struct tegra_dma_channel *tdc
On Tue, Aug 18, 2015 at 02:49:09PM +0100, Jon Hunter wrote:
> @@ -1543,7 +1531,7 @@ static int tegra_dma_pm_suspend(struct device *dev)
> int ret;
>
> /* Enable clock before accessing register */
> - ret = tegra_dma_runtime_resume(dev);
> + ret = pm_runtime_get_sync(dev);
wh
On Thu, Aug 20, 2015 at 12:01:27PM +0530, punnaiah choudary kalluri wrote:
> On Thu, Aug 20, 2015 at 11:43 AM, Vinod Koul wrote:
> > On Thu, Aug 06, 2015 at 08:49:33AM +0530, Punnaiah Choudary Kalluri wrote:
> >
> >> + list_for_each_entry_safe(desc, next
On Thu, Aug 20, 2015 at 05:39:12PM +0200, Lars-Peter Clausen wrote:
> Add the devicetree descriptor for the Analog Devices AXI-DMAC DMA
> controller. This is a soft peripheral used in FPGAs and the bindings
> describe how it is connected to the system (clock, interrupt, memory map)
> as well as the
On Fri, Aug 21, 2015 at 02:33:34PM +0530, Rameshwar Prasad Sahu wrote:
> This patch provides the fix in the cleanup routing such that client can
> perform
> further submission by releasing the lock before calling client's callback
> function.
Applied, thanks
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On Fri, Aug 21, 2015 at 02:15:08PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Fri, Aug 21, 2015 at 2:09 PM, Vinod Koul wrote:
> > On Thu, Aug 20, 2015 at 04:00:56PM +0530, Rameshwar Prasad Sahu wrote:
> >> This patch fixes the an locking issue where
On Thu, Aug 20, 2015 at 04:00:56PM +0530, Rameshwar Prasad Sahu wrote:
> This patch fixes the an locking issue where client callback performs
??
> further submission.
Do you men you are preventing that or fixing for this to be allowed?
>
> Signed-off-by: Rameshwar Pr
On Thu, Aug 20, 2015 at 12:23:50PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 11:10 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
> >> + /* Invalidate unused source address field */
&g
On Thu, Aug 20, 2015 at 12:31:44PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 11:18 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
> >> + nents = sg_nents(req->src);
> >> +
On Thu, Aug 20, 2015 at 11:59:07AM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 10:56 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
> >> This patch adds support for new feature CRC32C calcu
On Tue, Jul 21, 2015 at 06:44:39PM +0530, Rameshwar Prasad Sahu wrote:
> This patch adds ACPI support for the APM X-Gene DMA engine driver.
Applied, thanks
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Mo
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
> >> +- interrupts: Should contain DMA channel interrupt
> > channel interrupt or interrupts, former says it is plural
>
> ZynqMP DMA has single interrupt for each channel So, that is the reason
> i have explicitly mentione
On Thu, Aug 06, 2015 at 08:49:33AM +0530, Punnaiah Choudary Kalluri wrote:
> + list_for_each_entry_safe(desc, next, &chan->done_list, node) {
> + dma_async_tx_callback callback;
> + void *callback_param;
> +
> + list_del(&desc->node);
> +
> + cal
On Thu, Aug 06, 2015 at 08:49:32AM +0530, Punnaiah Choudary Kalluri wrote:
> Device-tree binding documentation for Xilinx zynqmp dma engine used in
> Zynq UltraScale+ MPSoC.
>
> Signed-off-by: Punnaiah Choudary Kalluri
> ---
> Changes in v4:
> - None
> Changes in v3:
> - None
> Changes in v2:
> -
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
> + nents = sg_nents(req->src);
> + sg_count = dma_map_sg(dev, req->src, nents, DMA_TO_DEVICE);
> + if (!sg_count) {
> + dev_err(dev, "Failed to map src sg");
> + return -ENOMEM;
mapping error
On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
> + /* Invalidate unused source address field */
> + for (; i < 4; i++)
> + xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
> +
> + /* Check whether requested buffer processed */
> + if
On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
> This patch adds support for new feature CRC32C calculation in
> dmaengine framework.
Looks okay can you please update Documentation also
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On Wed, Aug 19, 2015 at 07:44:10PM +0200, Lars-Peter Clausen wrote:
> On 08/19/2015 07:12 PM, Vinod Koul wrote:
> > On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> >>> where is device side programming ?
> >>
> >> in the start_transfer(
mac_write(dmac, AXI_DMAC_REG_X_LENGTH, sg->x_len - 1);
> + axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, sg->y_len - 1);
> + axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, flags);
> + axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 1);
> +}
On Wed, Aug 19, 2
On Tue, Jul 28, 2015 at 11:38:06AM +0200, Lars-Peter Clausen wrote:
> + active = axi_dmac_active_desc(chan);
> + if (!active)
> + return;
> +
> + if (active->cyclic) {
> + vchan_cyclic_callback(&active->vdesc);
> + } else {
> + while (active &&
do
On Wed, Jul 08, 2015 at 05:11:24PM +0100, Peter Griffin wrote:
> +static int
> +st_fdma_elf_sanity_check(struct st_fdma_dev *fdev, const struct firmware *fw)
> +{
> + const char *fw_name = fdev->pdata->fw_name;
> + struct elf32_hdr *ehdr;
> + char class;
> +
> + if (!fw) {
> +
On Wed, Jul 08, 2015 at 05:11:22PM +0100, Peter Griffin wrote:
> This patch adds the DT binding documentation for the FDMA constroller
> found on STi based chipsets from STMicroelectronics.
>
> Signed-off-by: Ludovic Barre
> Signed-off-by: Peter Griffin
> ---
> Documentation/devicetree/bindings
On Sat, Jul 11, 2015 at 02:12:03PM +0200, Joachim Eastwood wrote:
> Hi Vinod,
>
> This is the non-RFC version of the patch set with only a few changes.
> Hope this can go in for 4.3. Changes to the DT for LPC18xx/43xx will
> go thru arm-soc once this get accepted.
>
>
> This patch set aims to ad
On Tue, Jul 21, 2015 at 10:14:11AM +0200, Michal Suchanek wrote:
> > Or alternatively we could publish the limitations of the channel using
> > capabilities so SPI knows I have a dmaengine channel and it can transfer
> > max N
> > length transfers so would be able to break rather than guessing it
On Sun, Jul 19, 2015 at 09:01:34PM +0200, Michal Suchanek wrote:
> Hello,
>
> On 15 July 2015 at 17:59, Brian Norris wrote:
> > Hi Michal,
> >
> > On Wed, Jul 15, 2015 at 01:52:27PM +0200, Marek Vasut wrote:
> >> The problem is, if you add a new DT binding, you'd have to support it
> >> forever,
On Fri, Jul 17, 2015 at 09:54:48AM +0530, punnaiah choudary kalluri wrote:
your MUA is wrapping lines funny, please fix it
> >> I have explored using the virt-dma to reduce the common list processing,
> >> But
> >> in this driver descriptor processing and cleaning is happening inside
> >> the tas
On Fri, Jul 17, 2015 at 06:22:42AM +0530, punnaiah choudary kalluri wrote:
> On Thu, Jul 16, 2015 at 6:05 PM, Vinod Koul wrote:
> > On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote:
> >> +/* Register Offsets */
> >> +#define ISR
On Tue, Jul 07, 2015 at 03:34:25PM +0530, Rameshwar Prasad Sahu wrote:
> There is an overlap in dma ring cmd csr region due to sharing of ethernet
> ring cmd csr region. This patch fix the resource overlapping by mapping
> the entire dma ring cmd csr region.
Applied thanks
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On Tue, Jun 16, 2015 at 08:04:43AM +0530, Punnaiah Choudary Kalluri wrote:
> +/* Register Offsets */
> +#define ISR 0x100
> +#define IMR 0x104
> +#define IER 0x108
> +#define IDS 0x10C
> +#define CTR
On Tue, Jun 30, 2015 at 02:27:27PM +0200, Paul Osmialowski wrote:
The patch title is not per subsystem semantics, pls fix that
> Surprisingly small amount of work was required in order to extend already
> existing eDMA driver with the support for Kinetis SoC architecture.
And this doesn't tell me
On Mon, Jun 22, 2015 at 02:31:00PM +0300, Peter Ujfalusi wrote:
> On 06/12/2015 03:58 PM, Vinod Koul wrote:
> > Sorry this slipped thru
>
> I was away for a week anyways ;)
>
> > Thinking about it again, I think we should coverge to two APIs and mark the
> >
On Tue, Jun 23, 2015 at 11:19:46PM +0200, Paul Osmialowski wrote:
> Surprisingly small amount of work was required in order to extend already
> existing eDMA driver with the support for Kinetis SoC architecture.
>
> Note that is needed (which is denoted by
> CONFIG_NEED_MACH_MEMORY_H) as it provi
On Thu, Jun 04, 2015 at 06:58:06PM +0300, Peter Ujfalusi wrote:
> Vinod,
>
> On 06/02/2015 03:55 PM, Vinod Koul wrote:
> > On Fri, May 29, 2015 at 05:32:50PM +0300, Peter Ujfalusi wrote:
> >> On 05/29/2015 01:18 PM, Vinod Koul wrote:
> >>> On Fri, May
On Wed, Jun 03, 2015 at 09:26:41PM +, Michal Suchanek wrote:
> The kernel is not trying to increase mcbufsz. It suggests you should try
> doing so. Also print the calculated required size of mcbufsz.
pls use right subsystem name in the patches
I have applied this now
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On Tue, Jun 02, 2015 at 02:33:33PM +0530, Rameshwar Prasad Sahu wrote:
> This patch fixes sparse warnings like incorrect type in assignment
> (different base types), cast to restricted __le64.
>
I am appliying this but ideally you should have split thsi into seprate
patches for each fix
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On Fri, May 29, 2015 at 05:32:50PM +0300, Peter Ujfalusi wrote:
> On 05/29/2015 01:18 PM, Vinod Koul wrote:
> > On Fri, May 29, 2015 at 11:42:27AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 29, 2015 at 11:33 AM, Vinod Koul wrote:
> >>> On Tue, May 26, 2
On Fri, May 29, 2015 at 11:42:27AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 29, 2015 at 11:33 AM, Vinod Koul wrote:
> > On Tue, May 26, 2015 at 04:25:57PM +0300, Peter Ujfalusi wrote:
> >> dma_request_slave_channel_compat() 'eats' up the returned error codes
On Tue, May 26, 2015 at 04:25:57PM +0300, Peter Ujfalusi wrote:
> dma_request_slave_channel_compat() 'eats' up the returned error codes which
> prevents drivers using the compat call to be able to do deferred probing.
>
> The new wrapper is identical in functionality but it will return with error
On Wed, May 06, 2015 at 11:31:31AM +0200, Jens Kuske wrote:
> The H3 SoC has the same dma engine as the A31 (sun6i), with a
> reduced amount of endpoints and physical channels. Add the proper
> config data and compatible string to support it.
Applied, thanks
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On Mon, Apr 20, 2015 at 08:38:18AM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>> >> @@ -2085,6 +2043,5 @@ module_platform_driver(xgene_dma_driver);
> >>
> >> MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
> >> MODULE_AUTHOR("Rameshwar Prasad Sahu ");
> >> -MODULE_AUTHOR("Loc Ho ");
> > And why th
> /* Get DMA error interrupt */
> @@ -2076,7 +2035,6 @@ static struct platform_driver xgene_dma_driver = {
> .remove = xgene_dma_remove,
> .driver = {
> .name = "X-Gene-DMA",
> - .owner = THIS_MODULE,
I have already applied a patch for this
>
On Wed, Mar 18, 2015 at 07:17:33PM +0530, Rameshwar Prasad Sahu wrote:
> This patch set implements the APM X-Gene SoC DMA driver support to offload
> the DMA operations such as memory copy(memcpy), scatter gather memory copy,
> raid5 xor and raid6 p+q.
Applied, now
Thanks
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On Wed, Apr 01, 2015 at 03:22:43PM +0900, Yoshihiro Shimoda wrote:
> This patch set is based on slave-dma.git / next branch.
> (commit id = 739e9c81155e74ca7acfa152eea4e8c055fe35b8)
Applied, thanks
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>
> Changes from v3:
> - Call devm_free_irq() in usb_dmac_chan_remove() to prevent the
On Mon, Mar 23, 2015 at 02:32:07AM +, yoshihiro shimoda wrote:
> > > > > +static void usb_dmac_chan_remove(struct usb_dmac_chan *uchan)
> > > > > +{
> > > > > + tasklet_kill(&uchan->task);
> > > > that part is good, but how about disabling irq? you can still get
> > > > insterrupt
> > >
>
On Tue, Mar 17, 2015 at 12:46:12AM -0500, Andy Gross wrote:
> +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t
> cookie,
> + struct dma_tx_state *txstate)
> +{
> + struct adm_chan *achan = to_adm_chan(chan);
> + struct virt_dma_desc *vd;
> + enum dma_statu
On Wed, Mar 18, 2015 at 04:16:34PM +, Zubair Lutfullah Kakakhel wrote:
> Hi,
>
> Here we have three patches that add a DMA driver for the Ingenic JZ4780 SoC.
>
> JZ4780 support is still in-flight.
>
> These are based on 4.0-rc4.
Applied, thanks
Please ensure you use the right subsystem nam
On Fri, Mar 27, 2015 at 02:25:29PM +0200, Peter Ujfalusi wrote:
> On 03/26/2015 05:32 PM, Vinod Koul wrote:
> >> I have added the DT binding document since this series adds support for
> >> routers for platforms booting with DT:
> >>
> >> Documentati
On Thu, Mar 26, 2015 at 02:31:30PM +0200, Peter Ujfalusi wrote:
> On 03/26/2015 12:56 PM, Vinod Koul wrote:
> >> +#define TI_XBAR_OUTPUTS 127
> >> +#define TI_XBAR_INPUTS256
> > Ideally this should be moved to DT. Will next revision of this chip always
> >
On Thu, Mar 26, 2015 at 02:11:38PM +0200, Peter Ujfalusi wrote:
> On 03/26/2015 12:50 PM, Vinod Koul wrote:
> > On Wed, Mar 11, 2015 at 03:23:24PM +0200, Peter Ujfalusi wrote:
> >> DMA routers are transparent devices used to mux DMA requests from
> >> peripherals to DMA
On Wed, Mar 11, 2015 at 03:23:27PM +0200, Peter Ujfalusi wrote:
> Instead of magic numbers in the code, use define for number of logical DMA
> channels and DMA requests.
>
> Signed-off-by: Peter Ujfalusi
> ---
> drivers/dma/omap-dma.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-
On Wed, Mar 11, 2015 at 03:23:26PM +0200, Peter Ujfalusi wrote:
> The DRA7x has more peripherals with DMA requests than the sDMA can handle:
> 205 vs 127. All DMA requests are routed through the DMA crossbar, which can
> be configured to route selected incoming DMA requests to specific sDMA
> reque
On Wed, Mar 11, 2015 at 03:23:24PM +0200, Peter Ujfalusi wrote:
> DMA routers are transparent devices used to mux DMA requests from
> peripherals to DMA controllers. They are used when the SoC integrates more
> devices with DMA requests then their controller can handle.
> DRA7x is one example of su
On Thu, Mar 19, 2015 at 08:12:57AM +, yoshihiro shimoda wrote:
> Hi Vinod,
>
> Thank you for your review!
>
> > On Wed, Mar 11, 2015 at 02:39:54PM +0900, Yoshihiro Shimoda wrote:
> > > +static struct dma_async_tx_descriptor *
> > > +usb_dmac_prep_slave_sg(struct dma_chan *chan, struct scatter
On Tue, Mar 17, 2015 at 06:07:36PM +, Zubair Lutfullah Kakakhel wrote:
> >> +static uint32_t jz4780_dma_transfer_size(unsigned long val, int *ord)
> >> +{
> >> + *ord = ffs(val) - 1;
> >> +
> >> + /* 8 byte transfer sizes unsupported so fall back on 4. */
> > okay falling back is not a good i
On Wed, Mar 11, 2015 at 02:39:54PM +0900, Yoshihiro Shimoda wrote:
> +static struct dma_async_tx_descriptor *
> +usb_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
> +unsigned int sg_len, enum dma_transfer_direction dir,
> +unsigned long d
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